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execute.s
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execute.s
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.equ fast, 1
.data
.global st, sttap, stint, counter, mem, v, intr, tap, pc, start, endd
.global sp, mp, t, u, ff, ff_, fa, fa_, fb, fb_, fr, fr_
.global a, c, b, e, d, l, h, a_, c_, b_, e_, d_, l_, h_
.global xl, xh, yl, yh, i, r, rs, prefix, iff, im, w, halted
.align
st: .word 0
sthi: .word 0
sttap: .quad 0
stint: .quad 0
counter:.quad 100000000
v: .word 0
intr: .word 0
tap: .word 0
mem: .word 0
ff: .short 0
pc: .short 0
fa: .short 0
sp: .short 0
fb: .short 0
c: .byte 0
b: .byte 0
fr: .short 0
e: .byte 0
d: .byte 0
mp: .short 0
l: .byte 0
h: .byte 0
prefix: .byte 0
rs: .byte 0
r: .byte 0
a: .byte 0
start: .short 0
xl: .byte 0
xh: .byte 0
dummy2: .byte 0
i: .byte 0
yl: .byte 0
yh: .byte 0
t: .short 0
u: .short 0
fa_: .short 0
fb_: .short 0
ff_: .short 0
fr_: .short 0
c_: .byte 0
b_: .byte 0
e_: .byte 0
d_: .byte 0
dummy1: .short 0
l_: .byte 0
h_: .byte 0
endd: .short 0
a_: .byte 0
im: .byte 0
iff: .byte 0
halted: .byte 0
w: .byte 0
.equ ost, -44
.equ osthi, 4+ost
.equ osttap, 4+osthi
.equ ostint, 8+osttap
.equ ocounter, 8+ostint
.equ ov, 8+ocounter
.equ ointr, 4+ov
.equ otap, 4+ointr
.equ omem, 4+otap
.equ off, 4+omem
.equ opc, 2+off
.equ ofa, 2+opc
.equ osp, 2+ofa
.equ ofb, 2+osp
.equ oc, 2+ofb
.equ ob, 1+oc
.equ ofr, 1+ob
.equ oe, 2+ofr
.equ od, 1+oe
.equ omp, 1+od
.equ ol, 2+omp
.equ oh, 1+ol
.equ oprefix, 1+oh
.equ ors, 1+oprefix
.equ or, 1+ors
.equ oa, 1+or
.equ ostart, 1+oa
.equ oxl, 2+ostart
.equ oxh, 1+oxl
.equ odummy2, 1+oxh
.equ oi, 1+odummy2
.equ oyl, 1+oi
.equ oyh, 1+oyl
.equ ot, 1+oyh
.equ ou, 2+ot
.equ ofa_, 2+ou
.equ ofb_, 2+ofa_
.equ off_, 2+ofb_
.equ ofr_, 2+off_
.equ oc_, 2+ofr_
.equ ob_, 1+oc_
.equ oe_, 1+ob_
.equ od_, 1+oe_
.equ odummy1, 1+od_
.equ ol_, 2+odummy1
.equ oh_, 1+ol_
.equ oendd, 1+oh_
.equ oa_, 2+oendd
.equ oim, 1+oa_
.equ oiff, 1+im
.equ ohalted, 1+oiff
.equ ow, 1+ohalted
punt .req r0
mem .req r1
stlo .req r2
pcff .req r3
spfa .req r4
bcfb .req r5
defr .req r6
hlmp .req r7
arvpref .req r8
ixstart .req r9
iyi .req r12
.macro TIME cycles
adds stlo, stlo, #\cycles
blcs insth
.endm
.macro PREFIX0
.if fast==0
bic arvpref, #0xff
.endif
b salida
.endm
.macro PREFIX1
.if fast==0
bic arvpref, #0xff
add arvpref, arvpref, #1
.endif
b salida
.endm
.macro PREFIX2
.if fast==0
orr arvpref, #0xff
.endif
b salida
.endm
.macro LDRRIM regis
TIME 10
ldr lr, [mem, pcff, lsr #16]
add pcff, #0x00020000
pkhbt \regis, \regis, lr, lsl #16
PREFIX0
.endm
.macro LDRIM regis, ofs
TIME 7
bic \regis, #0x00ff0000 << \ofs
ldrb lr, [mem, pcff, lsr #16]
add pcff, #0x00010000
orr \regis, lr, lsl #16+\ofs
PREFIX0
.endm
.macro LDRRPNN regis, cycl
TIME \cycl
ldr lr, [mem, pcff, lsr #16]
mov lr, lr, lsl #16
ldr r11, [mem, lr, lsr #16]
pkhbt \regis, \regis, r11, lsl #16
add pcff, #0x00020000
add lr, #0x00010000
pkhtb hlmp, hlmp, lr, asr #16
PREFIX0
.endm
.macro LDPNNRR regis, cycl
TIME \cycl
ldr lr, [mem, pcff, lsr #16]
uxtah r11, mem, lr
mov r10, \regis, lsr #16
strh r10, [r11]
add pcff, #0x00020000
add lr, #0x00000001
pkhtb hlmp, hlmp, lr
.endm
.macro LDXX dst, ofd, src, ofs
TIME 4
bic \dst, #0x00ff0000 << \ofd
and lr, \src, #0x00ff0000 << \ofs
.if \ofs-\ofd==-8
orr \dst, lr, ror #24
.else
orr \dst, lr, ror #\ofs-\ofd
.endif
PREFIX0
.endm
.macro INC regis, ofs
TIME 4
.if \ofs==0
and lr, \regis, #0x00ff0000
pkhtb spfa, spfa, lr, asr #16
.else
mov lr, \regis, lsr #24
pkhtb spfa, spfa, lr
.endif
mov lr, #0x00000001
pkhtb bcfb, bcfb, lr
uadd8 lr, lr, spfa
bic \regis, #0x00ff0000 << \ofs
orr \regis, \regis, lr, lsl #16+\ofs
pkhtb defr, defr, lr
and r11, pcff, #0x00000100
orr lr, r11
pkhtb pcff, pcff, lr
PREFIX0
.endm
.macro DEC regis, ofs
TIME 4
.if \ofs==0
and lr, \regis, #0x00ff0000
pkhtb spfa, spfa, lr, asr #16
.else
mov lr, \regis, lsr #24
pkhtb spfa, spfa, lr
.endif
mov lr, #0xffff00ff
pkhtb bcfb, bcfb, lr, asr #16
uadd8 lr, lr, spfa
bic \regis, #0x00ff0000 << \ofs
orr \regis, \regis, lr, lsl #16+\ofs
pkhtb defr, defr, lr
and r11, pcff, #0x00000100
orr lr, r11
pkhtb pcff, pcff, lr
PREFIX0
.endm
.macro INCPI regis
TIME 19
add r11, lr, \regis, lsr #16
ldrb lr, [mem, r11]
pkhtb spfa, spfa, lr
mov lr, #0x00000001
pkhtb bcfb, bcfb, lr
add lr, spfa
strb lr, [mem, r11]
uxtb lr, lr
pkhtb defr, defr, lr
and r11, pcff, #0x00000100
orr lr, r11
pkhtb pcff, pcff, lr
PREFIX0
.endm
.macro DECPI regis
TIME 19
add r11, lr, \regis, lsr #16
ldrb lr, [mem, r11]
pkhtb spfa, spfa, lr
mov lr, #0xffffffff
pkhtb bcfb, bcfb, lr
add lr, spfa
strb lr, [mem, r11]
uxtb lr, lr
pkhtb defr, defr, lr
and r11, pcff, #0x00000100
orr lr, r11
pkhtb pcff, pcff, lr
PREFIX0
.endm
.macro XADD regis, ofs, cycl
TIME \cycl
mov r11, arvpref, lsr #24
pkhtb spfa, spfa, r11
.if \ofs==0
and lr, \regis, #0x00ff0000
pkhtb bcfb, bcfb, lr, asr #16
.else
.if \ofs<24
mov lr, \regis, lsr #24
.endif
pkhtb bcfb, bcfb, lr
.endif
add lr, spfa, bcfb
pkhtb pcff, pcff, lr
uxtb lr, lr
bic arvpref, #0xff000000
orr arvpref, lr, lsl #24
pkhtb defr, defr, lr
PREFIX0
.endm
.macro XADC regis, ofs, cycl
TIME \cycl
mov r11, arvpref, lsr #24
pkhtb spfa, spfa, r11
.if \ofs==0
and lr, \regis, #0x00ff0000
pkhtb bcfb, bcfb, lr, asr #16
.else
.if \ofs<24
mov lr, \regis, lsr #24
.endif
pkhtb bcfb, bcfb, lr
.endif
movs lr, pcff, lsl #24
adc lr, spfa, bcfb
pkhtb pcff, pcff, lr
uxtb lr, lr
bic arvpref, #0xff000000
orr arvpref, lr, lsl #24
pkhtb defr, defr, lr
PREFIX0
.endm
.macro XSUB regis, ofs, cycl
TIME \cycl
mov r11, arvpref, lsr #24
pkhtb spfa, spfa, r11
.if \ofs<24
uxtb lr, \regis, ror #16+\ofs
.endif
mvn lr, lr
pkhtb bcfb, bcfb, lr
add lr, r11
add lr, #0x00000001
pkhtb pcff, pcff, lr
uxtb lr, lr
bic arvpref, #0xff000000
orr arvpref, lr, lsl #24
pkhtb defr, defr, lr
PREFIX0
.endm
.macro XSBC regis, ofs, cycl
TIME \cycl
mov r11, arvpref, lsr #24
pkhtb spfa, spfa, r11
.if \ofs<24
uxtb lr, \regis, ror #16+\ofs
.endif
mvn lr, lr
pkhtb bcfb, bcfb, lr
eor lr, pcff, #0x00000100
movs lr, lr, lsl #24
adc lr, spfa, bcfb
pkhtb pcff, pcff, lr
uxtb lr, lr
bic arvpref, #0xff000000
orr arvpref, lr, lsl #24
pkhtb defr, defr, lr
PREFIX0
.endm
.macro XAND regis, ofs, cycl
TIME \cycl
.if \ofs==24
mov r10, #0xffffff00
orr lr, r10
and arvpref, lr, ror #8
.else
.if \ofs==0
mov lr, #0xff00ffff
orr lr, \regis
and arvpref, lr, ror #24
.else
mov lr, #0x00ffffff
orr lr, \regis
and arvpref, lr
.endif
.endif
mov lr, arvpref, lsr #24
pkhtb bcfb, bcfb, lr, asr #16
pkhtb defr, defr, lr
pkhtb pcff, pcff, lr
mvn lr, lr
pkhtb spfa, spfa, lr
PREFIX0
.endm
.macro XOR regis, ofs, cycl
TIME \cycl
.if \ofs==24
eor arvpref, lr, lsl #24
.else
and lr, \regis, #0x00ff0000 << \ofs
eor arvpref, lr, lsl #8-\ofs
.endif
mov lr, arvpref, lsr #24
pkhtb defr, defr, lr
pkhtb pcff, pcff, lr
add lr, #0x00000100
pkhtb spfa, spfa, lr
pkhtb bcfb, bcfb, lr, asr #16
PREFIX0
.endm
.macro OR regis, ofs, cycl
TIME \cycl
.if \ofs==24
orr arvpref, lr, lsl #24
.else
and lr, \regis, #0x00ff0000 << \ofs
orr arvpref, lr, lsl #8-\ofs
.endif
mov lr, arvpref, lsr #24
pkhtb defr, defr, lr
pkhtb pcff, pcff, lr
add lr, #0x00000100
pkhtb spfa, spfa, lr
pkhtb bcfb, bcfb, lr, asr #16
PREFIX0
.endm
.macro CP regis, ofs, cycl
TIME \cycl
mov r11, arvpref, lsr #24
pkhtb spfa, spfa, r11
.if \ofs==24
mvn r11, lr
pkhtb bcfb, bcfb, r11
sub r10, spfa, lr
and r11, r10, #0x000000ff
pkhtb defr, defr, r11
eor r10, lr
and r10, #0xffffffd7
eor r10, lr
.else
.if \ofs==0
and lr, \regis, #0x00ff0000
mvn r11, lr, asr #16
pkhtb bcfb, bcfb, r11
sub r10, spfa, lr, asr #16
and r11, r10, #0x000000ff
pkhtb defr, defr, r11
eor r10, lr, lsr #16
and r10, #0xffffffd7
eor r10, lr, lsr #16
.else
mov lr, \regis, lsr #24
mvn r11, lr
pkhtb bcfb, bcfb, r11
sub r10, spfa, lr
and r11, r10, #0x000000ff
pkhtb defr, defr, r11
eor r10, lr
and r10, #0xffffffd7
eor r10, lr
.endif
.endif
pkhtb pcff, pcff, r10
PREFIX0
.endm
.macro INCW regis
TIME 6
add \regis, #0x00010000
PREFIX0
.endm
.macro DECW regis
TIME 6
sub \regis, #0x00010000
PREFIX0
.endm
.macro CALLC
beq callnn
TIME 10
add pcff, #0x00020000
PREFIX0
.endm
.macro CALLCI
bne callnn
TIME 10
add pcff, #0x00020000
PREFIX0
.endm
.macro JPC
beq jpcc
TIME 10
add pcff, #0x00020000
PREFIX0
.endm
.macro JPCI
bne jpcc
TIME 10
add pcff, #0x00020000
PREFIX0
.endm
.macro RETC
beq ret11
TIME 5
PREFIX0
.endm
.macro RETCI
bne ret11
TIME 5
PREFIX0
.endm
.macro LDRP src, dst, ofs
TIME 7
mov r11, \src, lsr #16
ldrb lr, [mem, r11]
bic \dst, #0x00ff0000 << \ofs
orr \dst, \dst, lr, lsl #16+\ofs
add r11, #1
pkhtb hlmp, hlmp, r11
PREFIX0
.endm
.macro LDRPI src, dst, ofs
TIME 15
ldr lr, [mem, pcff, lsr #16]
add pcff, #0x00010000
sxtb lr, lr
add lr, \src, lr, lsl #16
ldrb lr, [mem, lr, lsr #16]
bic \dst, #0x00ff0000 << \ofs
orr \dst, lr, lsl #16+\ofs
PREFIX0
.endm
.macro LDPR src, dst, ofs
TIME 7
mov lr, \dst, lsr #16+\ofs
strb lr, [mem, \src, lsr #16]
mov lr, #0x00010000
uadd8 lr, lr, \src
pkhtb hlmp, hlmp, lr, asr #16
PREFIX0
.endm
.macro LDPRI src, dst, ofs
TIME 15
ldr lr, [mem, pcff, lsr #16]
add pcff, #0x00010000
sxtb lr, lr
add lr, \src, lr, lsl #16
mov r11, \dst, lsr #16+\ofs
strb r11, [mem, lr, lsr #16]
PREFIX0
.endm
.macro LDPIM src
TIME 15
ldr lr, [mem, pcff, lsr #16]
add pcff, #0x00020000
mov r11, lr, lsr #8
sxtb lr, lr
add lr, \src, lr, lsl #16
strb r11, [mem, lr, lsr #16]
PREFIX0
.endm
.macro RET cycl
TIME \cycl
ldr lr, [mem, spfa, lsr #16]
add spfa, #0x00020000
pkhtb hlmp, hlmp, lr
pkhbt pcff, pcff, lr, lsl #16
.endm
.macro JRC
beq jrnn
TIME 7
add pcff, #0x00010000
PREFIX0
.endm
.macro JRCI
bne jrnn
TIME 7
add pcff, #0x00010000
PREFIX0
.endm
.macro PUS regis
TIME 11
sub spfa, #0x00020000
mov lr, spfa, lsr #16
mov r11, \regis, lsr #16
strh r11, [mem, lr]
PREFIX0
.endm
.macro POPP regis
TIME 10
ldr lr, [mem, spfa, lsr #16]
pkhbt \regis, \regis, lr, lsl #16
add spfa, #0x00020000
.endm
.macro RLC regis, ofs
TIME 8
uxtb lr, \regis, ror #16+\ofs
add lr, lr, lr, lsl #8
pkhtb pcff, pcff, lr, asr #7
uxtb lr, pcff
bic \regis, #0x00ff0000 << \ofs
orr \regis, lr, lsl #16+\ofs
pkhtb defr, defr, lr
orr lr, #0x00000100
pkhtb spfa, spfa, lr
pkhtb bcfb, bcfb, lr, asr #16
b salida
.endm
.macro RLCX regis, ofs
add lr, r10, r10, lsl #8
pkhtb pcff, pcff, lr, asr #7
uxtb lr, pcff
pkhtb defr, defr, lr
.if \regis!=arvpref || \ofs!=0
bic \regis, #0x00ff0000 << \ofs
orr \regis, lr, lsl #16+\ofs
.endif
orr lr, #0x00000100
pkhtb spfa, spfa, lr
pkhtb bcfb, bcfb, lr, asr #16
strb lr, [mem, r11]
TIME 8
b salida
.endm
.macro RRC regis, ofs
TIME 8
.if \ofs==0
uxtb lr, \regis, ror #16
movs lr, lr, lsr #1
.else
movs lr, \regis, lsr #25
.endif
orrcs lr, #0x00000180
pkhtb pcff, pcff, lr
uxtb lr, lr
bic \regis, #0x00ff0000 << \ofs
orr \regis, lr, lsl #16+\ofs
pkhtb defr, defr, lr
orr lr, #0x00000100
pkhtb spfa, spfa, lr
pkhtb bcfb, bcfb, lr, asr #16
b salida
.endm
.macro RRCX regis, ofs
movs lr, r10, lsr #1
orrcs lr, #0x00000180
pkhtb pcff, pcff, lr
uxtb lr, lr
.if \regis!=arvpref || \ofs!=0
bic \regis, #0x00ff0000 << \ofs
orr \regis, lr, lsl #16+\ofs
.endif
pkhtb defr, defr, lr
orr lr, #0x00000100
pkhtb spfa, spfa, lr
pkhtb bcfb, bcfb, lr, asr #16
strb lr, [mem, r11]
TIME 8
b salida
.endm
.macro RL regis, ofs
TIME 8
movs lr, pcff, lsl #24
uxtb lr, \regis, ror #16+\ofs
adc lr, lr
pkhtb pcff, pcff, lr
uxtb lr, lr
bic \regis, #0x00ff0000 << \ofs
orr \regis, lr, lsl #16+\ofs
pkhtb defr, defr, lr
add lr, #0x00000100
pkhtb spfa, spfa, lr
pkhtb bcfb, bcfb, lr, asr #16
b salida
.endm
.macro RLX regis, ofs
movs lr, pcff, lsl #24
adc lr, r10, r10
pkhtb pcff, pcff, lr
uxtb lr, lr
pkhtb defr, defr, lr
.if \regis!=arvpref || \ofs!=0
bic \regis, #0x00ff0000 << \ofs
orr \regis, lr, lsl #16+\ofs
.endif
orr lr, #0x00000100
pkhtb spfa, spfa, lr
pkhtb bcfb, bcfb, lr, asr #16
strb lr, [mem, r11]
TIME 8
b salida
.endm
.macro RR regis, ofs
TIME 8
uxtb lr, \regis, ror #16+\ofs
add lr, lr, lr, lsl #9
and r10, pcff, #0x00000100
orr lr, r10
pkhtb pcff, pcff, lr, asr #1
uxtb lr, pcff
bic \regis, #0x00ff0000 << \ofs
orr \regis, lr, lsl #16+\ofs
pkhtb defr, defr, lr
add lr, #0x00000100
pkhtb spfa, spfa, lr
pkhtb bcfb, bcfb, lr, asr #16
b salida
.endm
.macro RRX regis, ofs
add lr, r10, r10, lsl #9
tst pcff, #0x00000100
orrne lr, #0x00000100
pkhtb pcff, pcff, lr, asr #1
uxtb lr, pcff
pkhtb defr, defr, lr
.if \regis!=arvpref || \ofs!=0
bic \regis, #0x00ff0000 << \ofs
orr \regis, lr, lsl #16+\ofs
.endif
orr lr, #0x00000100
pkhtb spfa, spfa, lr
pkhtb bcfb, bcfb, lr, asr #16
strb lr, [mem, r11]
TIME 8
b salida
.endm
.macro SLA regis, ofs
TIME 8
uxtb lr, \regis, ror #16+\ofs
mov lr, lr, lsl #1
pkhtb pcff, pcff, lr
uxtb lr, lr
bic \regis, #0x00ff0000 << \ofs
orr \regis, lr, lsl #16+\ofs
pkhtb defr, defr, lr
add lr, #0x00000100
pkhtb spfa, spfa, lr
pkhtb bcfb, bcfb, lr, asr #16
b salida
.endm
.macro SLAX regis, ofs
mov lr, r10, lsl #1
pkhtb pcff, pcff, lr
uxtb lr, lr
pkhtb defr, defr, lr
.if \regis!=arvpref || \ofs!=0
bic \regis, #0x00ff0000 << \ofs
orr \regis, lr, lsl #16+\ofs
.endif
orr lr, #0x00000100
pkhtb spfa, spfa, lr
pkhtb bcfb, bcfb, lr, asr #16
strb lr, [mem, r11]
TIME 8
b salida
.endm
.macro SRA regis, ofs
TIME 8
uxtb lr, \regis, ror #16+\ofs
add lr, lr, lr, lsl #9
tst lr, #0x00000080
orrne lr, #0x00000100
pkhtb pcff, pcff, lr, asr #1
uxtb lr, pcff
bic \regis, #0x00ff0000 << \ofs
orr \regis, lr, lsl #16+\ofs
pkhtb defr, defr, lr
add lr, #0x00000100
pkhtb spfa, spfa, lr
pkhtb bcfb, bcfb, lr, asr #16
b salida
.endm
.macro SRAX regis, ofs
add lr, r10, r10, lsl #9
tst lr, #0x00000080
orrne lr, #0x00000100
pkhtb pcff, pcff, lr, asr #1
uxtb lr, pcff
pkhtb defr, defr, lr
.if \regis!=arvpref || \ofs!=0
bic \regis, #0x00ff0000 << \ofs
orr \regis, lr, lsl #16+\ofs
.endif
orr lr, #0x00000100
pkhtb spfa, spfa, lr
pkhtb bcfb, bcfb, lr, asr #16
strb lr, [mem, r11]
TIME 8
b salida
.endm
.macro SLL regis, ofs
TIME 8
uxtb lr, \regis, ror #16+\ofs
mov lr, lr, lsl #1
orr lr, #0x00000001
pkhtb pcff, pcff, lr
uxtb lr, lr
bic \regis, #0x00ff0000 << \ofs
orr \regis, lr, lsl #16+\ofs
pkhtb defr, defr, lr
add lr, #0x00000100
pkhtb spfa, spfa, lr
pkhtb bcfb, bcfb, lr, asr #16
b salida
.endm
.macro SLLX regis, ofs
mov lr, r10, lsl #1
orr lr, #0x00000001
pkhtb pcff, pcff, lr
uxtb lr, lr
pkhtb defr, defr, lr
.if \regis!=arvpref || \ofs!=0
bic \regis, #0x00ff0000 << \ofs
orr \regis, lr, lsl #16+\ofs
.endif
orr lr, #0x00000100
pkhtb spfa, spfa, lr
pkhtb bcfb, bcfb, lr, asr #16
strb lr, [mem, r11]
TIME 8
b salida
.endm
.macro SRL regis, ofs
TIME 8
uxtb lr, \regis, ror #16+\ofs
add lr, lr, lr, lsl #9
pkhtb pcff, pcff, lr, asr #1
uxtb lr, pcff
bic \regis, #0x00ff0000 << \ofs
orr \regis, lr, lsl #16+\ofs
pkhtb defr, defr, lr
add lr, #0x00000100
pkhtb spfa, spfa, lr
pkhtb bcfb, bcfb, lr, asr #16
b salida
.endm
.macro SRLX regis, ofs
add lr, r10, r10, lsl #9
orr lr, #0x00000001
pkhtb pcff, pcff, lr, asr #1
uxtb lr, pcff
pkhtb defr, defr, lr
.if \regis!=arvpref || \ofs!=0
bic \regis, #0x00ff0000 << \ofs
orr \regis, lr, lsl #16+\ofs
.endif
orr lr, #0x00000100
pkhtb spfa, spfa, lr
pkhtb bcfb, bcfb, lr, asr #16
strb lr, [mem, r11]
TIME 8
b salida
.endm
.macro BIT const, regis, ofs
TIME 8
mov lr, \regis, lsr #16+\ofs
and r11, lr, #\const
pkhtb defr, defr, r11
and lr, #0x00000028
orr lr, r11
bic pcff, #0x000000ff
uxtab pcff, pcff, lr
mvn r11, r11
pkhtb spfa, spfa, r11
pkhtb bcfb, bcfb, lr, asr #16
b salida
.endm
.macro BITHL const
TIME 12
ldrb r10, [mem, hlmp, lsr #16]
and r10, #\const
eor lr, r10, hlmp, lsr #8
and lr, #0xffffffd7
eor lr, hlmp, lsr #8
bic pcff, #0x000000ff
uxtab pcff, pcff, lr
pkhtb defr, defr, r10
mvn lr, r10
pkhtb spfa, spfa, lr
pkhtb bcfb, bcfb, r10, asr #16
b salida
.endm
.macro RES const, regis, ofs
TIME 8
.if \ofs==0
and \regis, #0xff00ffff | \const<<16
.else
and \regis, #0x00ffffff | \const<<24
.endif
b salida
.endm
.macro RESHL const
TIME 15
ldrb lr, [mem, hlmp, lsr #16]
and lr, #\const
strb lr, [mem, hlmp, lsr #16]
b salida
.endm
.macro RESXD const, regis, ofs
and r10, #\const
strb r10, [mem, r11]
.if \regis!=arvpref || \ofs!=0
bic \regis, #0x00ff0000 << \ofs
orr \regis, r10, lsl #16+\ofs
.endif
TIME 8
b salida
.endm
.macro SET const, regis, ofs
TIME 8
orr \regis, #\const<<(16+\ofs)
b salida
.endm
.macro SETHL const
TIME 15
ldrb lr, [mem, hlmp, lsr #16]
orr lr, #\const
strb lr, [mem, hlmp, lsr #16]
b salida
.endm
.macro SETXD const, regis, ofs
orr r10, #\const
strb r10, [mem, r11]
.if \regis!=arvpref || \ofs!=0
bic \regis, #0x00ff0000 << \ofs
orr \regis, r10, lsl #16+\ofs
.endif
TIME 8
b salida
.endm
.macro BITI const
TIME 5
and r10, #\const
eor lr, r10, hlmp, lsr #8
and lr, #0xffffffd7
eor lr, hlmp, lsr #8
bic pcff, #0x000000ff
uxtab pcff, pcff, lr
pkhtb defr, defr, r10
mvn lr, r10
pkhtb spfa, spfa, lr
pkhtb bcfb, bcfb, r10, asr #16
b salida
.endm
.macro EXSPI regis
TIME 19
add r10, mem, spfa, lsr #16
mov lr, \regis, lsr #16
swpb r11, lr, [r10]
mov lr, \regis, lsr #24
add r10, #1
swpb lr, lr, [r10]
orr lr, r11, lr, lsl #8
pkhbt \regis, \regis, lr, lsl #16
pkhtb hlmp, hlmp, lr
.endm