Altera Cyclone V Soc with dual-core ARM Cortex-A9s
- ARM v7 instruction set
- NEON TM SIMD coprocessor and VFPv3 per processor
- Snoop Control Unit (SCU) to ensure coherency within the cluster
- Accelerator coherency port (ACP) that accepts coherency memory access requests
- Interrupt controller
- One general-purpose timer and one watchdog timer per processor
- Debug and trace features
- 32 KB instruction and 32 KB data level 1 (L1) caches per processor
- Memory management unit (MMU) per processor
(no hardware virtualization, unfortunately...)