diff --git a/arch/arm/boot/dts/xilinx/Makefile b/arch/arm/boot/dts/xilinx/Makefile
index 33ffecd51cc3c8..97af323f308f34 100644
--- a/arch/arm/boot/dts/xilinx/Makefile
+++ b/arch/arm/boot/dts/xilinx/Makefile
@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
 	zynq-zc770-xm011.dtb \
 	zynq-zc770-xm012.dtb \
 	zynq-zc770-xm013.dtb \
+	zynq-zed-adv7511-ad7380.dtb \
 	zynq-zed-adv7511-ad7985.dtb \
 	zynq-zed.dtb \
 	zynq-zturn.dtb \
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7380.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7380.dts
new file mode 100644
index 00000000000000..28e9cbc833eb99
--- /dev/null
+++ b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7380.dts
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Analog Devices EVAL-AD7980FMCZ
+ * https://www.analog.com/en/products/ad7980.html
+ * https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD738xFMCZ.html
+ *
+ * hdl_project: <?>
+ * board_revision: <?>
+ *
+ * Copyright (C) 2023 Analog Devices Inc.
+ * Copyright (C) 2023 BayLibre, SAS
+ */
+/dts-v1/;
+
+#include <dt-bindings/dma/axi-dmac.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "zynq-zed.dtsi"
+#include "zynq-zed-adv7511.dtsi"
+
+/ {
+	eval_u2: eval-board-u2-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "EVAL +3.3V supply (U2)";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	eval_u3: eval-board-u3-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "EVAL +3.3V supply (U3)";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	eval_u6: eval-board-u6-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "EVAL +2.3V supply (U6)";
+		regulator-min-microvolt = <2300000>;
+		regulator-max-microvolt = <2300000>;
+		regulator-always-on;
+	};
+};
+
+&fpga_axi {
+	adc_trigger: pwm@44b00000 {
+		compatible = "adi,axi-pwmgen";
+		reg = <0x44b00000 0x1000>;
+		label = "adc_conversion_trigger";
+		#pwm-cells = <2>;
+		clocks = <&spi_clk>;
+	};
+
+	rx_dma: rx-dmac@44a30000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x44a30000 0x1000>;
+		#dma-cells = <1>;
+		interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clkc 17>;
+
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-width = <32>;
+				adi,source-bus-type = <AXI_DMAC_BUS_TYPE_AXI_STREAM>;
+				adi,destination-bus-width = <64>;
+				adi,destination-bus-type = <AXI_DMAC_BUS_TYPE_AXI_MM>;
+			};
+		};
+	};
+
+	spi_clk: clock-controller@44a70000 {
+		compatible = "adi,axi-clkgen-2.00.a";
+		reg = <0x44a70000 0x1000>;
+		#clock-cells = <0>;
+		clocks = <&clkc 15>;
+		clock-names = "s_axi_aclk", "clkin1";
+		clock-output-names = "spi_clk";
+
+		assigned-clocks = <&spi_clk>;
+		assigned-clock-rates = <160000000>;
+	};
+
+	axi_spi_engine_0: spi@44a00000 {
+		compatible = "adi,axi-spi-engine-1.00.a";
+		reg = <0x44a00000 0x1000>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "s_axi_aclk", "spi_clk";
+
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+
+		offloads {
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+	
+			offload_0: offload@0 {
+				reg = <0>;
+				compatible = "adi,axi-spi-engine-offload-pwm-trigger-dma-output";
+				pwms = <&adc_trigger 0 0>;
+				dmas = <&rx_dma 0>;
+				dma-names = "rx";
+			};
+		};
+
+		ad7380: adc@0 {
+			compatible = "adi,ad7380";
+			reg = <0>;
+			spi-cpol;
+			// TODO: awaiting HDL fix for CPHA
+			// spi-cpha;
+			spi-max-frequency = <80000000>; /* 12.5 ns period */
+			adi,sdo-mode = "1-wire";
+			eval_u2-supply = <&eval_u2>;
+			eval_u6-supply = <&eval_u6>;
+			refio-supply = <&eval_u3>;
+			adi,offloads = <&offload_0>;
+		};
+	};
+};