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encounter.log8
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Checking out Encounter license ...
Encounter_Digital_Impl_Sys_XL 9.1 license checkout succeeded.
You can run 2 CPU jobs with the base license that is currently checked out.
If required, use the setMultiCpuUsage command to enable multi-CPU processing.
This Encounter release has been compiled with OA version 22.04-p058.
*******************************************************************
* Copyright (c) Cadence Design Systems, Inc. 1996 - 2009. *
* All rights reserved. *
* *
* *
* *
* This program contains confidential and trade secret information *
* of Cadence Design Systems, Inc. and is protected by copyright *
* law and international treaties. Any reproduction, use, *
* distribution or disclosure of this program or any portion of it,*
* or any attempt to obtain a human-readable version of this *
* program, without the express, prior written consent of *
* Cadence Design Systems, Inc., is strictly prohibited. *
* *
* Cadence Design Systems, Inc. *
* 2655 Seely Avenue *
* San Jose, CA 95134, USA *
* *
* *
*******************************************************************
@(#)CDS: Encounter v09.11-s084_1 (64bit) 04/26/2010 12:41 (Linux 2.6)
@(#)CDS: NanoRoute v09.11-s008 NR100226-1806/USR63-UB (database version 2.30, 93.1.1) {superthreading v1.14}
@(#)CDS: CeltIC v09.11-s011_1 (64bit) 03/04/2010 14:24:46 (Linux 2.6.9-78.0.25.ELsmp)
@(#)CDS: CTE 09.11-s016_1 (64bit) Apr 8 2010 03:29:23 (Linux 2.6.9-78.0.25.ELlargesmp)
@(#)CDS: CPE v09.11-s023
--- Starting "Encounter v09.11-s084_1" on Mon May 4 12:00:06 2015 (mem=59.9M) ---
--- Running on ecegrid-thin5.ecn.purdue.edu (x86_64 w/Linux 2.6.32-504.12.2.el6.x86_64) ---
This version was compiled on Mon Apr 26 12:41:12 PDT 2010.
Set DBUPerIGU to 1000.
Set net toggle Scale Factor to 1.00
Set Shrink Factor to 1.00000
<CMD> loadConfig ./encounter.conf
Reading config file - ./encounter.conf
**WARN: (ENCEXT-1085): Option 'rda_Input(ui_res_scale)' used in configuration file './encounter.conf' is obsolete. The name will be converted into new format automatically if design is saved and then restored. Alternatively, update the configuration file to use names 'rda_Input(ui_preRoute_res)' and/or 'rda_Input(ui_postRoute_res)' for resistance scale factors to be used at preRoute/postRoute stages of the design . The obsolete name works in this release. But to avoid this warning and to ensure compatibility with future releases, update this option name.
Loading Lef file /package/eda/cells/OSU/v2.7/cadence/lib/ami05/lib/osu05_stdcells.lef...
**WARN: (ENCLF-108): There is no overlap layer defined in any lef file
so you are unable to create rectilinear partition in a hierarchical flow.
Set DBUPerIGU to M2 pitch 2400.
Initializing default via types and wire widths ...
Power Planner/ViaGen version 8.1.46 promoted on 02/17/2009.
viaInitial starts at Mon May 4 12:00:22 2015
**WARN: (ENCPP-544): You didn't use the STACK keyword with the LEF SAMENET rule. Stacked vias might not be created correctly.
SAMENET cc via 0.150 ;
**WARN: (ENCPP-544): You didn't use the STACK keyword with the LEF SAMENET rule. Stacked vias might not be created correctly.
SAMENET via via2 0.150 ;
**WARN: (ENCPP-557): a single-layer VIARULE GENERATE for turn-vias is obsolete and is being ignored. You should remove this statement from your LEF file.
VIARULE TURN1 GENERATE
**WARN: (ENCPP-557): a single-layer VIARULE GENERATE for turn-vias is obsolete and is being ignored. You should remove this statement from your LEF file.
VIARULE TURN2 GENERATE
**WARN: (ENCPP-557): a single-layer VIARULE GENERATE for turn-vias is obsolete and is being ignored. You should remove this statement from your LEF file.
VIARULE TURN3 GENERATE
viaInitial ends at Mon May 4 12:00:22 2015
Reading netlist ...
Backslashed names will retain backslash and a trailing blank character.
Reading verilog netlist 'mapped/Floating_point_co_processor_top.v'
Inserting temporary buffers to remove assignment statements.
Module on_chip_sram_wrapper not defined. Created automatically.
**WARN: (ENCVL-346): Module on_chip_sram_wrapper is not defined in LEF files. It will be treated as an empty module.
Undeclared bus init_file_number in module on_chip_sram_wrapper ... created as [31:0].
Undeclared bus dump_file_number in module on_chip_sram_wrapper ... created as [31:0].
Undeclared bus start_address in module on_chip_sram_wrapper ... created as [31:0].
Undeclared bus last_address in module on_chip_sram_wrapper ... created as [31:0].
Undeclared bus address in module on_chip_sram_wrapper ... created as [7:0].
Undeclared bus read_data in module on_chip_sram_wrapper ... created as [31:0].
Undeclared bus write_data in module on_chip_sram_wrapper ... created as [31:0].
*** Memory Usage v0.159.2.6.2.1 (Current mem = 419.320M, initial mem = 59.918M) ***
*** End netlist parsing (cpu=0:00:00.4, real=0:00:00.0, mem=419.3M) ***
Set top cell to Floating_point_co_processor_top.
Reading common timing library '/package/eda/cells/OSU/v2.7/cadence/lib/ami05/lib/osu05_stdcells.tlf' ...
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'A' of cell 'AND2X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'B' of cell 'AND2X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND2X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'A' of cell 'AND2X2' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'B' of cell 'AND2X2' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND2X2' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'A' of cell 'AOI21X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'B' of cell 'AOI21X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'C' of cell 'AOI21X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AOI21X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'A' of cell 'AOI22X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'B' of cell 'AOI22X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'C' of cell 'AOI22X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'D' of cell 'AOI22X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AOI22X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'A' of cell 'BUFX2' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'BUFX2' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'A' of cell 'BUFX4' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'BUFX4' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'A' of cell 'CLKBUF1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (ENCTS-124): Timing library description of pin 'YPAD' is missing from cell 'PADVDD' in timing library 'osu05_stdcells'.
**WARN: (ENCTS-124): Timing library description of pin 'YPAD' is missing from cell 'PADGND' in timing library 'osu05_stdcells'.
read 39 cells in library 'osu05_stdcells'
*** End library_loading (cpu=0.00min, mem=0.3M, fe_cpu=0.06min, fe_mem=419.7M) ***
**WARN: (ENCDB-2504): Cell on_chip_sram_wrapper is instantiated in the Verilog netlist, but is not defined.
Mark pin read_data[31] of cell on_chip_sram_wrapper output for net load_data[31] in module Floating_point_co_processor_design
Mark pin read_data[30] of cell on_chip_sram_wrapper output for net load_data[30] in module Floating_point_co_processor_design
Mark pin read_data[29] of cell on_chip_sram_wrapper output for net load_data[29] in module Floating_point_co_processor_design
Mark pin read_data[28] of cell on_chip_sram_wrapper output for net load_data[28] in module Floating_point_co_processor_design
Mark pin read_data[27] of cell on_chip_sram_wrapper output for net load_data[27] in module Floating_point_co_processor_design
Mark pin read_data[26] of cell on_chip_sram_wrapper output for net load_data[26] in module Floating_point_co_processor_design
Mark pin read_data[25] of cell on_chip_sram_wrapper output for net load_data[25] in module Floating_point_co_processor_design
Mark pin read_data[24] of cell on_chip_sram_wrapper output for net load_data[24] in module Floating_point_co_processor_design
Mark pin read_data[23] of cell on_chip_sram_wrapper output for net load_data[23] in module Floating_point_co_processor_design
Mark pin read_data[22] of cell on_chip_sram_wrapper output for net load_data[22] in module Floating_point_co_processor_design
Mark pin read_data[21] of cell on_chip_sram_wrapper output for net load_data[21] in module Floating_point_co_processor_design
Mark pin read_data[20] of cell on_chip_sram_wrapper output for net load_data[20] in module Floating_point_co_processor_design
Mark pin read_data[19] of cell on_chip_sram_wrapper output for net load_data[19] in module Floating_point_co_processor_design
Mark pin read_data[18] of cell on_chip_sram_wrapper output for net load_data[18] in module Floating_point_co_processor_design
Mark pin read_data[17] of cell on_chip_sram_wrapper output for net load_data[17] in module Floating_point_co_processor_design
Mark pin read_data[16] of cell on_chip_sram_wrapper output for net load_data[16] in module Floating_point_co_processor_design
Mark pin read_data[15] of cell on_chip_sram_wrapper output for net load_data[15] in module Floating_point_co_processor_design
Mark pin read_data[14] of cell on_chip_sram_wrapper output for net load_data[14] in module Floating_point_co_processor_design
Mark pin read_data[13] of cell on_chip_sram_wrapper output for net load_data[13] in module Floating_point_co_processor_design
Mark pin read_data[12] of cell on_chip_sram_wrapper output for net load_data[12] in module Floating_point_co_processor_design
Mark pin read_data[11] of cell on_chip_sram_wrapper output for net load_data[11] in module Floating_point_co_processor_design
Mark pin read_data[10] of cell on_chip_sram_wrapper output for net load_data[10] in module Floating_point_co_processor_design
Mark pin read_data[9] of cell on_chip_sram_wrapper output for net load_data[9] in module Floating_point_co_processor_design
Mark pin read_data[8] of cell on_chip_sram_wrapper output for net load_data[8] in module Floating_point_co_processor_design
Mark pin read_data[7] of cell on_chip_sram_wrapper output for net load_data[7] in module Floating_point_co_processor_design
Mark pin read_data[6] of cell on_chip_sram_wrapper output for net load_data[6] in module Floating_point_co_processor_design
Mark pin read_data[5] of cell on_chip_sram_wrapper output for net load_data[5] in module Floating_point_co_processor_design
Mark pin read_data[4] of cell on_chip_sram_wrapper output for net load_data[4] in module Floating_point_co_processor_design
Mark pin read_data[3] of cell on_chip_sram_wrapper output for net load_data[3] in module Floating_point_co_processor_design
Mark pin read_data[2] of cell on_chip_sram_wrapper output for net load_data[2] in module Floating_point_co_processor_design
Mark pin read_data[1] of cell on_chip_sram_wrapper output for net load_data[1] in module Floating_point_co_processor_design
Mark pin read_data[0] of cell on_chip_sram_wrapper output for net load_data[0] in module Floating_point_co_processor_design
Found empty module (on_chip_sram_wrapper).
Starting recursive module instantiation check.
No recursion found.
Building hierarchical netlist for Cell Floating_point_co_processor_top ...
*** Netlist is unique.
** info: there are 449 modules.
** info: there are 48992 stdCell insts.
** info: there are 107 Pad insts.
*** Memory Usage v0.159.2.6.2.1 (Current mem = 450.453M, initial mem = 59.918M) ***
*info - Done with setDoAssign with 1214 assigns removed and 0 assigns could not be removed.
CTE reading timing constraint file 'encounter.pt' ...
**WARN: (TCLCMD-513): No matching object found for 'transmit' (File encounter.pt, Line 20).
**ERROR: (TCLCMD-917): Cannot find 'ports' that match 'transmit' (File encounter.pt, Line 20).
**WARN: (TCLCMD-513): No matching object found for '' (File encounter.pt, Line 20).
**ERROR: (TCLNL-312): set_input_delay: Invalid list of pins: '' (File encounter.pt, Line 20).
**WARN: (TCLCMD-513): No matching object found for 'write_enable' (File encounter.pt, Line 22).
**ERROR: (TCLCMD-917): Cannot find 'ports' that match 'write_enable' (File encounter.pt, Line 22).
**WARN: (TCLCMD-513): No matching object found for '' (File encounter.pt, Line 22).
**ERROR: (TCLNL-312): set_input_delay: Invalid list of pins: '' (File encounter.pt, Line 22).
**WARN: (TCLCMD-513): No matching object found for 'write_data[7]' (File encounter.pt, Line 24).
**ERROR: (TCLCMD-917): Cannot find 'ports' that match 'write_data[7]' (File encounter.pt, Line 24).
**WARN: (TCLCMD-513): No matching object found for '' (File encounter.pt, Line 24).
**ERROR: (TCLNL-312): set_input_delay: Invalid list of pins: '' (File encounter.pt, Line 24).
**WARN: (TCLCMD-513): No matching object found for 'write_data[6]' (File encounter.pt, Line 26).
**ERROR: (TCLCMD-917): Cannot find 'ports' that match 'write_data[6]' (File encounter.pt, Line 26).
**WARN: (TCLCMD-513): No matching object found for '' (File encounter.pt, Line 26).
**ERROR: (TCLNL-312): set_input_delay: Invalid list of pins: '' (File encounter.pt, Line 26).
**WARN: (TCLCMD-513): No matching object found for 'write_data[5]' (File encounter.pt, Line 28).
**ERROR: (TCLCMD-917): Cannot find 'ports' that match 'write_data[5]' (File encounter.pt, Line 28).
**WARN: (TCLCMD-513): No matching object found for '' (File encounter.pt, Line 28).
**ERROR: (TCLNL-312): set_input_delay: Invalid list of pins: '' (File encounter.pt, Line 28).
**WARN: (TCLCMD-513): No matching object found for 'write_data[4]' (File encounter.pt, Line 30).
**ERROR: (TCLCMD-917): Cannot find 'ports' that match 'write_data[4]' (File encounter.pt, Line 30).
**WARN: (TCLCMD-513): No matching object found for '' (File encounter.pt, Line 30).
**ERROR: (TCLNL-312): set_input_delay: Invalid list of pins: '' (File encounter.pt, Line 30).
**WARN: (TCLCMD-513): No matching object found for 'write_data[3]' (File encounter.pt, Line 32).
**ERROR: (TCLCMD-917): Cannot find 'ports' that match 'write_data[3]' (File encounter.pt, Line 32).
**WARN: (TCLCMD-513): No matching object found for '' (File encounter.pt, Line 32).
**ERROR: (TCLNL-312): set_input_delay: Invalid list of pins: '' (File encounter.pt, Line 32).
**WARN: (TCLCMD-513): No matching object found for 'write_data[2]' (File encounter.pt, Line 34).
**ERROR: (TCLCMD-917): Cannot find 'ports' that match 'write_data[2]' (File encounter.pt, Line 34).
**WARN: (TCLCMD-513): No matching object found for '' (File encounter.pt, Line 34).
**ERROR: (TCLNL-312): set_input_delay: Invalid list of pins: '' (File encounter.pt, Line 34).
**WARN: (TCLCMD-513): No matching object found for 'write_data[1]' (File encounter.pt, Line 36).
**ERROR: (TCLCMD-917): Cannot find 'ports' that match 'write_data[1]' (File encounter.pt, Line 36).
**WARN: (TCLCMD-513): No matching object found for '' (File encounter.pt, Line 36).
**ERROR: (TCLNL-312): set_input_delay: Invalid list of pins: '' (File encounter.pt, Line 36).
**WARN: (TCLCMD-513): No matching object found for 'write_data[0]' (File encounter.pt, Line 38).
**ERROR: (TCLCMD-917): Cannot find 'ports' that match 'write_data[0]' (File encounter.pt, Line 38).
**WARN: (TCLCMD-513): No matching object found for '' (File encounter.pt, Line 38).
**ERROR: (TCLNL-312): set_input_delay: Invalid list of pins: '' (File encounter.pt, Line 38).
**ERROR: (TCLCMD-917): Cannot find 'ports' that match 'fifo_full' (File encounter.pt, Line 44).
**ERROR: (TCLNL-312): set_output_delay: Invalid list of pins: '' (File encounter.pt, Line 44).
**ERROR: (TCLCMD-917): Cannot find 'ports' that match 'fifo_empty' (File encounter.pt, Line 46).
**ERROR: (TCLNL-312): set_output_delay: Invalid list of pins: '' (File encounter.pt, Line 46).
**ERROR: (TCLCMD-917): Cannot find 'ports' that match 'd_plus' (File encounter.pt, Line 48).
**ERROR: (TCLNL-312): set_output_delay: Invalid list of pins: '' (File encounter.pt, Line 48).
**ERROR: (TCLCMD-917): Cannot find 'ports' that match 'd_minus' (File encounter.pt, Line 50).
**ERROR: (TCLNL-312): set_output_delay: Invalid list of pins: '' (File encounter.pt, Line 50).
**ERROR: (TCLCMD-917): Cannot find 'ports' that match 'transmit' (File encounter.pt, Line 60).
**ERROR: (TCLNL-312): set_driving_cell: Invalid list of pins: '' (File encounter.pt, Line 60).
**ERROR: (TCLCMD-917): Cannot find 'ports' that match 'write_enable' (File encounter.pt, Line 62).
**ERROR: (TCLNL-312): set_driving_cell: Invalid list of pins: '' (File encounter.pt, Line 62).
**ERROR: (TCLCMD-917): Cannot find 'ports' that match 'write_data[7]' (File encounter.pt, Line 64).
**ERROR: (TCLNL-312): set_driving_cell: Invalid list of pins: '' (File encounter.pt, Line 64).
**ERROR: (TCLCMD-917): Cannot find 'ports' that match 'write_data[6]' (File encounter.pt, Line 66).
**ERROR: (TCLNL-312): set_driving_cell: Invalid list of pins: '' (File encounter.pt, Line 66).
**ERROR: (TCLCMD-917): Cannot find 'ports' that match 'write_data[5]' (File encounter.pt, Line 68).
**ERROR: (TCLNL-312): set_driving_cell: Invalid list of pins: '' (File encounter.pt, Line 68).
**ERROR: (TCLCMD-917): Cannot find 'ports' that match 'write_data[4]' (File encounter.pt, Line 70).
**ERROR: (TCLNL-312): set_driving_cell: Invalid list of pins: '' (File encounter.pt, Line 70).
**ERROR: (TCLNL-312): set_driving_cell: Invalid list of pins: '' (File encounter.pt, Line 72).
**ERROR: (TCLNL-312): set_driving_cell: Invalid list of pins: '' (File encounter.pt, Line 74).
**ERROR: (TCLNL-312): set_driving_cell: Invalid list of pins: '' (File encounter.pt, Line 76).
**ERROR: (TCLNL-312): set_driving_cell: Invalid list of pins: '' (File encounter.pt, Line 78).
INFO (CTE): read_dc_script finished with 20 WARNING and 44 ERROR
*** Read timing constraints (cpu=0:00:00.0 mem=462.4M) ***
Total number of combinational cells: 26
Total number of sequential cells: 4
Total number of tristate cells: 2
Total number of level shifter cells: 0
Total number of power gating cells: 0
Total number of isolation cells: 0
Total number of power switch cells: 0
Total number of pulse generator cells: 0
Total number of always on buffers: 0
Total number of retention cells: 0
List of usable buffers: BUFX2 BUFX4 CLKBUF1
Total number of usable buffers: 3
List of unusable buffers:
Total number of unusable buffers: 0
List of usable inverters: INVX2 INVX1 INVX4 INVX8
Total number of usable inverters: 4
List of unusable inverters:
Total number of unusable inverters: 0
List of identified usable delay cells: CLKBUF2 CLKBUF3
Total number of identified usable delay cells: 2
List of identified unusable delay cells:
Total number of identified unusable delay cells: 0
*info: set bottom ioPad orient R180
Reading IO assignment file "encounter.io" ...
**Warn: ignored IO file "encounter.io" line 118: Pad: U108 S
Reason: unable to determine object from name.
Horizontal Layer M1 offset = 1500 (derived)
Vertical Layer M2 offset = 1200 (derived)
Set Using Default Delay Limit as 1000.
Set Default Net Delay as 1000 ps.
Set Default Net Load as 0.5 pF.
Set Input Pin Transition Delay as 120 ps.
PreRoute Cap Scale Factor : 1.00
PreRoute Res Scale Factor : 1.00
PostRoute Cap Scale Factor : 1.00
PostRoute Res Scale Factor : 1.00
PostRoute XCap Scale Factor : 1.00
PreRoute Clock Cap Scale Factor : 1.00 [Derived from postRoute_cap (effortLevel low)]
PreRoute Clock Res Scale Factor : 1.00 [Derived from postRoute_res (effortLevel low)]
PostRoute Clock Cap Scale Factor : 1.00 [Derived from postRoute_cap (effortLevel low)]
PostRoute Clock Res Scale Factor : 1.00 [Derived from postRoute_res (effortLevel low)]
**WARN: (ENCOPT-3465): The buffer cells were automatically identified. The command setBufFootPrint is ignored. If you want to force the tool to honor this setting, you have to load a footprint file through the loadFootPrint command.
**WARN: (ENCOPT-3466): The inverter cells were automatically identified. The command setInvFootPrint is ignored. If you want to force the tool to honor this setting, you have to load a footprint file through the loadFootPrint command.
**WARN: (ENCOPT-3467): The delay cells were automatically identified. The command setDelayFootPrint is ignored. If you want to force the tool to honor this setting, you have to load a footprint file through the loadFootPrint command.
<CMD> floorPlan -r 1.0 0.4 5000 5000 5000 5000
Snap core to left to manufacture grid: 4999.9500.
Snap core to bottom to manufacture grid: 4999.9500.
Snap core to right to manufacture grid: 4999.9500.
Snap core to top to manufacture grid: 4999.9500.
Adjusting Core to Left to: 5001.6000. Core to Bottom to: 5001.0000.
Horizontal Layer M1 offset = 1500 (derived)
Vertical Layer M2 offset = 1200 (derived)
<CMD> addRing -spacing_bottom 9.9 -width_left 9.9 -width_bottom 9.9 -width_top 9.9 -spacing_top 9.9 -layer_bottom metal1 -width_right 9.9 -around core -center 1 -layer_top metal1 -spacing_right 9.9 -spacing_left 9.9 -layer_right metal2 -layer_left metal2 -offset_top 9.9 -offset_bottom 9.9 -offset_left 9.9 -offset_right 9.9 -nets { gnd vdd }
The power planner created 8 wires.
<CMD> setPlaceMode -congEffort medium
<CMD> placeDesign -inPlaceOpt
*** Starting placeDesign concurrent flow ***
*** Start deleteBufferTree ***
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.1, MEM = 491.8M)
Number of Loop : 0
Start delay calculation (mem=491.785M)...
Delay calculation completed. (cpu=0:00:01.4 real=0:00:01.0 mem=499.965M 0)
*** CDM Built up (cpu=0:00:02.8 real=0:00:02.0 mem= 500.0M) ***
Info: Detect buffers to remove automatically.
Analyzing netlist ...
Updating netlist
*summary: 2634 instances (buffers/inverters) removed
*** Finish deleteBufferTree (0:00:04.0) ***
Extracting standard cell pins and blockage ......
Pin and blockage extraction finished
Extracting macro/IO cell pins and blockage ......
Pin and blockage extraction finished
*** Starting "NanoPlace(TM) placement v0.892.2.8.2.1 (mem=503.6M)" ...
*** Build Buffered Sizing Timing Model
(cpu=0:00:00.0 mem=503.6M) ***
*** Build Virtual Sizing Timing Model
(cpu=0:00:00.0 mem=503.6M) ***
Options: timingDriven ignoreScan ignoreSpare pinGuide gpeffort=medium
**WARN: (ENCDB-2082): Scan chains were not defined, -ignoreScan option will be ignored.
Please first define the scan chains before using this option.
#std cell=46358 #block=0 (0 floating + 0 preplaced) #ioInst=111 #net=48177 #term=160377 #term/net=3.33, #fixedIo=111, #floatIo=0, #fixedPin=105, #floatPin=0
stdCell: 46358 single + 0 double + 0 multi
Total standard cell length = 729.8880 (mm), area = 21.8966 (mm^2)
Average module density = 0.391.
Density for the design = 0.391.
= stdcell_area 304120 (21896640 um^2) / alloc_area 777876 (56007072 um^2).
Pin Density = 0.527.
= total # of pins 160377 / total Instance area 304120.
Iteration 1: Total net bbox = 2.637e+06 (1.41e+06 1.22e+06)
Est. stn bbox = 2.637e+06 (1.41e+06 1.22e+06)
cpu = 0:00:00.6 real = 0:00:00.0 mem = 534.7M
Iteration 2: Total net bbox = 2.637e+06 (1.41e+06 1.22e+06)
Est. stn bbox = 2.637e+06 (1.41e+06 1.22e+06)
cpu = 0:00:00.0 real = 0:00:00.0 mem = 534.7M
Iteration 3: Total net bbox = 2.644e+06 (1.42e+06 1.23e+06)
Est. stn bbox = 2.644e+06 (1.42e+06 1.23e+06)
cpu = 0:00:00.1 real = 0:00:00.0 mem = 534.7M
Iteration 4: Total net bbox = 1.508e+07 (6.46e+06 8.62e+06)
Est. stn bbox = 1.508e+07 (6.46e+06 8.62e+06)
cpu = 0:00:06.5 real = 0:00:07.0 mem = 534.7M
Iteration 5: Total net bbox = 1.203e+07 (5.11e+06 6.92e+06)
Est. stn bbox = 1.203e+07 (5.11e+06 6.92e+06)
cpu = 0:00:05.2 real = 0:00:05.0 mem = 534.7M
Iteration 6: Total net bbox = 1.267e+07 (5.94e+06 6.73e+06)
Est. stn bbox = 1.267e+07 (5.94e+06 6.73e+06)
cpu = 0:00:08.2 real = 0:00:09.0 mem = 537.7M
Iteration 7: Total net bbox = 1.271e+07 (5.97e+06 6.74e+06)
Est. stn bbox = 1.521e+07 (6.90e+06 8.31e+06)
cpu = 0:00:21.1 real = 0:00:21.0 mem = 524.4M
Iteration 8: Total net bbox = 1.274e+07 (5.98e+06 6.75e+06)
Est. stn bbox = 1.523e+07 (6.91e+06 8.33e+06)
cpu = 0:00:10.4 real = 0:00:10.0 mem = 524.4M
Iteration 9: Total net bbox = 1.192e+07 (5.64e+06 6.27e+06)
Est. stn bbox = 1.452e+07 (6.70e+06 7.83e+06)
cpu = 0:00:28.4 real = 0:00:28.0 mem = 527.4M
Iteration 10: Total net bbox = 1.198e+07 (5.67e+06 6.31e+06)
Est. stn bbox = 1.459e+07 (6.73e+06 7.86e+06)
cpu = 0:00:10.5 real = 0:00:11.0 mem = 527.4M
Iteration 11: Total net bbox = 1.201e+07 (5.73e+06 6.29e+06)
Est. stn bbox = 1.477e+07 (6.91e+06 7.86e+06)
cpu = 0:00:26.7 real = 0:00:27.0 mem = 528.4M
Iteration 12: Total net bbox = 1.215e+07 (5.79e+06 6.36e+06)
Est. stn bbox = 1.492e+07 (6.97e+06 7.95e+06)
cpu = 0:00:10.7 real = 0:00:10.0 mem = 528.4M
Iteration 13: Total net bbox = 1.268e+07 (6.08e+06 6.60e+06)
Est. stn bbox = 1.553e+07 (7.31e+06 8.22e+06)
cpu = 0:01:36 real = 0:01:37 mem = 523.4M
Iteration 14: Total net bbox = 1.268e+07 (6.08e+06 6.60e+06)
Est. stn bbox = 1.553e+07 (7.31e+06 8.22e+06)
cpu = 0:00:00.1 real = 0:00:00.0 mem = 525.4M
Iteration 15: Total net bbox = 1.294e+07 (6.31e+06 6.63e+06)
Est. stn bbox = 1.581e+07 (7.55e+06 8.26e+06)
cpu = 0:00:00.6 real = 0:00:00.0 mem = 525.4M
*** cost = 1.294e+07 (6.31e+06 6.63e+06) (cpu for global=0:03:25) real=0:03:24***
Core Placement runtime cpu: 0:02:50 real: 0:02:51
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode. (cpu=0:00:02.2, real=0:00:02.0)
move report: preRPlace moves 2302 insts, mean move: 5.49 um, max move: 48.00 um
max move on inst (I0/FP_PROCESSOR/SIN/MULX3FAC/op1_reg[28]): (5306.40, 8871.00) --> (5354.40, 8871.00)
Placement tweakage begins.
wire length = 1.294e+07 = 6.308e+06 H + 6.635e+06 V
wire length = 1.261e+07 = 6.000e+06 H + 6.613e+06 V
Placement tweakage ends.
move report: wireLenOpt moves 9706 insts, mean move: 28.01 um, max move: 96.00 um
max move on inst (I0/FP_PROCESSOR/SIN/MULX3/NORM/U59): (6535.20, 7011.00) --> (6631.20, 7011.00)
move report: rPlace moves 11562 insts, mean move: 24.31 um, max move: 96.00 um
max move on inst (I0/FP_PROCESSOR/SIN/MULX3/NORM/U59): (6535.20, 7011.00) --> (6631.20, 7011.00)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 96.00 um
inst (I0/FP_PROCESSOR/SIN/MULX3/NORM/U59) with max move: (6535.2, 7011) -> (6631.2, 7011)
mean (X+Y) = 24.31 um
Total instances flipped for WireLenOpt: 695
Total instances flipped, including legalization: 22460
Total instances moved : 11562
*** cpu=0:00:03.3 mem=539.0M mem(used)=22.0M***
Total net length = 1.262e+07 (6.000e+06 6.618e+06) (ext = 0.000e+00)
*** End of Placement (cpu=0:03:31, real=0:03:31, mem=537.1M) ***
default core: bins with density > 0.75 = 1.12 % ( 7 / 625 )
*** Free Virtual Timing Model ...(mem=521.3M)
Starting IO pin assignment...
**WARN: (ENCSP-9025): No scan chain specified/traced.
setAnalysisMode -domain allClockDomain -checkType setup -skew true -usefulSkew false -log true -warn true -caseAnalysis true -sequentialConstProp false -moduleIOCstr true -clockPropagation forcedIdeal -clkSrcPath false -timingSelfLoopsNoSkew false -asyncChecks async -useOutputPinCap true -latch true -latchDelayCalIteration 2 -timeBorrowing true -latchFullDelayCal false -clockGatingCheck true -enableMultipleDriveNet true -analysisType single -cppr false -clkNetsMarking beforeConstProp -honorVirtualPartition false -honorClockDomains true
**WARN: (ENCOPT-6055): The following cells have a dont_touch property but without being dont_use.
Such configuration can impact the timing closure because they can be inserted in the netlist but never transformed again.
It is recommended that you apply a dont_use attribute on them.
Cell PADVDD is dont_touch but not dont_use
Cell PADNC is dont_touch but not dont_use
Cell PADGND is dont_touch but not dont_use
Cell PADFC is dont_touch but not dont_use
...
Reporting only the 20 first cells found...
**optDesign ... cpu = 0:00:00, real = 0:00:00, mem = 519.2M **
Added -handlePreroute to trialRouteMode
*** optDesign -preCTS ***
DRC Margin: user margin 0.0; extra margin 0.2
Setup Target Slack: user slack 0.0; extra slack 0.1
Hold Target Slack: user slack 0.0
*info: Setting setup target slack to 0.100
*info: Hold target slack is 0.000
*** CTE mode ***
*** Starting trialRoute (mem=519.2M) ***
There are 0 pin guide points passed to trialRoute.
**WARN: (ENCTR-2325): 52 nets connect a pad term to a fterm without geometry and will not be routed.
Options: -handlePreroute -noPinGuide
Nr of prerouted/Fixed nets = 105
routingBox: (1200 1500) (18099600 18070500)
coreBox: (5301600 5301000) (12799800 12771000)
Number of multi-gpin terms=0, multi-gpins=0, moved blk term=14/1468
Phase 1a route (0:00:00.5 559.8M):
Est net length = 1.502e+07um = 7.339e+06H + 7.683e+06V
Usage: (14.3%H 11.2%V) = (8.133e+06um 1.181e+07um) = (655862 390190)
Obstruct: 5561 = 1452 (0.4%H) + 4109 (1.1%V)
Overflow: 26353 = 3781 (1.04% H) + 22572 (6.23% V)
Number obstruct path=180 reroute=0
Phase 1b route (0:00:00.3 562.3M):
Usage: (14.3%H 11.2%V) = (8.129e+06um 1.182e+07um) = (655534 390658)
Overflow: 24333 = 2527 (0.69% H) + 21806 (6.02% V)
Phase 1c route (0:00:00.2 562.3M):
Usage: (14.2%H 11.3%V) = (8.120e+06um 1.185e+07um) = (654825 391554)
Overflow: 22107 = 1817 (0.50% H) + 20290 (5.60% V)
Phase 1d route (0:00:00.2 563.3M):
Usage: (14.3%H 11.4%V) = (8.167e+06um 1.198e+07um) = (658727 395977)
Overflow: 15599 = 760 (0.21% H) + 14839 (4.10% V)
Phase 1e route (0:00:00.6 565.1M):
Usage: (14.5%H 11.6%V) = (8.247e+06um 1.224e+07um) = (665036 404435)
Overflow: 10414 = 65 (0.02% H) + 10349 (2.86% V)
Phase 1f route (0:00:00.6 565.1M):
Usage: (14.7%H 11.7%V) = (8.388e+06um 1.233e+07um) = (676592 407608)
Overflow: 6131 = 10 (0.00% H) + 6121 (1.69% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-3: 0 0.00% 5 0.00%
-2: 0 0.00% 414 0.11%
-1: 10 0.00% 5527 1.53%
--------------------------------------
0: 3434 0.94% 36477 10.07%
1: 8100 2.22% 29516 8.15%
2: 11424 3.13% 24693 6.82%
3: 14549 3.99% 20183 5.57%
4: 17142 4.70% 17891 4.94%
5: 18280 5.01% 158387 43.73%
6: 19206 5.26% 1003 0.28%
7: 19006 5.21% 20 0.01%
8: 17086 4.68% 29 0.01%
9: 14428 3.95% 12 0.00%
10: 48882 13.40% 15 0.00%
11: 38 0.01% 34 0.01%
12: 25 0.01% 36 0.01%
13: 78 0.02% 9 0.00%
14: 647 0.18% 25 0.01%
15: 87469 23.97% 30 0.01%
16: 85080 23.32% 37 0.01%
17: 0 0.00% 16 0.00%
18: 0 0.00% 10 0.00%
19: 0 0.00% 18 0.00%
20: 0 0.00% 67840 18.73%
Global route (cpu=2.3s real=2.0s 562.4M)
*** After '-updateRemainTrks' operation:
Usage: (14.7%H 11.7%V) = (8.388e+06um 1.233e+07um) = (676592 407608)
Overflow: 6131 = 10 (0.00% H) + 6121 (1.69% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-3: 0 0.00% 5 0.00%
-2: 0 0.00% 414 0.11%
-1: 10 0.00% 5527 1.53%
--------------------------------------
0: 3434 0.94% 36477 10.07%
1: 8100 2.22% 29516 8.15%
2: 11424 3.13% 24693 6.82%
3: 14549 3.99% 20183 5.57%
4: 17142 4.70% 17891 4.94%
5: 18280 5.01% 158387 43.73%
6: 19206 5.26% 1003 0.28%
7: 19006 5.21% 20 0.01%
8: 17086 4.68% 29 0.01%
9: 14428 3.95% 12 0.00%
10: 48882 13.40% 15 0.00%
11: 38 0.01% 34 0.01%
12: 25 0.01% 36 0.01%
13: 78 0.02% 9 0.00%
14: 647 0.18% 25 0.01%
15: 87469 23.97% 30 0.01%
16: 85080 23.32% 37 0.01%
17: 0 0.00% 16 0.00%
18: 0 0.00% 10 0.00%
19: 0 0.00% 18 0.00%
20: 0 0.00% 67840 18.73%
*** Completed Phase 1 route (0:00:02.7 553.7M) ***
Total length: 1.556e+07um, number of vias: 338271
M1(H) length: 0.000e+00um, number of vias: 160074
M2(V) length: 8.164e+06um, number of vias: 178197
M3(H) length: 7.400e+06um
*** Completed Phase 2 route (0:00:02.2 573.8M) ***
*** Finished all Phases (cpu=0:00:05.1 mem=573.8M) ***
Peak Memory Usage was 561.1M
*** Finished trialRoute (cpu=0:00:05.4 mem=573.8M) ***
Extraction called for design 'Floating_point_co_processor_top' of instances=46469 and nets=49669 using extraction engine 'preRoute' .
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
Default RC Extraction called for design Floating_point_co_processor_top.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
RCMode: Default
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res Scaling Factor : 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Default RC Extraction DONE (CPU Time: 0:00:00.1 Real Time: 0:00:00.0 MEM: 573.820M)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.1, MEM = 586.6M)
Number of Loop : 0
Start delay calculation (mem=586.602M)...
**WARN: (ENCEXT-2882): Unable to find resistance for via 'M3_M2' in capacitance table or LEF files. Check the capacitance table and LEF files. Assigning default value of 4.0 ohms.
**WARN: (ENCEXT-2882): Unable to find resistance for via 'M2_M1' in capacitance table or LEF files. Check the capacitance table and LEF files. Assigning default value of 4.0 ohms.
Delay calculation completed. (cpu=0:00:03.9 real=0:00:04.0 mem=589.680M 30)
*** CDM Built up (cpu=0:00:05.2 real=0:00:05.0 mem= 589.7M) ***
Info: 105 io nets excluded
Info: 2 clock nets excluded from IPO operation.
Netlist preparation processing...
Removed 1819 instances
*info: Marking 0 isolation instances dont touch
*info: Marking 0 level shifter instances dont touch
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
*** Starting delays update (0:03:53 mem=602.6M) ***
*** Finished delays update (0:03:59 mem=595.0M) ***
**optDesign ... cpu = 0:00:20, real = 0:00:20, mem = 596.1M **
*info: Start fixing DRV (Mem = 596.13M) ...
*info: Options = -maxCap -maxTran -noMaxFanout -sensitivity -backward -reduceBuffer -maxIter 1
*info: Start fixing DRV iteration 1 ...
*** Starting dpFixDRCViolation (596.1M)
*info: 105 io nets excluded
*info: 2 clock nets excluded
*info: 2 special nets excluded.
*info: 1770 no-driver nets excluded.
*** Starting multi-driver net buffering ***
*summary: 0 non-ignored multi-driver nets.
*** Finished buffering multi-driver nets (CPU=0:00:00.5, MEM=596.1M) ***
*info: There are 3 candidate Buffer cells
*info: There are 4 candidate Inverter cells
Initializing placement sections/sites ...
Density before buffering = 0.373719
Start fixing design rules ... (0:00:00.4 600.2M)
Phase 1 (2) Starts......
Phase 2 Starts......
Done fixing design rule (0:00:15.8 611.4M)
Summary:
1776 buffers added on 1375 nets (with 840 drivers resized)
Density after buffering = 0.382974
*** Completed dpFixDRCViolation (0:00:16.5 610.0M)
Re-routed 3982 nets
Extraction called for design 'Floating_point_co_processor_top' of instances=46426 and nets=50029 using extraction engine 'preRoute' .
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
Default RC Extraction called for design Floating_point_co_processor_top.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
RCMode: Default
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res Scaling Factor : 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Default RC Extraction DONE (CPU Time: 0:00:00.1 Real Time: 0:00:00.0 MEM: 610.004M)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.1, MEM = 603.6M)
Number of Loop : 0
Start delay calculation (mem=603.562M)...
Delay calculation completed. (cpu=0:00:03.6 real=0:00:03.0 mem=606.543M 0)
*** CDM Built up (cpu=0:00:05.0 real=0:00:05.0 mem= 606.5M) ***
*info: DRV Fixing Iteration 1.
*info: Remaining violations:
*info: Max cap violations: 9
*info: Max tran violations: 0
*info: Prev Max cap violations: 1403
*info: Prev Max tran violations: 0
*info:
*info: Completed fixing DRV (CPU Time = 0:00:23, Mem = 606.54M).
**optDesign ... cpu = 0:00:43, real = 0:00:43, mem = 606.5M **
*** Starting optFanout (606.5M)
*info: 105 io nets excluded
*info: 2 clock nets excluded
*info: 2 special nets excluded.
*info: 1770 no-driver nets excluded.
*** Starting multi-driver net buffering ***
*summary: 0 non-ignored multi-driver nets.
*** Finished buffering multi-driver nets (CPU=0:00:00.5, MEM=606.5M) ***
Start fixing timing ... (0:00:00.4 606.5M)
Start clock batches slack = -11.747ns
**WARN: (ENCDB-2513): Given orientation not legal, FE_OFC2653_npaddr_1_ remains original orientation R0, check for SYMMETRY statement in the LEF file for the cell INVX8.
**WARN: (ENCDB-2513): Given orientation not legal, FE_OFC2654_npaddr_1_ remains original orientation R0, check for SYMMETRY statement in the LEF file for the cell INVX8.
**WARN: (ENCDB-2513): Given orientation not legal, FE_OFC2655_npaddr_0_ remains original orientation R0, check for SYMMETRY statement in the LEF file for the cell INVX8.
**WARN: (ENCDB-2513): Given orientation not legal, FE_OFC2656_npaddr_0_ remains original orientation R0, check for SYMMETRY statement in the LEF file for the cell INVX4.
Phase 1 (2) Starts......
Phase 2 Starts......
End batches slack = -9.600ns
*info: Buffered 0 large fanout net (> 100 terms)
Done fixing timing (0:00:28.9 623.1M)
Summary:
4734 buffers added on 1081 nets (with 2123 drivers resized)
997 nets rebuffered with 1251 inst removed and 4544 inst added
Density after buffering = 0.403158
*** Completed optFanout (0:00:29.5 623.1M)
Re-routed 53 nets
Extraction called for design 'Floating_point_co_processor_top' of instances=49909 and nets=53512 using extraction engine 'preRoute' .
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
Default RC Extraction called for design Floating_point_co_processor_top.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
RCMode: Default
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res Scaling Factor : 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Default RC Extraction DONE (CPU Time: 0:00:00.1 Real Time: 0:00:00.0 MEM: 623.102M)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.1, MEM = 614.5M)
Number of Loop : 0
Start delay calculation (mem=614.516M)...
Delay calculation completed. (cpu=0:00:03.7 real=0:00:03.0 mem=617.438M 0)
*** CDM Built up (cpu=0:00:05.1 real=0:00:05.0 mem= 617.4M) ***
**optDesign ... cpu = 0:01:18, real = 0:01:19, mem = 617.4M **
*** Timing NOT met, worst failing slack is -10.045
*** Check timing (0:00:00.5)
************ Recovering area ***************
Info: 105 io nets excluded
Info: 2 clock nets excluded from IPO operation.
*** Starting Area Reclaim ***
** Density before area reclaim = 39.782% **
*** starting 1-st reclaim pass: 46058 instances
*** starting 2-nd reclaim pass: 45600 instances
*** starting 3-rd reclaim pass: 16743 instances
*** starting 4-th reclaim pass: 2436 instances
*** starting 5-th reclaim pass: 10 instances
** Area Reclaim Summary: Buffer Deletion = 21 Declone = 437 Downsize = 3407 **
** Density Change = 0.068% **
** Density after area reclaim = 39.713% **
*** Finished Area Reclaim (0:00:30.3) ***
*** Starting sequential cell resizing ***
density before resizing = 39.713%
*summary: 0 instances changed cell type
density after resizing = 39.713%
*** Finish sequential cell resizing (cpu=0:00:01.5 mem=622.2M) ***
density before resizing = 39.713%
* summary of transition time violation fixes:
*summary: 124 instances changed cell type
density after resizing = 39.747%
*** Starting trialRoute (mem=589.1M) ***
There are 0 pin guide points passed to trialRoute.
Options: -handlePreroute -keepMarkedOptRoutes -noPinGuide
Nr of prerouted/Fixed nets = 190
routingBox: (1200 1500) (18099600 18070500)
coreBox: (5301600 5301000) (12799800 12771000)
Number of multi-gpin terms=0, multi-gpins=0, moved blk term=14/1497
Phase 1a route (0:00:00.4 603.5M):
Est net length = 1.447e+07um = 7.093e+06H + 7.382e+06V
Usage: (13.8%H 11.0%V) = (7.870e+06um 1.159e+07um) = (633982 382681)
Obstruct: 5553 = 1452 (0.4%H) + 4101 (1.1%V)
Overflow: 24533 = 2841 (0.78% H) + 21692 (5.99% V)
Number obstruct path=181 reroute=0
Phase 1b route (0:00:00.3 605.5M):
Usage: (13.8%H 11.0%V) = (7.867e+06um 1.160e+07um) = (633685 383161)
Overflow: 22728 = 1724 (0.47% H) + 21004 (5.80% V)
Phase 1c route (0:00:00.2 606.5M):
Usage: (13.8%H 11.0%V) = (7.855e+06um 1.162e+07um) = (632727 383966)
Overflow: 20954 = 1097 (0.30% H) + 19856 (5.48% V)
Phase 1d route (0:00:00.3 606.5M):
Usage: (13.8%H 11.1%V) = (7.899e+06um 1.175e+07um) = (636406 388199)
Overflow: 14768 = 383 (0.10% H) + 14385 (3.97% V)
Phase 1e route (0:00:00.5 608.2M):
Usage: (14.0%H 11.3%V) = (7.998e+06um 1.196e+07um) = (644508 395099)
Overflow: 10218 = 54 (0.01% H) + 10164 (2.81% V)
Phase 1f route (0:00:00.5 609.2M):
Usage: (14.3%H 11.4%V) = (8.135e+06um 1.206e+07um) = (655846 398475)
Overflow: 6019 = 12 (0.00% H) + 6007 (1.66% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-3: 0 0.00% 6 0.00%
-2: 0 0.00% 392 0.11%
-1: 12 0.00% 5442 1.50%
--------------------------------------
0: 2932 0.80% 34881 9.63%
1: 7094 1.94% 28557 7.88%
2: 10634 2.91% 24873 6.87%
3: 13997 3.84% 20220 5.58%
4: 17027 4.67% 17846 4.93%
5: 19057 5.22% 160856 44.41%
6: 19525 5.35% 1031 0.28%
7: 19124 5.24% 19 0.01%
8: 16604 4.55% 11 0.00%
9: 13856 3.80% 7 0.00%
10: 51685 14.16% 13 0.00%
11: 38 0.01% 31 0.01%
12: 25 0.01% 30 0.01%
13: 78 0.02% 2 0.00%
14: 714 0.20% 7 0.00%
15: 87536 23.99% 14 0.00%
16: 84946 23.28% 24 0.01%
17: 0 0.00% 11 0.00%
18: 0 0.00% 7 0.00%
19: 0 0.00% 3 0.00%
20: 0 0.00% 67952 18.76%
Global route (cpu=2.3s real=2.0s 607.0M)
*** After '-updateRemainTrks' operation:
Usage: (14.3%H 11.4%V) = (8.135e+06um 1.206e+07um) = (655846 398475)
Overflow: 6019 = 12 (0.00% H) + 6007 (1.66% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-3: 0 0.00% 6 0.00%
-2: 0 0.00% 392 0.11%
-1: 12 0.00% 5442 1.50%
--------------------------------------
0: 2932 0.80% 34881 9.63%
1: 7094 1.94% 28557 7.88%
2: 10634 2.91% 24873 6.87%
3: 13997 3.84% 20220 5.58%
4: 17027 4.67% 17846 4.93%
5: 19057 5.22% 160856 44.41%
6: 19525 5.35% 1031 0.28%
7: 19124 5.24% 19 0.01%
8: 16604 4.55% 11 0.00%
9: 13856 3.80% 7 0.00%
10: 51685 14.16% 13 0.00%
11: 38 0.01% 31 0.01%
12: 25 0.01% 30 0.01%
13: 78 0.02% 2 0.00%
14: 714 0.20% 7 0.00%
15: 87536 23.99% 14 0.00%
16: 84946 23.28% 24 0.01%
17: 0 0.00% 11 0.00%
18: 0 0.00% 7 0.00%
19: 0 0.00% 3 0.00%
20: 0 0.00% 67952 18.76%
*** Completed Phase 1 route (0:00:02.8 598.1M) ***
Total length: 1.500e+07um, number of vias: 333520
M1(H) length: 1.512e+02um, number of vias: 161435
M2(V) length: 7.828e+06um, number of vias: 172085
M3(H) length: 7.173e+06um
*** Completed Phase 2 route (0:00:02.7 619.2M) ***
*** Finished all Phases (cpu=0:00:05.8 mem=619.2M) ***
Peak Memory Usage was 606.5M
*** Finished trialRoute (cpu=0:00:06.2 mem=619.2M) ***
Extraction called for design 'Floating_point_co_processor_top' of instances=49451 and nets=53055 using extraction engine 'preRoute' .
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
Default RC Extraction called for design Floating_point_co_processor_top.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
RCMode: Default
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res Scaling Factor : 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Default RC Extraction DONE (CPU Time: 0:00:00.2 Real Time: 0:00:00.0 MEM: 603.512M)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.1, MEM = 616.3M)
Number of Loop : 0
Start delay calculation (mem=616.293M)...
Delay calculation completed. (cpu=0:00:03.9 real=0:00:03.0 mem=618.793M 0)
*** CDM Built up (cpu=0:00:05.5 real=0:00:05.0 mem= 618.8M) ***
**optDesign ... cpu = 0:02:04, real = 0:02:05, mem = 618.8M **
*info: Start fixing DRV (Mem = 618.79M) ...
*info: Options = -maxCap -maxTran -noMaxFanout -sensitivity -backward -reduceBuffer -secondPreCtsDrv -maxIter 1
*info: Start fixing DRV iteration 1 ...
*** Starting dpFixDRCViolation (618.8M)
*info: 105 io nets excluded
*info: 2 clock nets excluded
*info: 2 special nets excluded.
*info: 1771 no-driver nets excluded.
*** Starting multi-driver net buffering ***
*summary: 0 non-ignored multi-driver nets.
*** Finished buffering multi-driver nets (CPU=0:00:00.6, MEM=618.8M) ***
Start fixing design rules ... (0:00:00.6 619.8M)
Done fixing design rule (0:00:01.5 619.9M)
Summary:
107 buffers added on 103 nets (with 30 drivers resized)
Density after buffering = 0.397850
*** Completed dpFixDRCViolation (0:00:02.3 618.9M)
Re-routed 332 nets
Extraction called for design 'Floating_point_co_processor_top' of instances=49558 and nets=53162 using extraction engine 'preRoute' .
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
Default RC Extraction called for design Floating_point_co_processor_top.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
RCMode: Default
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res Scaling Factor : 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Default RC Extraction DONE (CPU Time: 0:00:00.1 Real Time: 0:00:00.0 MEM: 618.922M)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.1, MEM = 615.9M)
Number of Loop : 0
Start delay calculation (mem=615.871M)...
Delay calculation completed. (cpu=0:00:03.9 real=0:00:04.0 mem=618.793M 0)
*** CDM Built up (cpu=0:00:05.5 real=0:00:05.0 mem= 618.8M) ***
*info: DRV Fixing Iteration 1.
*info: Remaining violations:
*info: Max cap violations: 0
*info: Max tran violations: 0
*info: Prev Max cap violations: 12
*info: Prev Max tran violations: 0
*info:
*info: Completed fixing DRV (CPU Time = 0:00:10, Mem = 618.79M).
**optDesign ... cpu = 0:02:14, real = 0:02:15, mem = 618.8M **
*** Timing NOT met, worst failing slack is -9.636
*** Check timing (0:00:00.5)
*** Starting optCritPath ***
*info: 105 io nets excluded
*info: 2 clock nets excluded
*info: 2 special nets excluded.
*info: 1771 no-driver nets excluded.
Density : 0.3979
Max route overflow : 0.0166
Current slack : -9.636 ns, density : 0.3979
Current slack : -9.636 ns, density : 0.3979
Current slack : -9.636 ns, density : 0.3978
Current slack : -9.636 ns, density : 0.3978
Current slack : -9.211 ns, density : 0.3979
Current slack : -9.211 ns, density : 0.3979
Current slack : -9.182 ns, density : 0.3979
Current slack : -9.182 ns, density : 0.3978
Current slack : -9.182 ns, density : 0.3978
Current slack : -9.171 ns, density : 0.3978
Current slack : -9.171 ns, density : 0.3978
Current slack : -9.171 ns, density : 0.3978
Current slack : -8.796 ns, density : 0.3980
Current slack : -8.796 ns, density : 0.3980
Current slack : -8.649 ns, density : 0.3985
Current slack : -8.649 ns, density : 0.3985
Current slack : -8.544 ns, density : 0.3987
Current slack : -8.513 ns, density : 0.3987
Current slack : -8.249 ns, density : 0.3997
Current slack : -8.214 ns, density : 0.3998
Current slack : -8.189 ns, density : 0.3997
Current slack : -8.150 ns, density : 0.3997
Current slack : -8.011 ns, density : 0.4011
Current slack : -7.994 ns, density : 0.4011
Current slack : -7.941 ns, density : 0.4011
Current slack : -7.902 ns, density : 0.4011
Current slack : -7.809 ns, density : 0.4018
Current slack : -7.792 ns, density : 0.4019
Current slack : -7.792 ns, density : 0.4019
Current slack : -7.780 ns, density : 0.4019
Current slack : -7.733 ns, density : 0.4029
Current slack : -7.733 ns, density : 0.4029
Current slack : -7.733 ns, density : 0.4029
Current slack : -7.733 ns, density : 0.4029
Current slack : -7.708 ns, density : 0.4034
Current slack : -7.692 ns, density : 0.4042
Current slack : -7.630 ns, density : 0.4137
Current slack : -7.630 ns, density : 0.4139
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
*** Starting delays update (0:02:45 mem=652.7M) ***
*** Finished delays update (0:02:51 mem=651.1M) ***
Current slack : -7.613 ns, density : 0.4147
Current slack : -7.524 ns, density : 0.4147
Current slack : -7.490 ns, density : 0.4147
Current slack : -7.490 ns, density : 0.4146
Current slack : -7.490 ns, density : 0.4146
Current slack : -7.490 ns, density : 0.4147
Current slack : -7.458 ns, density : 0.4592
Current slack : -7.452 ns, density : 0.4593
Current slack : -7.452 ns, density : 0.4593
Current slack : -7.432 ns, density : 0.4593
Current slack : -7.432 ns, density : 0.4592
Current slack : -7.432 ns, density : 0.4592
Current slack : -7.432 ns, density : 0.4592