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encounter.log1
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Checking out Encounter license ...
Encounter_Digital_Impl_Sys_XL 9.1 license checkout succeeded.
You can run 2 CPU jobs with the base license that is currently checked out.
If required, use the setMultiCpuUsage command to enable multi-CPU processing.
This Encounter release has been compiled with OA version 22.04-p058.
*******************************************************************
* Copyright (c) Cadence Design Systems, Inc. 1996 - 2009. *
* All rights reserved. *
* *
* *
* *
* This program contains confidential and trade secret information *
* of Cadence Design Systems, Inc. and is protected by copyright *
* law and international treaties. Any reproduction, use, *
* distribution or disclosure of this program or any portion of it,*
* or any attempt to obtain a human-readable version of this *
* program, without the express, prior written consent of *
* Cadence Design Systems, Inc., is strictly prohibited. *
* *
* Cadence Design Systems, Inc. *
* 2655 Seely Avenue *
* San Jose, CA 95134, USA *
* *
* *
*******************************************************************
@(#)CDS: Encounter v09.11-s084_1 (64bit) 04/26/2010 12:41 (Linux 2.6)
@(#)CDS: NanoRoute v09.11-s008 NR100226-1806/USR63-UB (database version 2.30, 93.1.1) {superthreading v1.14}
@(#)CDS: CeltIC v09.11-s011_1 (64bit) 03/04/2010 14:24:46 (Linux 2.6.9-78.0.25.ELsmp)
@(#)CDS: CTE 09.11-s016_1 (64bit) Apr 8 2010 03:29:23 (Linux 2.6.9-78.0.25.ELlargesmp)
@(#)CDS: CPE v09.11-s023
--- Starting "Encounter v09.11-s084_1" on Fri Mar 6 13:26:19 2015 (mem=59.9M) ---
--- Running on ecegrid-thin1.ecn.purdue.edu (x86_64 w/Linux 2.6.32-504.8.1.el6.x86_64) ---
This version was compiled on Mon Apr 26 12:41:12 PDT 2010.
Set DBUPerIGU to 1000.
Set net toggle Scale Factor to 1.00
Set Shrink Factor to 1.00000
<CMD> loadConfig ./encounter.conf
Reading config file - ./encounter.conf
**WARN: (ENCEXT-1085): Option 'rda_Input(ui_res_scale)' used in configuration file './encounter.conf' is obsolete. The name will be converted into new format automatically if design is saved and then restored. Alternatively, update the configuration file to use names 'rda_Input(ui_preRoute_res)' and/or 'rda_Input(ui_postRoute_res)' for resistance scale factors to be used at preRoute/postRoute stages of the design . The obsolete name works in this release. But to avoid this warning and to ensure compatibility with future releases, update this option name.
Loading Lef file /package/eda/cells/OSU/v2.7/cadence/lib/ami05/lib/osu05_stdcells.lef...
**WARN: (ENCLF-108): There is no overlap layer defined in any lef file
so you are unable to create rectilinear partition in a hierarchical flow.
Set DBUPerIGU to M2 pitch 2400.
Initializing default via types and wire widths ...
Power Planner/ViaGen version 8.1.46 promoted on 02/17/2009.
viaInitial starts at Fri Mar 6 13:27:17 2015
**WARN: (ENCPP-544): You didn't use the STACK keyword with the LEF SAMENET rule. Stacked vias might not be created correctly.
SAMENET cc via 0.150 ;
**WARN: (ENCPP-544): You didn't use the STACK keyword with the LEF SAMENET rule. Stacked vias might not be created correctly.
SAMENET via via2 0.150 ;
**WARN: (ENCPP-557): a single-layer VIARULE GENERATE for turn-vias is obsolete and is being ignored. You should remove this statement from your LEF file.
VIARULE TURN1 GENERATE
**WARN: (ENCPP-557): a single-layer VIARULE GENERATE for turn-vias is obsolete and is being ignored. You should remove this statement from your LEF file.
VIARULE TURN2 GENERATE
**WARN: (ENCPP-557): a single-layer VIARULE GENERATE for turn-vias is obsolete and is being ignored. You should remove this statement from your LEF file.
VIARULE TURN3 GENERATE
viaInitial ends at Fri Mar 6 13:27:17 2015
Reading netlist ...
Backslashed names will retain backslash and a trailing blank character.
Reading verilog netlist 'mapped/lab7_layout_design.v'
Inserting temporary buffers to remove assignment statements.
*** Memory Usage v0.159.2.6.2.1 (Current mem = 385.059M, initial mem = 59.902M) ***
*** End netlist parsing (cpu=0:00:00.0, real=0:00:00.0, mem=385.1M) ***
Set top cell to lab7_layout_design.
Reading common timing library '/package/eda/cells/OSU/v2.7/cadence/lib/ami05/lib/osu05_stdcells.tlf' ...
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'A' of cell 'AND2X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'B' of cell 'AND2X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND2X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'A' of cell 'AND2X2' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'B' of cell 'AND2X2' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AND2X2' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'A' of cell 'AOI21X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'B' of cell 'AOI21X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'C' of cell 'AOI21X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AOI21X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'A' of cell 'AOI22X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'B' of cell 'AOI22X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'C' of cell 'AOI22X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'D' of cell 'AOI22X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'AOI22X1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'A' of cell 'BUFX2' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'BUFX2' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'A' of cell 'BUFX4' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell 'BUFX4' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (TECHLIB-436): Attribute 'fanout_load' on 'input/inout' pin 'A' of cell 'CLKBUF1' is not defined in the library. Either define this value in the library or use set_default_timing_library to pick these values from a default library.
**WARN: (ENCTS-124): Timing library description of pin 'YPAD' is missing from cell 'PADVDD' in timing library 'osu05_stdcells'.
**WARN: (ENCTS-124): Timing library description of pin 'YPAD' is missing from cell 'PADGND' in timing library 'osu05_stdcells'.
read 39 cells in library 'osu05_stdcells'
*** End library_loading (cpu=0.00min, mem=0.3M, fe_cpu=0.11min, fe_mem=385.4M) ***
Starting recursive module instantiation check.
No recursion found.
Building hierarchical netlist for Cell lab7_layout_design ...
*** Netlist is unique.
** info: there are 56 modules.
** info: there are 838 stdCell insts.
** info: there are 18 Pad insts.
*** Memory Usage v0.159.2.6.2.1 (Current mem = 386.875M, initial mem = 59.902M) ***
*info - Done with setDoAssign with 1 assigns removed and 0 assigns could not be removed.
CTE reading timing constraint file 'encounter.pt' ...
INFO (CTE): constraints read successfully
*** Read timing constraints (cpu=0:00:00.0 mem=395.8M) ***
Total number of combinational cells: 26
Total number of sequential cells: 4
Total number of tristate cells: 2
Total number of level shifter cells: 0
Total number of power gating cells: 0
Total number of isolation cells: 0
Total number of power switch cells: 0
Total number of pulse generator cells: 0
Total number of always on buffers: 0
Total number of retention cells: 0
List of usable buffers: BUFX2 BUFX4 CLKBUF1
Total number of usable buffers: 3
List of unusable buffers:
Total number of unusable buffers: 0
List of usable inverters: INVX2 INVX1 INVX4 INVX8
Total number of usable inverters: 4
List of unusable inverters:
Total number of unusable inverters: 0
List of identified usable delay cells: CLKBUF2 CLKBUF3
Total number of identified usable delay cells: 2
List of identified unusable delay cells:
Total number of identified unusable delay cells: 0
*info: set bottom ioPad orient R180
Reading IO assignment file "encounter.io" ...
Horizontal Layer M1 offset = 1500 (derived)
Vertical Layer M2 offset = 1200 (derived)
Set Using Default Delay Limit as 1000.
Set Default Net Delay as 1000 ps.
Set Default Net Load as 0.5 pF.
Set Input Pin Transition Delay as 120 ps.
PreRoute Cap Scale Factor : 1.00
PreRoute Res Scale Factor : 1.00
PostRoute Cap Scale Factor : 1.00
PostRoute Res Scale Factor : 1.00
PostRoute XCap Scale Factor : 1.00
PreRoute Clock Cap Scale Factor : 1.00 [Derived from postRoute_cap (effortLevel low)]
PreRoute Clock Res Scale Factor : 1.00 [Derived from postRoute_res (effortLevel low)]
PostRoute Clock Cap Scale Factor : 1.00 [Derived from postRoute_cap (effortLevel low)]
PostRoute Clock Res Scale Factor : 1.00 [Derived from postRoute_res (effortLevel low)]
**WARN: (ENCOPT-3465): The buffer cells were automatically identified. The command setBufFootPrint is ignored. If you want to force the tool to honor this setting, you have to load a footprint file through the loadFootPrint command.
**WARN: (ENCOPT-3466): The inverter cells were automatically identified. The command setInvFootPrint is ignored. If you want to force the tool to honor this setting, you have to load a footprint file through the loadFootPrint command.
**WARN: (ENCOPT-3467): The delay cells were automatically identified. The command setDelayFootPrint is ignored. If you want to force the tool to honor this setting, you have to load a footprint file through the loadFootPrint command.
<CMD> floorPlan -r 2.0 0.6 50 50 50 50
Snap core to left to manufacture grid: 49.9500.
Snap core to bottom to manufacture grid: 49.9500.
Snap core to right to manufacture grid: 49.9500.
Snap core to top to manufacture grid: 49.9500.
Adjusting Core to Left to: 50.4000. Core to Bottom to: 51.0000.
Horizontal Layer M1 offset = 1500 (derived)
Vertical Layer M2 offset = 1200 (derived)
<CMD> addRing -spacing_bottom 9.9 -width_left 9.9 -width_bottom 9.9 -width_top 9.9 -spacing_top 9.9 -layer_bottom metal1 -width_right 9.9 -around core -center 1 -layer_top metal1 -spacing_right 9.9 -spacing_left 9.9 -layer_right metal2 -layer_left metal2 -offset_top 9.9 -offset_bottom 9.9 -offset_left 9.9 -offset_right 9.9 -nets { gnd vdd }
The power planner created 8 wires.
<CMD> setPlaceMode -congEffort medium
<CMD> placeDesign -inPlaceOpt
*** Starting placeDesign concurrent flow ***
*** Start deleteBufferTree ***
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.0, MEM = 408.2M)
Number of Loop : 0
Start delay calculation (mem=408.168M)...
Delay calculation completed. (cpu=0:00:00.0 real=0:00:00.0 mem=412.398M 0)
*** CDM Built up (cpu=0:00:00.1 real=0:00:00.0 mem= 412.4M) ***
Info: Detect buffers to remove automatically.
Analyzing netlist ...
Updating netlist
*summary: 67 instances (buffers/inverters) removed
*** Finish deleteBufferTree (0:00:00.1) ***
Extracting standard cell pins and blockage ......
Pin and blockage extraction finished
Extracting macro/IO cell pins and blockage ......
Pin and blockage extraction finished
*** Starting "NanoPlace(TM) placement v0.892.2.8.2.1 (mem=412.4M)" ...
*** Build Buffered Sizing Timing Model
(cpu=0:00:00.0 mem=412.4M) ***
*** Build Virtual Sizing Timing Model
(cpu=0:00:00.0 mem=412.4M) ***
Options: timingDriven ignoreScan ignoreSpare pinGuide gpeffort=medium
**WARN: (ENCDB-2082): Scan chains were not defined, -ignoreScan option will be ignored.
Please first define the scan chains before using this option.
#std cell=771 #block=0 (0 floating + 0 preplaced) #ioInst=44 #net=799 #term=2553 #term/net=3.20, #fixedIo=44, #floatIo=0, #fixedPin=16, #floatPin=0
stdCell: 771 single + 0 double + 0 multi
Total standard cell length = 11.2704 (mm), area = 0.3381 (mm^2)
Average module density = 0.392.
Density for the design = 0.392.
= stdcell_area 4696 (338112 um^2) / alloc_area 11988 (863136 um^2).
Pin Density = 0.544.
= total # of pins 2553 / total Instance area 4696.
Iteration 1: Total net bbox = 2.198e+04 (1.36e+04 8.40e+03)
Est. stn bbox = 2.198e+04 (1.36e+04 8.40e+03)
cpu = 0:00:00.0 real = 0:00:00.0 mem = 412.6M
Iteration 2: Total net bbox = 2.198e+04 (1.36e+04 8.40e+03)
Est. stn bbox = 2.198e+04 (1.36e+04 8.40e+03)
cpu = 0:00:00.0 real = 0:00:00.0 mem = 412.6M
Iteration 3: Total net bbox = 2.310e+04 (1.46e+04 8.51e+03)
Est. stn bbox = 2.310e+04 (1.46e+04 8.51e+03)
cpu = 0:00:00.1 real = 0:00:00.0 mem = 412.6M
Iteration 4: Total net bbox = 5.560e+04 (2.49e+04 3.07e+04)
Est. stn bbox = 5.560e+04 (2.49e+04 3.07e+04)
cpu = 0:00:00.2 real = 0:00:00.0 mem = 412.6M
Iteration 5: Total net bbox = 7.360e+04 (3.58e+04 3.78e+04)
Est. stn bbox = 7.360e+04 (3.58e+04 3.78e+04)
cpu = 0:00:00.2 real = 0:00:00.0 mem = 412.6M
Iteration 6: Total net bbox = 8.095e+04 (3.83e+04 4.26e+04)
Est. stn bbox = 8.095e+04 (3.83e+04 4.26e+04)
cpu = 0:00:00.2 real = 0:00:00.0 mem = 412.7M
Iteration 7: Total net bbox = 8.359e+04 (4.02e+04 4.33e+04)
Est. stn bbox = 9.964e+04 (4.74e+04 5.22e+04)
cpu = 0:00:00.8 real = 0:00:01.0 mem = 412.6M
Iteration 8: Total net bbox = 8.359e+04 (4.02e+04 4.33e+04)
Est. stn bbox = 9.964e+04 (4.74e+04 5.22e+04)
cpu = 0:00:00.2 real = 0:00:00.0 mem = 412.6M
Iteration 9: Total net bbox = 8.910e+04 (4.36e+04 4.55e+04)
Est. stn bbox = 1.044e+05 (5.06e+04 5.38e+04)
cpu = 0:00:00.3 real = 0:00:00.0 mem = 412.6M
Iteration 10: Total net bbox = 9.362e+04 (4.75e+04 4.61e+04)
Est. stn bbox = 1.092e+05 (5.48e+04 5.45e+04)
cpu = 0:00:00.0 real = 0:00:00.0 mem = 412.6M
*** cost = 9.362e+04 (4.75e+04 4.61e+04) (cpu for global=0:00:01.2) real=0:00:01.0***
Core Placement runtime cpu: 0:00:01.0 real: 0:00:01.0
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode. (cpu=0:00:00.1, real=0:00:00.0)
move report: preRPlace moves 87 insts, mean move: 5.24 um, max move: 36.00 um
max move on inst (I0/LD/T_FIFO/IP_FIFO/URFC/rwptr_r2_reg[3]): (1046.40, 501.00) --> (1082.40, 501.00)
Placement tweakage begins.
wire length = 9.344e+04 = 4.736e+04 H + 4.609e+04 V
wire length = 8.930e+04 = 4.355e+04 H + 4.575e+04 V
Placement tweakage ends.
move report: wireLenOpt moves 154 insts, mean move: 26.28 um, max move: 52.80 um
max move on inst (I0/LD/T_SR_0/U16): (393.60, 1281.00) --> (446.40, 1281.00)
move report: rPlace moves 226 insts, mean move: 19.65 um, max move: 52.80 um
max move on inst (I0/LD/T_FIFO/IP_FIFO/UFIFORAM/U124): (784.80, 711.00) --> (837.60, 711.00)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 52.80 um
inst (I0/LD/T_FIFO/IP_FIFO/UFIFORAM/U124) with max move: (784.8, 711) -> (837.6, 711)
mean (X+Y) = 19.65 um
Total instances flipped for WireLenOpt: 30
Total instances flipped, including legalization: 372
Total instances moved : 226
*** cpu=0:00:00.1 mem=412.6M mem(used)=0.0M***
Total net length = 8.933e+04 (4.355e+04 4.578e+04) (ext = 0.000e+00)
*** End of Placement (cpu=0:00:01.3, real=0:00:01.0, mem=412.6M) ***
default core: bins with density > 0.75 = 0 % ( 0 / 12 )
*** Free Virtual Timing Model ...(mem=405.8M)
Starting IO pin assignment...
**WARN: (ENCSP-9025): No scan chain specified/traced.
setAnalysisMode -domain allClockDomain -checkType setup -skew true -usefulSkew false -log true -warn true -caseAnalysis true -sequentialConstProp false -moduleIOCstr true -clockPropagation forcedIdeal -clkSrcPath false -timingSelfLoopsNoSkew false -asyncChecks async -useOutputPinCap true -latch true -latchDelayCalIteration 2 -timeBorrowing true -latchFullDelayCal false -clockGatingCheck true -enableMultipleDriveNet true -analysisType single -cppr false -clkNetsMarking beforeConstProp -honorVirtualPartition false -honorClockDomains true
**WARN: (ENCOPT-6055): The following cells have a dont_touch property but without being dont_use.
Such configuration can impact the timing closure because they can be inserted in the netlist but never transformed again.
It is recommended that you apply a dont_use attribute on them.
Cell PADVDD is dont_touch but not dont_use
Cell PADNC is dont_touch but not dont_use
Cell PADGND is dont_touch but not dont_use
Cell PADFC is dont_touch but not dont_use
...
Reporting only the 20 first cells found...
**optDesign ... cpu = 0:00:00, real = 0:00:00, mem = 405.8M **
Added -handlePreroute to trialRouteMode
*** optDesign -preCTS ***
DRC Margin: user margin 0.0; extra margin 0.2
Setup Target Slack: user slack 0.0; extra slack 0.1
Hold Target Slack: user slack 0.0
*info: Setting setup target slack to 0.100
*info: Hold target slack is 0.000
*** CTE mode ***
*** Starting trialRoute (mem=407.0M) ***
There are 0 pin guide points passed to trialRoute.
**WARN: (ENCTR-2325): 15 nets connect a pad term to a fterm without geometry and will not be routed.
Options: -handlePreroute -noPinGuide
Nr of prerouted/Fixed nets = 16
routingBox: (1200 1500) (1498800 1780500)
coreBox: (350400 351000) (1150050 1431000)
Number of multi-gpin terms=0, multi-gpins=0, moved blk term=1/2
Phase 1a route (0:00:00.0 408.4M):
Est net length = 1.106e+05um = 5.458e+04H + 5.599e+04V
Usage: (20.1%H 30.5%V) = (6.724e+04um 1.214e+05um) = (5471 4047)
Obstruct: 2321 = 1088 (27.5%H) + 1233 (31.2%V)
Overflow: 21 = 0 (0.00% H) + 21 (0.79% V)
Phase 1b route (0:00:00.0 410.9M):
Usage: (20.0%H 30.5%V) = (6.705e+04um 1.214e+05um) = (5455 4047)
Overflow: 20 = 0 (0.00% H) + 20 (0.75% V)
Phase 1c route (0:00:00.0 410.9M):
Usage: (19.9%H 30.6%V) = (6.680e+04um 1.215e+05um) = (5434 4051)
Overflow: 17 = 0 (0.00% H) + 17 (0.64% V)
Phase 1d route (0:00:00.0 410.9M):
Usage: (19.9%H 30.6%V) = (6.683e+04um 1.216e+05um) = (5437 4053)
Overflow: 14 = 0 (0.00% H) + 14 (0.53% V)
Phase 1e route (0:00:00.0 411.6M):
Usage: (19.9%H 30.6%V) = (6.676e+04um 1.216e+05um) = (5431 4054)
Overflow: 14 = 0 (0.00% H) + 14 (0.51% V)
Phase 1f route (0:00:00.0 411.6M):
Usage: (20.0%H 30.6%V) = (6.693e+04um 1.218e+05um) = (5445 4060)
Overflow: 5 = 0 (0.00% H) + 5 (0.18% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-1: 0 0.00% 5 0.18%
--------------------------------------
0: 2 0.07% 204 7.50%
1: 95 3.32% 250 9.19%
2: 13 0.45% 386 14.20%
3: 98 3.42% 527 19.38%
4: 56 1.96% 494 18.17%
5: 146 5.10% 750 27.58%
6: 329 11.49% 25 0.92%
7: 577 20.15% 10 0.37%
8: 601 20.98% 11 0.40%
9: 440 15.36% 13 0.48%
10: 375 13.09% 44 1.62%
13: 1 0.03% 0 0.00%
14: 65 2.27% 0 0.00%
15: 66 2.30% 0 0.00%
Global route (cpu=0.0s real=0.0s 409.1M)
*** After '-updateRemainTrks' operation:
Usage: (20.0%H 30.6%V) = (6.693e+04um 1.218e+05um) = (5445 4060)
Overflow: 5 = 0 (0.00% H) + 5 (0.18% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-1: 0 0.00% 5 0.18%
--------------------------------------
0: 2 0.07% 204 7.50%
1: 95 3.32% 250 9.19%
2: 13 0.45% 386 14.20%
3: 98 3.42% 527 19.38%
4: 56 1.96% 494 18.17%
5: 146 5.10% 750 27.58%
6: 329 11.49% 25 0.92%
7: 577 20.15% 10 0.37%
8: 601 20.98% 11 0.40%
9: 440 15.36% 13 0.48%
10: 375 13.09% 44 1.62%
13: 1 0.03% 0 0.00%
14: 65 2.27% 0 0.00%
15: 66 2.30% 0 0.00%
*** Completed Phase 1 route (0:00:00.0 407.1M) ***
Total length: 1.136e+05um, number of vias: 4886
M1(H) length: 0.000e+00um, number of vias: 2505
M2(V) length: 5.990e+04um, number of vias: 2381
M3(H) length: 5.373e+04um
*** Completed Phase 2 route (0:00:00.0 408.2M) ***
*** Finished all Phases (cpu=0:00:00.1 mem=408.2M) ***
Peak Memory Usage was 407.1M
*** Finished trialRoute (cpu=0:00:00.1 mem=408.2M) ***
Extraction called for design 'lab7_layout_design' of instances=815 and nets=803 using extraction engine 'preRoute' .
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
Default RC Extraction called for design lab7_layout_design.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
RCMode: Default
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res Scaling Factor : 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Default RC Extraction DONE (CPU Time: 0:00:00.0 Real Time: 0:00:00.0 MEM: 408.238M)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.0, MEM = 414.9M)
Number of Loop : 0
Start delay calculation (mem=414.891M)...
**WARN: (ENCEXT-2882): Unable to find resistance for via 'M3_M2' in capacitance table or LEF files. Check the capacitance table and LEF files. Assigning default value of 4.0 ohms.
**WARN: (ENCEXT-2882): Unable to find resistance for via 'M2_M1' in capacitance table or LEF files. Check the capacitance table and LEF files. Assigning default value of 4.0 ohms.
Delay calculation completed. (cpu=0:00:00.1 real=0:00:00.0 mem=415.121M 0)
*** CDM Built up (cpu=0:00:00.1 real=0:00:00.0 mem= 415.1M) ***
Info: 16 io nets excluded
Info: 2 clock nets excluded from IPO operation.
Netlist preparation processing...
Removed 0 instance
*info: Marking 0 isolation instances dont touch
*info: Marking 0 level shifter instances dont touch
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
*** Starting delays update (0:00:08.3 mem=416.4M) ***
*** Finished delays update (0:00:08.5 mem=416.4M) ***
**optDesign ... cpu = 0:00:00, real = 0:00:01, mem = 416.2M **
*info: Start fixing DRV (Mem = 416.27M) ...
*info: Options = -maxCap -maxTran -noMaxFanout -sensitivity -backward -reduceBuffer -maxIter 1
*info: Start fixing DRV iteration 1 ...
*** Starting dpFixDRCViolation (416.3M)
*info: 16 io nets excluded
*info: 2 clock nets excluded
*info: 2 special nets excluded.
*info: 4 no-driver nets excluded.
*** Starting multi-driver net buffering ***
*summary: 0 non-ignored multi-driver nets.
*** Finished buffering multi-driver nets (CPU=0:00:00.0, MEM=416.3M) ***
*info: There are 3 candidate Buffer cells
*info: There are 4 candidate Inverter cells
Initializing placement sections/sites ...
Density before buffering = 0.391725
Start fixing design rules ... (0:00:00.0 416.3M)
Done fixing design rule (0:00:00.1 416.5M)
Summary:
12 buffers added on 12 nets (with 0 driver resized)
Density after buffering = 0.394811
*** Completed dpFixDRCViolation (0:00:00.1 416.5M)
Re-routed 24 nets
Extraction called for design 'lab7_layout_design' of instances=827 and nets=815 using extraction engine 'preRoute' .
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
Default RC Extraction called for design lab7_layout_design.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
RCMode: Default
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res Scaling Factor : 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Default RC Extraction DONE (CPU Time: 0:00:00.0 Real Time: 0:00:00.0 MEM: 416.473M)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.0, MEM = 416.2M)
Number of Loop : 0
Start delay calculation (mem=416.242M)...
Delay calculation completed. (cpu=0:00:00.1 real=0:00:00.0 mem=416.473M 0)
*** CDM Built up (cpu=0:00:00.1 real=0:00:00.0 mem= 416.5M) ***
*info: DRV Fixing Iteration 1.
*info: Remaining violations:
*info: Max cap violations: 0
*info: Max tran violations: 0
*info: Prev Max cap violations: 6
*info: Prev Max tran violations: 0
*info:
*info: Completed fixing DRV (CPU Time = 0:00:00, Mem = 416.47M).
**optDesign ... cpu = 0:00:01, real = 0:00:01, mem = 416.5M **
*** Starting optFanout (416.5M)
*info: 16 io nets excluded
*info: 2 clock nets excluded
*info: 2 special nets excluded.
*info: 4 no-driver nets excluded.
*** Starting multi-driver net buffering ***
*summary: 0 non-ignored multi-driver nets.
*** Finished buffering multi-driver nets (CPU=0:00:00.0, MEM=416.5M) ***
Start fixing timing ... (0:00:00.0 416.5M)
*info: Buffered 0 large fanout net (> 100 terms)
Done fixing timing (0:00:00.1 416.5M)
Summary:
0 buffer added on 0 net (with 0 driver resized)
Density after buffering = 0.394811
*** Completed optFanout (0:00:00.1 416.5M)
**optDesign ... cpu = 0:00:01, real = 0:00:01, mem = 416.5M **
*** Timing Is met
*** Check timing (0:00:00.0)
************ Recovering area ***************
Info: 16 io nets excluded
Info: 2 clock nets excluded from IPO operation.
*** Starting Area Reclaim ***
** Density before area reclaim = 39.481% **
*** starting 1-st reclaim pass: 648 instances
*** starting 2-nd reclaim pass: 622 instances
*** starting 3-rd reclaim pass: 189 instances
** Area Reclaim Summary: Buffer Deletion = 2 Declone = 24 Downsize = 21 **
** Density Change = 0.792% **
** Density after area reclaim = 38.689% **
*** Finished Area Reclaim (0:00:00.3) ***
density before resizing = 38.689%
* summary of transition time violation fixes:
*summary: 4 instances changed cell type
density after resizing = 38.722%
*** Starting trialRoute (mem=416.9M) ***
There are 0 pin guide points passed to trialRoute.
Options: -handlePreroute -keepMarkedOptRoutes -noPinGuide
Nr of prerouted/Fixed nets = 16
routingBox: (1200 1500) (1498800 1780500)
coreBox: (350400 351000) (1150050 1431000)
Number of multi-gpin terms=0, multi-gpins=0, moved blk term=1/2
Phase 1a route (0:00:00.0 418.2M):
Est net length = 1.107e+05um = 5.476e+04H + 5.590e+04V
Usage: (20.1%H 30.4%V) = (6.729e+04um 1.209e+05um) = (5474 4028)
Obstruct: 2321 = 1088 (27.5%H) + 1233 (31.2%V)
Overflow: 22 = 0 (0.00% H) + 22 (0.82% V)
Phase 1b route (0:00:00.0 420.7M):
Usage: (20.0%H 30.4%V) = (6.709e+04um 1.209e+05um) = (5457 4028)
Overflow: 20 = 0 (0.00% H) + 20 (0.75% V)
Phase 1c route (0:00:00.0 420.7M):
Usage: (19.9%H 30.4%V) = (6.679e+04um 1.210e+05um) = (5432 4033)
Overflow: 17 = 0 (0.00% H) + 17 (0.64% V)
Phase 1d route (0:00:00.0 420.7M):
Usage: (19.9%H 30.5%V) = (6.682e+04um 1.211e+05um) = (5435 4036)
Overflow: 14 = 0 (0.00% H) + 14 (0.53% V)
Phase 1e route (0:00:00.0 421.4M):
Usage: (19.9%H 30.5%V) = (6.679e+04um 1.212e+05um) = (5432 4038)
Overflow: 14 = 0 (0.00% H) + 14 (0.51% V)
Phase 1f route (0:00:00.0 421.4M):
Usage: (20.0%H 30.5%V) = (6.696e+04um 1.213e+05um) = (5446 4044)
Overflow: 5 = 0 (0.00% H) + 5 (0.18% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-1: 0 0.00% 5 0.18%
--------------------------------------
0: 2 0.07% 206 7.58%
1: 95 3.32% 243 8.94%
2: 12 0.42% 380 13.98%
3: 95 3.32% 532 19.57%
4: 59 2.06% 502 18.46%
5: 158 5.52% 748 27.51%
6: 316 11.03% 25 0.92%
7: 582 20.32% 10 0.37%
8: 597 20.84% 11 0.40%
9: 437 15.26% 13 0.48%
10: 379 13.23% 44 1.62%
13: 1 0.03% 0 0.00%
14: 65 2.27% 0 0.00%
15: 66 2.30% 0 0.00%
Global route (cpu=0.0s real=0.0s 418.8M)
*** After '-updateRemainTrks' operation:
Usage: (20.0%H 30.5%V) = (6.696e+04um 1.213e+05um) = (5446 4044)
Overflow: 5 = 0 (0.00% H) + 5 (0.18% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-1: 0 0.00% 5 0.18%
--------------------------------------
0: 2 0.07% 206 7.58%
1: 95 3.32% 243 8.94%
2: 12 0.42% 380 13.98%
3: 95 3.32% 532 19.57%
4: 59 2.06% 502 18.46%
5: 158 5.52% 748 27.51%
6: 316 11.03% 25 0.92%
7: 582 20.32% 10 0.37%
8: 597 20.84% 11 0.40%
9: 437 15.26% 13 0.48%
10: 379 13.23% 44 1.62%
13: 1 0.03% 0 0.00%
14: 65 2.27% 0 0.00%
15: 66 2.30% 0 0.00%
*** Completed Phase 1 route (0:00:00.0 416.9M) ***
Total length: 1.136e+05um, number of vias: 4833
M1(H) length: 0.000e+00um, number of vias: 2471
M2(V) length: 5.976e+04um, number of vias: 2362
M3(H) length: 5.384e+04um
*** Completed Phase 2 route (0:00:00.1 416.9M) ***
*** Finished all Phases (cpu=0:00:00.1 mem=416.9M) ***
Peak Memory Usage was 416.9M
*** Finished trialRoute (cpu=0:00:00.1 mem=416.9M) ***
Extraction called for design 'lab7_layout_design' of instances=801 and nets=790 using extraction engine 'preRoute' .
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
Default RC Extraction called for design lab7_layout_design.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
RCMode: Default
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res Scaling Factor : 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Default RC Extraction DONE (CPU Time: 0:00:00.0 Real Time: 0:00:00.0 MEM: 410.172M)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.0, MEM = 416.7M)
Number of Loop : 0
Start delay calculation (mem=416.688M)...
Delay calculation completed. (cpu=0:00:00.1 real=0:00:01.0 mem=416.918M 0)
*** CDM Built up (cpu=0:00:00.1 real=0:00:01.0 mem= 416.9M) ***
**optDesign ... cpu = 0:00:01, real = 0:00:02, mem = 416.9M **
*** Timing Is met
*** Check timing (0:00:00.0)
setClockDomains -fromType register -toType register
**WARN: (ENCCTE-318): Paths not in the reg2reg domain will be added 1000ns slack adjustment
*** Timing Is met
*** Check timing (0:00:00.0)
**optDesign ... cpu = 0:00:02, real = 0:00:02, mem = 417.2M **
*** Finished optDesign ***
*** Starting "NanoPlace(TM) placement v0.892.2.8.2.1 (mem=417.2M)" ...
*** Build Buffered Sizing Timing Model
(cpu=0:00:00.0 mem=410.4M) ***
*** Build Virtual Sizing Timing Model
(cpu=0:00:00.0 mem=410.4M) ***
Options: timingDriven ignoreSpare pinGuide gpeffort=medium
#std cell=757 #block=0 (0 floating + 0 preplaced) #ioInst=44 #net=785 #term=2519 #term/net=3.21, #fixedIo=44, #floatIo=0, #fixedPin=16, #floatPin=0
stdCell: 757 single + 0 double + 0 multi
Total standard cell length = 11.1408 (mm), area = 0.3342 (mm^2)
Average module density = 0.387.
Density for the design = 0.387.
= stdcell_area 4642 (334224 um^2) / alloc_area 11988 (863136 um^2).
Pin Density = 0.543.
= total # of pins 2519 / total Instance area 4642.
Iteration 10: Total net bbox = 8.841e+04 (4.37e+04 4.47e+04)
Est. stn bbox = 1.040e+05 (5.09e+04 5.31e+04)
cpu = 0:00:00.2 real = 0:00:00.0 mem = 417.3M
Iteration 11: Total net bbox = 9.141e+04 (4.69e+04 4.45e+04)
Est. stn bbox = 1.071e+05 (5.44e+04 5.28e+04)
cpu = 0:00:00.0 real = 0:00:00.0 mem = 417.3M
*** cost = 9.141e+04 (4.69e+04 4.45e+04) (cpu for global=0:00:00.2) real=0:00:00.0***
Core Placement runtime cpu: 0:00:00.2 real: 0:00:00.0
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode. (cpu=0:00:00.1, real=0:00:00.0)
move report: preRPlace moves 81 insts, mean move: 5.84 um, max move: 16.80 um
max move on inst (I0/LD/T_SR_1/curr_val_reg[5]): (396.00, 1191.00) --> (412.80, 1191.00)
Placement tweakage begins.
wire length = 9.141e+04 = 4.694e+04 H + 4.447e+04 V
wire length = 8.727e+04 = 4.308e+04 H + 4.419e+04 V
Placement tweakage ends.
move report: wireLenOpt moves 136 insts, mean move: 26.31 um, max move: 60.00 um
max move on inst (I0/LD/T_FIFO/IP_FIFO/UFIFORAM/U123): (813.60, 741.00) --> (873.60, 741.00)
move report: rPlace moves 207 insts, mean move: 18.81 um, max move: 60.00 um
max move on inst (I0/LD/T_FIFO/IP_FIFO/UFIFORAM/U123): (813.60, 741.00) --> (873.60, 741.00)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 60.00 um
inst (I0/LD/T_FIFO/IP_FIFO/UFIFORAM/U123) with max move: (813.6, 741) -> (873.6, 741)
mean (X+Y) = 18.81 um
Total instances flipped for WireLenOpt: 29
Total instances flipped, including legalization: 361
Total instances moved : 207
*** cpu=0:00:00.1 mem=417.3M mem(used)=0.0M***
Total net length = 8.726e+04 (4.309e+04 4.417e+04) (ext = 0.000e+00)
*** End of Placement (cpu=0:00:00.5, real=0:00:00.0, mem=417.3M) ***
default core: bins with density > 0.75 = 0 % ( 0 / 12 )
*** Free Virtual Timing Model ...(mem=410.5M)
Starting IO pin assignment...
**WARN: (ENCSP-9025): No scan chain specified/traced.
*** Finishing placeDesign concurrent flow ***
**placeDesign ... cpu = 0: 0: 4, real = 0: 0: 3, mem = 410.5M **
**WARN: (ENCEXT-3493): Extraction mode changed by calling extraction setup command 'setExtractRCMode'. Therefore, parasitic data in the tool generated as per previous mode is deleted. Call of extractRC/spefIn will generate/bring parasitic data in the tool as per current mode.
<CMD> checkPlace
Begin checking placement ...
*info: Placed = 757
*info: Unplaced = 0
Placement Density:38.72%(334224/863136)
<CMD> sroute -noBlockPins -noPadRings
**WARN: (ENCSR-4053): SRoute option "-noBlockPins" is obsolete and has been replaced by "-connect". The obsolete option still works in this release, but to avoid this warning and to ensure compatibility with future releases, update your script to use "-connect".
**WARN: (ENCSR-4053): SRoute option "-noPadRings" is obsolete and has been replaced by "-connect". The obsolete option still works in this release, but to avoid this warning and to ensure compatibility with future releases, update your script to use "-connect".
No routing obstructions were found in the design.
*** Begin SPECIAL ROUTE on Fri Mar 6 13:27:21 2015 ***
Sroute/fcroute version 8.1.46 promoted on 02/17/2009.
SPECIAL ROUTE ran on directory: /home/ecegrid/a/mg76/ece337/Lab7
SPECIAL ROUTE ran on machine: ecegrid-thin1.ecn.purdue.edu (Linux 2.6.32-504.8.1.el6.x86_64 Xeon 3.06Ghz)
Begin option processing ...
(from .sroute_15151.conf) srouteConnectPowerBump set to false
(from .sroute_15151.conf) routeSpecial set to true
(from .sroute_15151.conf) srouteConnectBlockPin set to false
(from .sroute_15151.conf) srouteFollowCorePinEnd set to 3
(from .sroute_15151.conf) srouteJogControl set to "preferWithChanges differentLayer"
(from .sroute_15151.conf) sroutePadPinAllPorts set to true
(from .sroute_15151.conf) sroutePreserveExistingRoutes set to true
End option processing: cpu: 0:00:00, real: 0:00:00, peak: 795.00 megs.
Reading DB technology information...
Finished reading DB technology information.
Reading floorplan and netlist information...
Finished reading floorplan and netlist information.
Read in 10 layers, 3 routing layers, 0 overlap layer
Read in 40 macros, 26 used
Read in 801 components
757 core components: 0 unplaced, 757 placed, 0 fixed
40 pad components: 0 unplaced, 0 placed, 40 fixed
4 other components: 0 unplaced, 0 placed, 4 fixed
Read in 16 logical pins
Read in 16 nets
Read in 2 special nets, 2 routed
Read in 1516 terminals
Begin power routing ...
CPU time for FollowPin 0 seconds
CPU time for FollowPin 0 seconds
Number of IO ports routed: 1 open: 1
Number of Stripe ports routed: 0
Number of Core ports routed: 74
Number of Followpin connections: 37
End power routing: cpu: 0:00:00, real: 0:00:00, peak: 802.00 megs.
Begin updating DB with routing results ...
Updating DB with 4 via definition ...
sroute post-processing starts at Fri Mar 6 13:27:21 2015
The viaGen is rebuilding shadow vias for net gnd.
sroute post-processing ends at Fri Mar 6 13:27:21 2015
sroute post-processing starts at Fri Mar 6 13:27:21 2015
The viaGen is rebuilding shadow vias for net vdd.
sroute post-processing ends at Fri Mar 6 13:27:21 2015
sroute: Total CPU time used = 0:0:0
sroute: Total Real time used = 0:0:0
sroute: Total Memory used = 0.51 megs
sroute: Total Peak Memory used = 411.19 megs
<CMD> trialRoute
*** Starting trialRoute (mem=411.2M) ***
There are 0 pin guide points passed to trialRoute.
**WARN: (ENCTR-2325): 15 nets connect a pad term to a fterm without geometry and will not be routed.
Options: -handlePreroute -keepMarkedOptRoutes -noPinGuide
Nr of prerouted/Fixed nets = 16
routingBox: (1200 1500) (1498800 1780500)
coreBox: (350400 351000) (1150050 1431000)
Number of multi-gpin terms=0, multi-gpins=0, moved blk term=1/5
Phase 1a route (0:00:00.0 412.5M):
Est net length = 1.087e+05um = 5.494e+04H + 5.374e+04V
Usage: (20.1%H 30.0%V) = (6.738e+04um 1.191e+05um) = (5482 3969)
Obstruct: 2324 = 1088 (27.5%H) + 1236 (31.3%V)
Overflow: 24 = 0 (0.00% H) + 24 (0.87% V)
Phase 1b route (0:00:00.0 415.0M):
Usage: (20.1%H 30.0%V) = (6.720e+04um 1.191e+05um) = (5467 3969)
Overflow: 22 = 0 (0.00% H) + 22 (0.80% V)
Phase 1c route (0:00:00.0 415.0M):
Usage: (20.0%H 30.0%V) = (6.696e+04um 1.191e+05um) = (5447 3970)
Overflow: 19 = 0 (0.00% H) + 19 (0.70% V)
Phase 1d route (0:00:00.0 415.0M):
Usage: (20.0%H 30.0%V) = (6.701e+04um 1.192e+05um) = (5451 3974)
Overflow: 15 = 0 (0.00% H) + 15 (0.55% V)
Phase 1e route (0:00:00.0 415.6M):
Usage: (20.0%H 30.0%V) = (6.699e+04um 1.193e+05um) = (5450 3975)
Overflow: 14 = 0 (0.00% H) + 14 (0.52% V)
Phase 1f route (0:00:00.0 415.6M):
Usage: (20.0%H 30.0%V) = (6.717e+04um 1.194e+05um) = (5465 3980)
Overflow: 6 = 0 (0.00% H) + 6 (0.22% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-1: 0 0.00% 6 0.22%
--------------------------------------
0: 2 0.07% 189 6.96%
1: 96 3.35% 246 9.06%
2: 10 0.35% 369 13.59%
3: 101 3.53% 551 20.29%
4: 87 3.04% 494 18.19%
5: 172 6.01% 754 27.76%
6: 280 9.78% 30 1.10%
7: 538 18.78% 9 0.33%
8: 606 21.16% 7 0.26%
9: 441 15.40% 19 0.70%
10: 399 13.93% 42 1.55%
13: 1 0.03% 0 0.00%
14: 65 2.27% 0 0.00%
15: 66 2.30% 0 0.00%
Global route (cpu=0.0s real=0.0s 413.1M)
*** After '-updateRemainTrks' operation:
Usage: (20.0%H 30.0%V) = (6.717e+04um 1.194e+05um) = (5465 3980)
Overflow: 6 = 0 (0.00% H) + 6 (0.22% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-1: 0 0.00% 6 0.22%
--------------------------------------
0: 2 0.07% 189 6.96%
1: 96 3.35% 246 9.06%
2: 10 0.35% 369 13.59%
3: 101 3.53% 551 20.29%
4: 87 3.04% 494 18.19%
5: 172 6.01% 754 27.76%
6: 280 9.78% 30 1.10%
7: 538 18.78% 9 0.33%
8: 606 21.16% 7 0.26%
9: 441 15.40% 19 0.70%
10: 399 13.93% 42 1.55%
13: 1 0.03% 0 0.00%
14: 65 2.27% 0 0.00%
15: 66 2.30% 0 0.00%
*** Completed Phase 1 route (0:00:00.1 411.2M) ***
Total length: 1.117e+05um, number of vias: 4846
M1(H) length: 0.000e+00um, number of vias: 2471
M2(V) length: 5.761e+04um, number of vias: 2375
M3(H) length: 5.406e+04um
*** Completed Phase 2 route (0:00:00.1 411.2M) ***
*** Finished all Phases (cpu=0:00:00.1 mem=411.2M) ***
Peak Memory Usage was 411.2M
*** Finished trialRoute (cpu=0:00:00.1 mem=411.2M) ***
<CMD> timeDesign -preCTS
*** Starting trialRoute (mem=411.2M) ***
There are 0 pin guide points passed to trialRoute.
Options: -handlePreroute -keepMarkedOptRoutes -noPinGuide
Nr of prerouted/Fixed nets = 16
routingBox: (1200 1500) (1498800 1780500)
coreBox: (350400 351000) (1150050 1431000)
Number of multi-gpin terms=0, multi-gpins=0, moved blk term=1/5
Phase 1a route (0:00:00.0 412.5M):
Est net length = 1.087e+05um = 5.494e+04H + 5.374e+04V
Usage: (20.1%H 30.0%V) = (6.738e+04um 1.191e+05um) = (5482 3969)
Obstruct: 2324 = 1088 (27.5%H) + 1236 (31.3%V)
Overflow: 24 = 0 (0.00% H) + 24 (0.87% V)
Phase 1b route (0:00:00.0 415.0M):
Usage: (20.1%H 30.0%V) = (6.720e+04um 1.191e+05um) = (5467 3969)
Overflow: 22 = 0 (0.00% H) + 22 (0.80% V)
Phase 1c route (0:00:00.0 415.0M):
Usage: (20.0%H 30.0%V) = (6.696e+04um 1.191e+05um) = (5447 3970)
Overflow: 19 = 0 (0.00% H) + 19 (0.70% V)
Phase 1d route (0:00:00.0 415.0M):
Usage: (20.0%H 30.0%V) = (6.701e+04um 1.192e+05um) = (5451 3974)
Overflow: 15 = 0 (0.00% H) + 15 (0.55% V)
Phase 1e route (0:00:00.0 415.6M):
Usage: (20.0%H 30.0%V) = (6.699e+04um 1.193e+05um) = (5450 3975)
Overflow: 14 = 0 (0.00% H) + 14 (0.52% V)
Phase 1f route (0:00:00.0 415.6M):
Usage: (20.0%H 30.0%V) = (6.717e+04um 1.194e+05um) = (5465 3980)
Overflow: 6 = 0 (0.00% H) + 6 (0.22% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-1: 0 0.00% 6 0.22%
--------------------------------------
0: 2 0.07% 189 6.96%
1: 96 3.35% 246 9.06%
2: 10 0.35% 369 13.59%
3: 101 3.53% 551 20.29%
4: 87 3.04% 494 18.19%
5: 172 6.01% 754 27.76%
6: 280 9.78% 30 1.10%
7: 538 18.78% 9 0.33%
8: 606 21.16% 7 0.26%
9: 441 15.40% 19 0.70%
10: 399 13.93% 42 1.55%
13: 1 0.03% 0 0.00%
14: 65 2.27% 0 0.00%
15: 66 2.30% 0 0.00%
Global route (cpu=0.1s real=0.0s 413.1M)
*** After '-updateRemainTrks' operation:
Usage: (20.0%H 30.0%V) = (6.717e+04um 1.194e+05um) = (5465 3980)
Overflow: 6 = 0 (0.00% H) + 6 (0.22% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-1: 0 0.00% 6 0.22%
--------------------------------------
0: 2 0.07% 189 6.96%
1: 96 3.35% 246 9.06%
2: 10 0.35% 369 13.59%
3: 101 3.53% 551 20.29%
4: 87 3.04% 494 18.19%
5: 172 6.01% 754 27.76%
6: 280 9.78% 30 1.10%
7: 538 18.78% 9 0.33%
8: 606 21.16% 7 0.26%
9: 441 15.40% 19 0.70%
10: 399 13.93% 42 1.55%
13: 1 0.03% 0 0.00%
14: 65 2.27% 0 0.00%
15: 66 2.30% 0 0.00%
*** Completed Phase 1 route (0:00:00.1 411.2M) ***
Total length: 1.117e+05um, number of vias: 4846
M1(H) length: 0.000e+00um, number of vias: 2471
M2(V) length: 5.761e+04um, number of vias: 2375
M3(H) length: 5.406e+04um
*** Completed Phase 2 route (0:00:00.1 411.2M) ***
*** Finished all Phases (cpu=0:00:00.1 mem=411.2M) ***
Peak Memory Usage was 411.2M
*** Finished trialRoute (cpu=0:00:00.1 mem=411.2M) ***
Extraction called for design 'lab7_layout_design' of instances=801 and nets=790 using extraction engine 'preRoute' .
**WARN: (ENCEXT-3530): Use of command 'setDesignMode -process <process_node>' prior to extraction is recommended for maximum accuracy and optimal automatic threshold setting.
Default RC Extraction called for design lab7_layout_design.
**WARN: (ENCEXT-6166): Using capacitance table file without EXTENDED section is not recommended and will result in lower accuracy for clock nets in preRoute extraction and for all nets when using postRoute extraction -effortLevel low. Regeneration of full capacitance table is recommended.
RCMode: Default
Capacitance Scaling Factor : 1.00000
Resistance Scaling Factor : 1.00000
Clock Cap. Scaling Factor : 1.00000
Clock Res Scaling Factor : 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Default RC Extraction DONE (CPU Time: 0:00:00.0 Real Time: 0:00:00.0 MEM: 411.191M)
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| 95.007 | 95.007 | 95.345 | 97.220 | N/A | N/A |
| TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| Violating Paths:| 0 | 0 | 0 | 0 | N/A | N/A |
| All Paths:| 210 | 135 | 151 | 4 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 38.722%
Routing Overflow: 0.00% H and 0.22% V
------------------------------------------------------------
Reported timing to dir ./timingReports
Total CPU time: 0.48 sec
Total Real time: 0.0 sec
Total Memory Usage: 418.832031 Mbytes
<CMD> setOptMode -yieldEffort none