From 1af05363d6353d7edd0d00e37ae0eb70f54b4b64 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 5 Feb 2024 14:22:33 +0000 Subject: [PATCH] [X86] getShuffleComment - use MI description to determine AVX512 masked predicates instead of src index offsets. --- llvm/lib/Target/X86/X86MCInstLower.cpp | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp index 31779f62547a6d..aa060de3bfefdc 100644 --- a/llvm/lib/Target/X86/X86MCInstLower.cpp +++ b/llvm/lib/Target/X86/X86MCInstLower.cpp @@ -1448,16 +1448,11 @@ static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, // Handle AVX512 MASK/MASXZ write mask comments. // MASK: zmmX {%kY} // MASKZ: zmmX {%kY} {z} - if (SrcOp1Idx > 1) { - assert((SrcOp1Idx == 2 || SrcOp1Idx == 3) && "Unexpected writemask"); - + if (X86II::isKMasked(MI->getDesc().TSFlags)) { const MachineOperand &WriteMaskOp = MI->getOperand(SrcOp1Idx - 1); - if (WriteMaskOp.isReg()) { - CS << " {%" << GetRegisterName(WriteMaskOp.getReg()) << "}"; - - if (SrcOp1Idx == 2) { - CS << " {z}"; - } + CS << " {%" << GetRegisterName(WriteMaskOp.getReg()) << "}"; + if (!X86II::isKMergeMasked(MI->getDesc().TSFlags)) { + CS << " {z}"; } }