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I have modified the Pico RISC-V core with crypto algorithms and want to get updated Fmax. Is there any way to calculate the latency introduced without running on FPGA using any example or test in simulation?
The text was updated successfully, but these errors were encountered:
I have modified the Pico RISC-V core with crypto algorithms and want to get updated Fmax. Is there any way to calculate the latency introduced without running on FPGA using any example or test in simulation?
The text was updated successfully, but these errors were encountered: