From 4c1c8cf504392b624a88304ca5ebc1965a038e7e Mon Sep 17 00:00:00 2001 From: deepesh2017 Date: Sun, 22 Sep 2024 13:07:21 -0700 Subject: [PATCH] Update tables.rst --- .../qdma_debug_flow/ports/tables.rst | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/pciedebug/source/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/qdma_debug_flow/ports/tables.rst b/pciedebug/source/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/qdma_debug_flow/ports/tables.rst index 37fe56f..66c6037 100644 --- a/pciedebug/source/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/qdma_debug_flow/ports/tables.rst +++ b/pciedebug/source/docs/QDMA_Subsystem_for_PCIExpress_IP_Driver/qdma_debug_flow/ports/tables.rst @@ -18,7 +18,10 @@ AXI4 Memory Mapped Master Bridge Read Address Interface Port Descriptions .. note:: - See the latest version of PG302 for updates + The table above is sourced from PG302. Refer to the links below for the relevant IP table. + PG302: https://docs.amd.com/r/en-US/pg302-qdma/QDMA-Global-Ports + PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/QDMA-Global-Ports?tocId=OZuHNoSk7b_ljTFaCFeXow + PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/QDMA-Global-Ports .. _axi4_memory_mapped_master_bridge_read_interface_port_descriptions: