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a/pciedebug/build/html/_sources/docs/Versal_ACAP_CPM_Mode_for_PCI_Express/versal_acap_cpm_example_designs.rst.txt b/pciedebug/build/html/_sources/docs/Versal_ACAP_CPM_Mode_for_PCI_Express/versal_acap_cpm_example_designs.rst.txt index ae9a19d..9dada3c 100644 --- a/pciedebug/build/html/_sources/docs/Versal_ACAP_CPM_Mode_for_PCI_Express/versal_acap_cpm_example_designs.rst.txt +++ b/pciedebug/build/html/_sources/docs/Versal_ACAP_CPM_Mode_for_PCI_Express/versal_acap_cpm_example_designs.rst.txt @@ -3,28 +3,42 @@ Versal ACAP CPM Example Designs =============================== -* Versal ACAP CPM5 QDMA Simulation Example Design +* Versal Adaptive SoC CPM5 QDMA Simulation Example Design - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm5_qdma -* Versal ACAP CPM4 QDMA Simulation Example Design +* Versal Adaptive SoC CPM4 QDMA Simulation Example Design - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm4_qdma -* Veral ACAP CPM5 BMD Simulation Example Design +* Versal Adaptive SoC CPM5 BMD Simulation Example Design - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm5_bmd -* Veral ACAP CPM4 BMD Simulation Example Design +* Versal Adaptive SoC CPM4 BMD Simulation Example Design - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm4_bmd -* Versal ACAP CPM - Using PCIe Link for Debug - - https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM_PCIe_Debug -* Veral ACAP Tandem PCIe Example Design - - https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM_Tandem_PCIe -* Versal ACAP CPM4/CPM5 AXI Bridge Root Complex Example Design +* Versal Adaptive SoC CPM - Using PCIe Link for Debug + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIe_Debug +* Versal Adaptive SoC CPM Tandem PCIe Example Design + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_Tandem_PCIe +* Versal Adaptive SoC CPM4/CPM5 AXI Bridge Root Complex Example Design - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_Bridge_RP_Design -* Versal ACAP CPM Gen4x8 QDMA Endpoint Example Design - - https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_ACAP_CPM_Gen4x8_QDMA_EP_Design -* Versal ACAP CPM5 PCIE PIO Example Design +* Versal Adaptive SoC CPM4 QDMA Gen4x8 MM/ST Example Design + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm4_qdma +* Versal Adaptive SoC CPM4 QDMA Gen4x8 Performance Example Design + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm4_qdma_perf +* Versal Adaptive SoC CPM5 QDMA Dual Ctrl Gen4x8 MM/ST Example Design + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_dual_ctrl +* Versal Adaptive SoC CPM5 QDMA Gen5x8 MM Only Performance Example Design + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_g5x8_mm_perf +* Versal Adaptive SoC CPM5 QDMA Gen4x8 MM/ST Example Design + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_mm_st +* Versal Adaptive SoC CPM5 QDMA Gen4x8 ST Only Performance Design + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_st_only +* Versal Adaptive SoC CPM5 PCIE PIO Example Design - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm5_pcie_pio -* Versal ACAP CPM4 PCIE PIO Example Design +* Versal Adaptive SoC CPM4 PCIE PIO Example Design - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm4_pcie_pio -* Versal ACAP CPM5 PCIE BMD EndPoint Example Design +* Versal Adaptive SoC CPM5 PCIE BMD EndPoint Example Design - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm5_bmd_ep -* Versal ACAP CPM4 PCIE BMD EndPoint Example Design - - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm4_bmd_ep +* Versal Adaptive SoC CPM4 PCIE BMD EndPoint Example Design + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm4_bmd_ep +* Versal Adaptive SoC CPM5 QDMA Dual Ctrl Gen5x8 Performance Example Design (Part Based) + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design_PartBased/cpm5_qdma_g5x8_dual_perf +* Versal Adaptive SoC CPM5 QDMA Gen5x8 ST Performance Example Design (Part Based) + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design_PartBased/cpm5_qdma_g5x8_st_perf diff --git a/pciedebug/build/html/docs/Versal_ACAP_CPM_Mode_for_PCI_Express/versal_acap_cpm_example_designs.html b/pciedebug/build/html/docs/Versal_ACAP_CPM_Mode_for_PCI_Express/versal_acap_cpm_example_designs.html index ee824af..4d55980 100644 --- a/pciedebug/build/html/docs/Versal_ACAP_CPM_Mode_for_PCI_Express/versal_acap_cpm_example_designs.html +++ b/pciedebug/build/html/docs/Versal_ACAP_CPM_Mode_for_PCI_Express/versal_acap_cpm_example_designs.html @@ -129,89 +129,138 @@

Versal ACAP CPM Example DesignsΒΆ

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47, 51, 66, 72], "thi": [4, 6, 8, 11, 14, 16, 18, 19, 32, 33, 38, 39, 41, 44, 45, 47, 51, 58, 59, 60, 66, 68, 72, 73, 77], "after": [4, 6, 8, 19, 32, 33, 47, 51, 58, 60, 72, 78], "being": [4, 9, 16, 19, 32, 33, 39, 41, 44, 47, 51, 57], "kept": 4, "minimum": [4, 19, 33], "durat": [4, 60], "least": 4, "equal": [4, 6, 19, 33], "complet": [4, 8, 16, 25, 44, 45, 47, 49, 51, 54, 55, 58, 59, 60, 78], "timeout": [4, 6, 47, 51, 57, 73, 78], "valu": [4, 9, 14, 16, 19, 33, 39, 41, 44, 47, 51, 58, 60, 73], "typic": [4, 11, 16, 32, 44], "50": 4, "m": [4, 41, 58], "clear": [4, 11, 19, 33, 44, 51], "ani": [4, 6, 8, 16, 19, 33, 45, 47, 51, 52, 57, 59, 60, 73], "pend": [4, 8, 11, 49], "transfer": [4, 10, 11, 14, 16, 44, 47, 49, 51, 52, 60], "mai": [4, 19, 33, 51], "current": [4, 45, 51, 72], "queu": 4, "data": [4, 6, 8, 11, 16, 19, 33, 44, 45, 49, 51, 52, 55, 59, 60, 68, 78], "path": [4, 19, 33], "To": [4, 10, 38, 39, 45, 51, 59, 66, 72], "type": [4, 6, 11, 19, 33, 55, 60], "command": [4, 9, 11, 14, 18, 32, 39, 41, 44, 47, 59, 72, 73], "tcl": [4, 11, 38, 45, 58, 72], "set_properti": [4, 11, 58, 72], "dict": [4, 11], "list": [4, 11, 19, 29, 32, 33, 47, 57], "config": [4, 6, 10, 11, 19, 24, 27, 32, 33, 58, 72], "soft_reset_en": 4, "true": [4, 11, 19, 33, 45, 58, 72], "get_ip": [4, 11, 72], "ip_nam": [4, 11], "request": [4, 6, 8, 11, 41, 44, 45, 51, 59, 60, 78], "length": [4, 6, 11, 45, 55], "greater": [4, 6, 41], "than": [4, 6, 11, 16, 32, 41, 44, 47, 51, 59, 60], "1": [4, 6, 7, 8, 10, 11, 14, 15, 19, 22, 25, 26, 29, 32, 33, 36, 39, 41, 44, 45, 47, 48, 49, 58, 59, 60, 64], "dword": [4, 6, 59], "size": [4, 6, 11, 16, 32, 44, 45, 47, 51, 60], "burst": [4, 6, 16, 44], "alwai": [4, 6, 11, 44, 47, 49, 51, 57], "width": [4, 6, 11, 16, 19, 33, 38, 44, 59, 60, 73], "bu": [4, 6, 9, 24, 27, 32, 39, 41, 44, 51, 59, 60, 73], "even": [4, 6, 11, 44, 47, 58], "receiv": [4, 6, 18, 41, 51, 60, 78], "shorter": [4, 6], "s_axi_wstrb": 4, "can": [4, 6, 8, 9, 11, 16, 19, 32, 33, 38, 39, 41, 44, 45, 47, 51, 58, 59, 60, 68, 72, 77], "us": [4, 5, 6, 9, 10, 11, 13, 14, 16, 19, 20, 24, 25, 26, 27, 29, 32, 33, 34, 38, 39, 40, 41, 44, 45, 46, 47, 51, 55, 59, 60, 62, 66, 67, 71, 72, 73, 74, 78], "facilit": 4, "align": [4, 44, 59], "address": [4, 6, 8, 10, 11, 25, 26, 32, 44, 51, 54, 59], "boundari": [4, 44, 45], "0": [4, 7, 10, 28, 29, 32, 39, 41, 44, 45, 47, 48, 54, 76], "begin": 4, "valid": [4, 39, 44, 60], "cycl": [4, 11, 18, 32, 60], "appropri": [4, 58], "calcul": 4, "offset": [4, 8, 10, 58], "given": [4, 11, 18, 47, 57], "howev": [4, 16, 41, 59], "identifi": [4, 10, 19, 33, 51, 58], "continu": [4, 16, 32, 51], "first": [4, 8, 19, 32, 33, 45, 47, 51, 57, 58, 78], "byte": [4, 10, 11, 16, 44, 45, 47, 59], "enabl": [4, 8, 11, 14, 16, 18, 19, 32, 33, 39, 41, 44, 47, 49, 51, 54, 55, 58, 59, 63, 66, 72, 73, 77], "last": [4, 11, 45, 54, 60], "The": [4, 6, 8, 9, 10, 11, 14, 16, 18, 19, 29, 32, 33, 38, 39, 41, 44, 45, 47, 51, 52, 58, 59, 60, 66, 68, 72, 73, 77], "core": [4, 14, 19, 24, 26, 27, 29, 33, 44, 58, 60, 69, 76], "conform": 4, "order": [4, 8, 32, 44, 47], "rule": [4, 8, 19, 33], "pci": [4, 7, 9, 15, 16, 18, 19, 22, 24, 25, 26, 27, 28, 29, 30, 32, 33, 36, 39, 41, 42, 48, 57, 58, 59, 63, 64, 66, 69, 72, 73, 76, 78], "sig": [4, 29], "specif": [4, 5, 9, 19, 33, 39, 44, 74, 78], "behavior": [4, 20, 34, 78], "ar": [4, 8, 9, 10, 11, 14, 16, 18, 19, 28, 32, 33, 39, 41, 44, 45, 47, 51, 54, 55, 57, 58, 59, 60, 66, 68, 72], "implement": [4, 11, 20, 29, 34, 44, 51, 78], "enforc": 4, "highli": 4, "parallel": 4, "bresp": [4, 8, 51], "remot": 4, "until": [4, 18, 58, 60], "memwr": 4, "tlp": [4, 6, 59, 60, 78], "transmiss": [4, 19, 33], "guarante": 4, "sent": [4, 11, 47, 51], "subsequ": 4, "tx": [4, 19, 33, 44, 57], "relax": [4, 32, 44], "within": [4, 10, 11, 16, 18, 19, 32, 33, 41, 58, 60], "header": 4, "permit": 4, "pass": [4, 29, 45], "previou": [4, 8, 19, 33, 72], "phase": [4, 19, 33, 51, 57, 66], "held": [4, 18], "have": [4, 8, 16, 19, 32, 33, 38, 41, 44, 45, 47, 51, 66], "ha": [4, 8, 9, 10, 11, 14, 18, 19, 32, 33, 39, 41, 44, 47, 51, 58, 59, 60], "been": [4, 6, 9, 11, 14, 19, 32, 33, 39, 45, 47, 58, 66], "attribut": [4, 59], "prior": [4, 8, 28, 51], "": [4, 6, 11, 15, 16, 19, 25, 26, 32, 33, 39, 41, 44, 45, 48, 51], "present": 4, "channel": [4, 10, 16, 19, 33, 72], "integr": [4, 14, 16, 18, 19, 22, 24, 25, 26, 27, 28, 32, 33, 36, 38, 44, 51, 57, 58, 59, 60, 63, 64, 66, 72, 76, 78], "block": [4, 11, 18, 19, 22, 24, 25, 26, 27, 28, 33, 36, 41, 45, 47, 51, 57, 58, 59, 60, 63, 64, 66, 72, 76, 77, 78], "express": [4, 7, 9, 15, 16, 18, 19, 22, 24, 25, 26, 27, 28, 29, 30, 33, 36, 38, 39, 42, 48, 57, 58, 59, 63, 64, 66, 69, 72, 76, 78], "detect": [4, 11, 14, 32, 41, 45, 47, 51, 59, 66, 68, 72, 78], "malform": 4, "configur": [4, 9, 11, 16, 18, 20, 24, 25, 27, 29, 34, 39, 44, 47, 49, 51, 57, 58, 59, 60, 66, 68, 73, 78], "result": [4, 6, 44, 51], "fatal": [4, 41, 45], "messag": [4, 25, 58], "upstream": [4, 59], "report": [4, 39, 41, 44, 45, 47, 48], "monitor": [4, 25, 45], "ensur": [4, 8, 11, 16, 18, 19, 32, 33, 41, 51, 57], "onli": [4, 6, 10, 11, 16, 18, 19, 33, 38, 41, 45, 47, 49, 51, 54, 59, 60, 72], "incr": 4, "increment": [4, 51], "other": [4, 8, 19, 33, 41, 44, 57], "treat": [4, 60], "condit": 4, "illeg": 4, "sib": 4, "In": [4, 6, 19, 24, 25, 27, 33, 38, 41, 44, 45, 47, 51, 59, 68, 72], "case": [4, 19, 26, 33, 38, 44, 45, 47, 51, 59], "slverr": 4, "beat": [4, 11, 60], "arbitrari": 4, "place": [4, 19, 32, 33, 58], "s_axi_rdata": 4, "respons": [4, 6, 10, 14, 47, 51, 55], "discard": 4, "normal": [4, 51], "depend": [4, 6, 8, 11, 44, 51, 60], "establish": [4, 6, 39], "maintain": [4, 51, 54, 58], "point": [4, 19, 33, 44, 45], "extern": [4, 68, 77], "lost": [4, 32, 51], "re": [4, 32, 58, 59, 66, 72], "return": [4, 6, 32, 66], "hot": [4, 18, 41], "goe": [4, 41, 51, 59, 66, 72], "down": [4, 14, 19, 32, 33, 41, 44, 47, 51], "space": [4, 10, 18, 19, 25, 32, 33, 39, 42, 51, 54, 59, 69, 73], "reconfigur": [4, 24, 27, 58], "yet": 4, "associ": [4, 41, 44, 45, 51], "start": [4, 41, 51, 58, 60, 66], "bar": [4, 8, 9, 16, 19, 32, 33, 39, 44, 55, 66], "support": [4, 7, 10, 11, 15, 16, 18, 19, 22, 24, 27, 30, 33, 36, 38, 39, 41, 42, 44, 45, 47, 48, 57, 59, 64, 66, 69, 72, 76], "filter": [4, 58], "forward": [4, 8], "translat": [4, 8, 9, 25, 39], "disabl": [4, 6, 9, 11, 16, 18, 19, 32, 33, 39, 41, 44, 51, 55, 59, 73], "custom": [4, 16, 19, 25, 33, 44, 45, 47, 58, 72], "design": [4, 9, 10, 11, 15, 16, 20, 22, 24, 25, 26, 27, 28, 29, 30, 32, 34, 36, 39, 42, 44, 47, 48, 51, 58, 59, 64, 66, 67, 72, 77, 78], "suit": [4, 28, 57], "rp": [4, 19, 33, 41], "applic": [4, 11, 16, 31, 32, 44, 47, 51, 58, 59, 60, 78], "without": [4, 6, 41], "default": [4, 6, 15, 19, 22, 25, 33, 36, 51, 59], "0x0000_0000": 4, "program": [4, 9, 24, 25, 27, 29, 32, 39, 41, 44, 45, 49, 51, 54, 58, 68], "separ": [4, 19, 33, 51, 58], "hit": [4, 47], "accord": [4, 19, 33], "outsid": [4, 47, 72], "rang": [4, 9, 39], "cannot": [4, 44, 58], "recommend": [4, 9, 39, 44, 51], "do": [4, 8, 14, 16, 19, 32, 33, 38, 39, 41, 45, 47, 58, 59, 66, 72], "set_finite_credit": 4, "fals": [4, 58, 72], "infinit": [4, 60], "credit": [4, 14, 16, 19, 25, 32, 33, 44, 45, 47, 49, 51, 54, 55, 60], "advertis": [4, 39], "complex": [4, 26, 29, 42, 71], "finit": 4, "requir": [4, 18, 19, 25, 32, 33, 39, 41, 44, 45, 47, 51, 58, 72], "most": [4, 19, 33], "obei": 4, "caution": [4, 44], "verifi": [4, 19, 25, 33, 49], "function": [4, 14, 39, 44, 45, 55, 59, 73], "output": [4, 14, 19, 24, 27, 33, 44, 47, 49, 58, 68, 73], "s_axi_arreadi": 4, "s_axi_rvalid": 4, "unrespons": 4, "met": [4, 24, 27], "older": 4, "axi_ctl_aclk": 4, "axi_ctl_aclk_out": 4, "puls": 4, "out": [4, 10, 19, 25, 32, 33, 45, 52, 68, 77], "activ": [4, 47, 58, 60], "low": [4, 44, 51], "main": [4, 16], "toggl": 4, "simul": [4, 19, 24, 25, 26, 27, 29, 33, 44, 71, 78], "run": [4, 9, 19, 25, 29, 32, 33, 39, 41, 44, 47, 51, 59, 66, 72], "featur": [4, 14, 19, 22, 25, 26, 33, 36, 45, 51, 55, 58, 59, 64, 66, 72], "captur": [4, 10, 19, 33, 59, 66], "waveform": 4, "access": [4, 6, 14, 39, 44, 58], "abov": [4, 11, 19, 41, 51, 59, 60, 66], "taken": [4, 11, 19, 33, 44, 51, 60], "qdma": [4, 15, 25, 26, 29, 38, 45, 47, 48, 51, 52, 57, 60, 71, 77], "product": [4, 7, 11, 16, 18, 51, 59, 60, 64, 69, 76], "guid": [4, 11, 15, 16, 18, 19, 22, 25, 26, 33, 36, 39, 42, 48, 51, 59, 60, 64, 66, 69, 72, 76], "pg195": [4, 10, 11, 12, 15], "document": [4, 5, 11, 13, 19, 20, 24, 27, 30, 33, 34, 40, 46, 47, 51, 59, 60, 62, 66, 67, 72, 74, 78], "gotcha": [5, 13, 46, 49, 62, 74, 78], "gener": [5, 11, 13, 14, 20, 25, 26, 29, 34, 40, 42, 46, 48, 49, 51, 62, 67, 74], "checklist": [5, 13, 20, 34, 40, 46, 49, 62, 67, 74, 78], "tip": [5, 13, 31, 40, 46, 49, 62, 67, 78], "question": [5, 13, 20, 34, 40, 46, 49, 62, 67, 78], "collater": [5, 13, 20, 34, 40, 46, 62, 67, 74, 78], "between": [6, 10, 19, 33], "d0": 6, "uniniti": 6, "state": [6, 8, 19, 32, 33, 41, 51, 59, 63, 66, 72, 73], "mean": [6, 32, 47], "physic": [6, 55, 58], "hasn": [6, 45], "t": [6, 19, 33, 41, 45, 58], "exchang": [6, 32], "initfc": 6, "enumer": [6, 9, 14, 19, 33, 39, 66, 78], "thu": [6, 51, 58, 60], "get": [6, 14, 16, 44, 47, 49, 58, 63, 66], "through": [6, 8, 10, 24, 25, 27, 32, 41, 44, 45, 51, 54, 59], "essenti": 6, "user_reset": 6, "releas": [6, 7, 15, 31, 39, 42, 48, 64, 76, 78], "layer": 6, "should": [6, 9, 10, 16, 19, 32, 33, 39, 41, 44, 45, 47, 51, 54, 58, 59, 60], "therefor": 6, "indic": [6, 11, 14, 18, 19, 32, 33, 51, 73], "send": [6, 16, 45, 47, 51, 57], "over": [6, 11, 60], "usabl": 6, "host": [6, 11, 16, 19, 25, 32, 33, 44, 47, 51, 54, 59, 66, 68, 72], "testbench": 6, "hang": [6, 14, 44, 47], "memori": [6, 10, 15, 16, 19, 24, 25, 26, 27, 32, 33, 39, 44, 47, 49, 51, 59, 66, 73], "whether": [6, 19, 32, 33, 38], "non": [6, 9, 19, 33, 39, 41, 58, 60], "exist": [6, 19, 32, 33, 72], "These": [6, 47, 58], "attempt": [6, 19, 33], "would": [6, 16, 41, 44], "readi": [6, 60], "mechan": [6, 11, 25], "unlik": [6, 39], "A": [6, 11, 19, 25, 33, 42, 51, 57, 69], "possibl": [6, 10, 16, 19, 33, 38, 44, 51, 72], "workaround": 6, "firewal": 6, "outstand": [6, 51, 60], "number": [6, 9, 16, 28, 39, 44, 45, 47, 51, 55, 60], "8": [6, 10, 25, 26, 41], "c_s_axi_num_read": 6, "one": [6, 11, 18, 32, 57], "instead": [6, 16, 19, 32, 33, 51, 59, 72], "narow": 6, "event": [6, 44], "though": [6, 47], "limit": [6, 16, 41, 72], "masteraxi": 6, "descript": [7, 15, 18, 19, 22, 33, 36, 42, 48, 49, 57, 59, 64, 69, 76], "url": [7, 15, 18, 22, 36, 42, 48, 57, 64, 69, 76], "v3": [7, 48], "http": [7, 15, 16, 18, 19, 22, 24, 27, 29, 30, 33, 36, 38, 39, 41, 42, 44, 45, 47, 48, 57, 59, 64, 66, 69, 71, 72, 76], "www": [7, 15, 18, 19, 22, 24, 27, 29, 30, 33, 36, 38, 39, 41, 42, 44, 48, 57, 59, 64, 66, 69, 72, 76], "xilinx": [7, 9, 15, 16, 18, 19, 22, 24, 25, 26, 27, 28, 29, 30, 33, 36, 38, 39, 41, 42, 44, 45, 47, 48, 51, 57, 59, 64, 66, 69, 71, 72, 76, 78], "com": [7, 15, 16, 18, 19, 22, 24, 27, 29, 30, 33, 36, 38, 39, 41, 42, 44, 45, 48, 57, 59, 64, 66, 69, 71, 72, 76], "ip_document": [7, 15, 64, 69, 76], "axi_pcie3": 7, "v3_0": 7, "pdf": [7, 15, 19, 22, 24, 27, 30, 33, 36, 57, 64, 69, 76], "xdma": [7, 9, 10, 11, 14, 15, 25, 26, 29, 39, 48, 52], "jtag": [7, 15, 19, 26, 32, 33], "answer": [7, 9, 15, 16, 18, 19, 22, 28, 31, 33, 34, 36, 38, 39, 41, 42, 44, 48, 59, 64, 66, 72, 76, 78], "71322": [7, 15], "html": [7, 15, 18, 19, 22, 29, 33, 36, 38, 39, 41, 42, 44, 47, 48, 59, 64, 66, 69, 72, 76], "note": [7, 15, 31, 39, 41, 42, 44, 47, 48, 64, 76, 78], "known": [7, 15, 19, 33, 41, 48, 64, 76], "2013": 7, "newer": [7, 15, 48], "tool": [7, 15, 48, 58], "54646": [7, 28], "gen": 7, "3": [7, 10, 15, 19, 25, 26, 33, 41, 45, 49, 57, 64, 66], "intellectu": 7, "properti": [7, 68, 72], "axi_pcie_gen3": 7, "trasfer": 8, "probe": [8, 14, 19, 33, 41], "m_axi": 8, "s_axi": 8, "direct": [8, 19, 32, 33, 44, 45, 47, 51, 54, 68, 72], "flow": [8, 9, 10, 25, 38, 39, 41, 46, 47, 72, 78], "trigger": [8, 25, 55, 73], "catch": 8, "made": [8, 29], "show": [8, 19, 33, 41, 45, 52, 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27, 29, 31, 34, 40, 46, 62, 67, 71, 74], "k": [0, 44], "map": [0, 10, 15, 25, 26, 32, 44, 45, 47, 49, 51, 54], "see": [1, 4, 8, 12, 14, 16, 19, 29, 32, 33, 38, 41, 44, 47, 50, 51, 54, 59, 61, 66, 72, 73], "latest": [1, 3, 4, 9, 11, 12, 16, 18, 39, 41, 50, 51, 59, 60, 61], "version": [1, 3, 4, 7, 9, 11, 12, 15, 16, 19, 28, 33, 39, 41, 45, 47, 48, 50, 51, 57, 59, 60, 61], "pg194": [1, 3, 7], "updat": [1, 3, 4, 11, 12, 44, 47, 49, 50, 51, 58, 59, 60, 61, 72], "global": [2, 49], "signal": [2, 3, 8, 10, 16, 18, 19, 25, 32, 33, 45, 47, 49, 57, 59, 60, 73], "axi": [2, 3, 4, 6, 7, 8, 9, 10, 15, 16, 25, 26, 28, 29, 32, 39, 42, 44, 47, 48, 49, 51, 55, 71], "slave": [2, 3, 4, 6, 10, 25, 51, 55], "interfac": [2, 3, 4, 6, 8, 9, 10, 11, 16, 19, 22, 25, 33, 36, 39, 44, 45, 47, 49, 51, 55, 57, 59, 60, 64, 66, 72, 77], "master": [2, 3, 4, 7, 10, 15, 16, 24, 26, 27, 28, 41, 47, 48, 51, 55, 59, 73], "axi4": [2, 3, 4, 10, 11, 24, 27, 47, 49, 51], "lite": [2, 3, 4, 8, 9, 10, 24, 27, 39, 55], "control": [2, 3, 4, 8, 9, 10, 11, 18, 25, 32, 39, 47, 48, 51], "bridg": [2, 3, 4, 6, 7, 8, 9, 15, 24, 25, 27, 28, 32, 39, 44, 48, 51, 55, 71], "gen3": [2, 3, 4, 7, 15, 16, 19, 22, 24, 25, 26, 27, 28, 29, 33, 36, 57, 64, 66], "msi": [2, 3, 11, 16, 18, 25, 41, 55, 66], "x": [2, 3, 11, 16, 18, 25, 41, 55, 66], "dma_bridg": [2, 3], "subsystem": [2, 3, 4, 7, 15, 24, 25, 26, 27, 28, 29, 42, 44, 48, 58], "mode": [2, 3, 4, 9, 16, 19, 24, 25, 27, 28, 33, 39, 41, 44, 45, 47, 49, 51, 55, 57, 58, 59, 66, 69, 78], "interrupt": [2, 3, 4, 11, 16, 25, 26, 41, 44, 47, 51, 54, 55, 64, 78], "decod": [2, 3, 4, 6, 47], "regist": [2, 3, 4, 7, 8, 9, 10, 11, 14, 15, 18, 19, 25, 26, 32, 33, 39, 41, 44, 45, 47, 49, 51, 59, 66, 69, 73], "phy": [2, 3, 28, 59, 72], "status_control": [2, 3], "root": [2, 3, 4, 9, 19, 26, 29, 33, 39, 41, 42, 59, 69, 71], "port": [2, 3, 4, 9, 10, 19, 26, 33, 39, 41, 42, 44, 45, 47, 49, 51, 59, 63, 69, 77], "error": [2, 3, 4, 6, 16, 19, 25, 33, 41, 44, 45, 47, 49, 51, 52, 55, 57, 58, 59, 60, 73], "fifo": [2, 3, 44, 60], "read": [2, 3, 4, 6, 7, 8, 9, 10, 11, 14, 15, 25, 26, 39, 41, 44, 49, 51, 55, 57, 59, 66, 78], "clock": [2, 3, 4, 18, 20, 34, 44, 55, 57, 58, 60, 66, 72, 78], "diagram": [2, 3, 44, 59, 66, 72], "ultrascal": [2, 3, 9, 18, 19, 22, 24, 25, 26, 27, 28, 29, 30, 33, 36, 39, 41, 42, 48, 58, 59, 63, 64, 66, 72], "devic": [2, 3, 4, 9, 10, 16, 19, 22, 25, 26, 29, 30, 33, 36, 38, 39, 41, 45, 48, 58, 59, 64, 66, 68, 72, 78], "endpoint": [2, 3, 4, 9, 16, 19, 24, 25, 26, 27, 28, 32, 33, 39, 41, 42, 57, 59, 71, 78], "system": [2, 3, 6, 9, 16, 20, 24, 26, 27, 30, 32, 34, 39, 41, 42, 44, 47, 48, 78], "reset": [2, 3, 4, 9, 19, 32, 33, 39, 41, 51, 57, 58, 72], "connect": [2, 3, 4, 16, 19, 24, 27, 29, 30, 32, 33, 39, 41, 47, 57, 58, 72], "confirm": [3, 9, 19, 33, 39, 41, 44, 47, 66, 72], "architectur": [3, 19, 25, 28, 30, 33, 58, 69], "i": [3, 4, 6, 8, 9, 10, 11, 14, 16, 18, 19, 32, 33, 39, 41, 44, 45, 47, 49, 51, 54, 55, 57, 58, 59, 60, 63, 66, 68, 72, 73, 78], "correct": [3, 4, 9, 19, 25, 33, 39, 44, 45, 51, 57, 58], "rootport": [3, 41], "check": [3, 6, 8, 10, 14, 16, 18, 19, 32, 33, 39, 41, 44, 45, 47, 49, 55, 57, 59, 66, 72, 73, 78], "statu": [3, 10, 14, 16, 19, 25, 33, 41, 44, 45, 47, 49, 51, 54, 55, 59, 66, 78], "If": [3, 4, 6, 8, 14, 16, 18, 19, 32, 33, 38, 39, 41, 44, 45, 47, 51, 54, 57, 58, 59, 66, 72, 73], "issu": [3, 4, 5, 7, 10, 13, 15, 16, 22, 25, 26, 34, 36, 40, 44, 46, 48, 49, 51, 52, 59, 62, 64, 66, 67, 72, 74, 76, 78], "relat": [3, 6, 10, 14, 19, 25, 33, 59, 66], "incom": [3, 51], "outgo": 3, "packet": [3, 4, 6, 8, 11, 19, 22, 25, 26, 33, 36, 44, 45, 47, 51, 55, 60, 64, 66], "from": [3, 4, 6, 9, 11, 16, 19, 29, 32, 33, 39, 41, 44, 45, 47, 48, 51, 52, 59, 60, 72, 78], "user": [3, 4, 9, 11, 16, 19, 25, 32, 33, 38, 39, 44, 45, 47, 51, 57, 58, 60, 66, 72], "logic": [3, 4, 16, 44, 45, 47, 51, 57, 58], "follow": [3, 4, 8, 9, 10, 11, 14, 19, 32, 33, 38, 39, 41, 44, 47, 59, 63, 66, 68, 72, 73], "vivado": [3, 4, 7, 10, 15, 16, 19, 22, 24, 25, 26, 27, 28, 29, 33, 36, 45, 47, 48, 57, 59, 64, 66, 72], "ila": [3, 10, 19, 25, 26, 32, 33, 47, 59, 66, 73], "an": [3, 4, 9, 11, 14, 16, 19, 26, 29, 32, 33, 38, 39, 41, 44, 45, 51, 52, 57, 58, 59, 60, 66], "write": [3, 4, 8, 10, 14, 25, 32, 44, 47, 49, 51, 55, 59, 66], "For": [3, 4, 6, 8, 9, 10, 11, 16, 19, 28, 33, 38, 39, 41, 44, 47, 51, 57, 58, 59, 66, 72, 73], "pleas": [3, 4, 11, 14, 19, 33, 51, 59, 60], "refer": [3, 4, 10, 11, 19, 24, 27, 30, 33, 45, 51, 59, 60, 66, 69], "new": [3, 4, 11, 25, 38, 49, 51, 58, 59, 60, 72, 77], "more": [3, 4, 11, 16, 32, 38, 44, 47, 51, 59, 60, 72, 73], "detail": [3, 4, 9, 16, 19, 33, 38, 39, 49, 51, 59, 60, 66, 73], "referenc": [3, 59], "assert": [4, 6, 11, 18, 44, 45, 47, 51, 59, 60], "bit": [4, 8, 10, 11, 18, 32, 39, 41, 45, 47, 49, 51, 54, 59, 60, 73], "doe": [4, 16, 19, 32, 33, 41, 45, 47, 51, 59, 72], "caus": [4, 19, 32, 33, 44, 51, 58], "line": [4, 18, 19, 32, 33, 44, 51], "unless": 4, "correspond": [4, 8, 19, 33, 47, 57, 60], "mask": [4, 19, 33, 47, 55], "also": [4, 16, 18, 44, 45, 51, 54, 58, 59, 60, 66], "set": [4, 6, 8, 9, 14, 19, 32, 33, 39, 41, 44, 45, 47, 51, 55, 57, 63, 68, 72], "avail": [4, 14, 16, 19, 33, 41, 44, 45, 47, 51, 54, 72], "dma": [4, 10, 14, 15, 16, 24, 25, 26, 27, 28, 29, 41, 44, 45, 47, 48, 49, 51, 54, 55, 57, 58, 78], "option": [4, 9, 16, 19, 33, 39, 55, 59, 60, 77], "dma_bridge_resetn": 4, "input": [4, 19, 24, 27, 32, 33, 44, 45, 49, 51, 57], "pin": [4, 9, 11, 18, 19, 32, 33, 39, 58, 72], "which": [4, 6, 14, 16, 19, 33, 41, 44, 45, 47, 51, 59], "allow": [4, 19, 33, 51, 60], "you": [4, 8, 11, 14, 16, 18, 19, 32, 33, 38, 39, 44, 47, 51, 60, 73], "all": [4, 11, 19, 28, 32, 33, 44, 45, 47, 49, 51, 55, 57, 58, 59], "intern": [4, 7, 8, 10, 15, 26, 45, 47, 49, 51, 55], "engin": [4, 44, 47, 49, 51, 54], "well": [4, 19, 33, 41, 44, 47, 51, 54, 66, 72], "peripher": [4, 6], "driven": [4, 32, 57], "axi_aresetn": [4, 6, 47], "axi_ctl_aresetn": 4, "when": [4, 6, 9, 11, 14, 32, 39, 41, 44, 45, 47, 51, 55, 57, 58, 60, 73, 78], "paramet": [4, 8, 10, 19, 33, 44, 49], "need": [4, 11, 18, 41, 44, 45, 47, 51, 73], "dure": [4, 11, 32, 39, 41, 51, 58, 60], "initi": [4, 9, 10, 14, 16, 24, 27, 39, 41, 49, 54, 58], "link": [4, 5, 6, 13, 14, 16, 24, 25, 26, 27, 32, 39, 40, 41, 44, 45, 46, 47, 51, 59, 60, 62, 66, 67, 71, 72, 73, 74, 78], "up": [4, 6, 8, 9, 14, 16, 32, 38, 39, 41, 45, 51, 59, 66], "oper": [4, 9, 39, 41, 44, 51], "becaus": [4, 6, 8, 44, 45, 51], "done": [4, 6, 9, 11, 18, 32, 39, 41, 45, 47, 51, 58, 68, 72], "automat": [4, 72], "ip": [4, 6, 7, 9, 11, 14, 15, 16, 18, 19, 24, 25, 26, 27, 29, 33, 39, 44, 45, 47, 48, 49, 57, 58, 59, 63, 66, 72, 77, 78], "must": [4, 8, 11, 32, 39, 44, 47, 51, 58, 59, 60], "termin": [4, 11, 19, 33], "transact": [4, 6, 8, 25, 51, 57, 59], "befor": [4, 6, 8, 14, 28, 39, 41, 44, 45, 47, 51, 66, 72], "thi": [4, 6, 8, 11, 14, 16, 18, 19, 32, 33, 38, 39, 41, 44, 45, 47, 51, 58, 59, 60, 66, 68, 72, 73, 77], "after": [4, 6, 8, 19, 32, 33, 47, 51, 58, 60, 72, 78], "being": [4, 9, 16, 19, 32, 33, 39, 41, 44, 47, 51, 57], "kept": 4, "minimum": [4, 19, 33], "durat": [4, 60], "least": 4, "equal": [4, 6, 19, 33], "complet": [4, 8, 16, 25, 44, 45, 47, 49, 51, 54, 55, 58, 59, 60, 78], "timeout": [4, 6, 47, 51, 57, 73, 78], "valu": [4, 9, 14, 16, 19, 33, 39, 41, 44, 47, 51, 58, 60, 73], "typic": [4, 11, 16, 32, 44], "50": 4, "m": [4, 41, 58], "clear": [4, 11, 19, 33, 44, 51], "ani": [4, 6, 8, 16, 19, 33, 45, 47, 51, 52, 57, 59, 60, 73], "pend": [4, 8, 11, 49], "transfer": [4, 10, 11, 14, 16, 44, 47, 49, 51, 52, 60], "mai": [4, 19, 33, 51], "current": [4, 45, 51, 72], "queu": 4, "data": [4, 6, 8, 11, 16, 19, 33, 44, 45, 49, 51, 52, 55, 59, 60, 68, 78], "path": [4, 19, 33], "To": [4, 10, 38, 39, 45, 51, 59, 66, 72], "type": [4, 6, 11, 19, 33, 55, 60], "command": [4, 9, 11, 14, 18, 32, 39, 41, 44, 47, 59, 72, 73], "tcl": [4, 11, 38, 45, 58, 72], "set_properti": [4, 11, 58, 72], "dict": [4, 11], "list": [4, 11, 19, 29, 32, 33, 47, 57], "config": [4, 6, 10, 11, 19, 24, 27, 32, 33, 58, 72], "soft_reset_en": 4, "true": [4, 11, 19, 33, 45, 58, 72], "get_ip": [4, 11, 72], "ip_nam": [4, 11], "request": [4, 6, 8, 11, 41, 44, 45, 51, 59, 60, 78], "length": [4, 6, 11, 45, 55], "greater": [4, 6, 41], "than": [4, 6, 11, 16, 32, 41, 44, 47, 51, 59, 60], "1": [4, 6, 7, 8, 10, 11, 14, 15, 19, 22, 25, 26, 29, 32, 33, 36, 39, 41, 44, 45, 47, 48, 49, 58, 59, 60, 64], "dword": [4, 6, 59], "size": [4, 6, 11, 16, 32, 44, 45, 47, 51, 60], "burst": [4, 6, 16, 44], "alwai": [4, 6, 11, 44, 47, 49, 51, 57], "width": [4, 6, 11, 16, 19, 33, 38, 44, 59, 60, 73], "bu": [4, 6, 9, 24, 27, 32, 39, 41, 44, 51, 59, 60, 73], "even": [4, 6, 11, 44, 47, 58], "receiv": [4, 6, 18, 41, 51, 60, 78], "shorter": [4, 6], "s_axi_wstrb": 4, "can": [4, 6, 8, 9, 11, 16, 19, 32, 33, 38, 39, 41, 44, 45, 47, 51, 58, 59, 60, 68, 72, 77], "us": [4, 5, 6, 9, 10, 11, 13, 14, 16, 19, 20, 24, 25, 26, 27, 29, 32, 33, 34, 38, 39, 40, 41, 44, 45, 46, 47, 51, 55, 59, 60, 62, 66, 67, 71, 72, 73, 74, 78], "facilit": 4, "align": [4, 44, 59], "address": [4, 6, 8, 10, 11, 25, 26, 32, 44, 51, 54, 59], "boundari": [4, 44, 45], "0": [4, 7, 10, 28, 29, 32, 39, 41, 44, 45, 47, 48, 54, 76], "begin": 4, "valid": [4, 39, 44, 60], "cycl": [4, 11, 18, 32, 60], "appropri": [4, 58], "calcul": 4, "offset": [4, 8, 10, 58], "given": [4, 11, 18, 47, 57], "howev": [4, 16, 41, 59], "identifi": [4, 10, 19, 33, 51, 58], "continu": [4, 16, 32, 51], "first": [4, 8, 19, 32, 33, 45, 47, 51, 57, 58, 78], "byte": [4, 10, 11, 16, 44, 45, 47, 59], "enabl": [4, 8, 11, 14, 16, 18, 19, 32, 33, 39, 41, 44, 47, 49, 51, 54, 55, 58, 59, 63, 66, 72, 73, 77], "last": [4, 11, 45, 54, 60], "The": [4, 6, 8, 9, 10, 11, 14, 16, 18, 19, 29, 32, 33, 38, 39, 41, 44, 45, 47, 51, 52, 58, 59, 60, 66, 68, 72, 73, 77], "core": [4, 14, 19, 24, 26, 27, 29, 33, 44, 58, 60, 69, 76], "conform": 4, "order": [4, 8, 32, 44, 47], "rule": [4, 8, 19, 33], "pci": [4, 7, 9, 15, 16, 18, 19, 22, 24, 25, 26, 27, 28, 29, 30, 32, 33, 36, 39, 41, 42, 48, 57, 58, 59, 63, 64, 66, 69, 72, 73, 76, 78], "sig": [4, 29], "specif": [4, 5, 9, 19, 33, 39, 44, 74, 78], "behavior": [4, 20, 34, 78], "ar": [4, 8, 9, 10, 11, 14, 16, 18, 19, 28, 32, 33, 39, 41, 44, 45, 47, 51, 54, 55, 57, 58, 59, 60, 66, 68, 72], "implement": [4, 11, 20, 29, 34, 44, 51, 78], "enforc": 4, "highli": 4, "parallel": 4, "bresp": [4, 8, 51], "remot": 4, "until": [4, 18, 58, 60], "memwr": 4, "tlp": [4, 6, 59, 60, 78], "transmiss": [4, 19, 33], "guarante": 4, "sent": [4, 11, 47, 51], "subsequ": 4, "tx": [4, 19, 33, 44, 57], "relax": [4, 32, 44], "within": [4, 10, 11, 16, 18, 19, 32, 33, 41, 58, 60], "header": 4, "permit": 4, "pass": [4, 29, 45], "previou": [4, 8, 19, 33, 72], "phase": [4, 19, 33, 51, 57, 66], "held": [4, 18], "have": [4, 8, 16, 19, 32, 33, 38, 41, 44, 45, 47, 51, 66], "ha": [4, 8, 9, 10, 11, 14, 18, 19, 32, 33, 39, 41, 44, 47, 51, 58, 59, 60], "been": [4, 6, 9, 11, 14, 19, 32, 33, 39, 45, 47, 58, 66], "attribut": [4, 59], "prior": [4, 8, 28, 51], "": [4, 6, 11, 15, 16, 19, 25, 26, 32, 33, 39, 41, 44, 45, 48, 51], "present": 4, "channel": [4, 10, 16, 19, 33, 72], "integr": [4, 14, 16, 18, 19, 22, 24, 25, 26, 27, 28, 32, 33, 36, 38, 44, 51, 57, 58, 59, 60, 63, 64, 66, 72, 76, 78], "block": [4, 11, 18, 19, 22, 24, 25, 26, 27, 28, 33, 36, 41, 45, 47, 51, 57, 58, 59, 60, 63, 64, 66, 72, 76, 77, 78], "express": [4, 7, 9, 15, 16, 18, 19, 22, 24, 25, 26, 27, 28, 29, 30, 33, 36, 38, 39, 42, 48, 57, 58, 59, 63, 64, 66, 69, 72, 76, 78], "detect": [4, 11, 14, 32, 41, 45, 47, 51, 59, 66, 68, 72, 78], "malform": 4, "configur": [4, 9, 11, 16, 18, 20, 24, 25, 27, 29, 34, 39, 44, 47, 49, 51, 57, 58, 59, 60, 66, 68, 73, 78], "result": [4, 6, 44, 51], "fatal": [4, 41, 45], "messag": [4, 25, 58], "upstream": [4, 59], "report": [4, 39, 41, 44, 45, 47, 48], "monitor": [4, 25, 45], "ensur": [4, 8, 11, 16, 18, 19, 32, 33, 41, 51, 57], "onli": [4, 6, 10, 11, 16, 18, 19, 33, 38, 41, 45, 47, 49, 51, 54, 59, 60, 71, 72], "incr": 4, "increment": [4, 51], "other": [4, 8, 19, 33, 41, 44, 57], "treat": [4, 60], "condit": 4, "illeg": 4, "sib": 4, "In": [4, 6, 19, 24, 25, 27, 33, 38, 41, 44, 45, 47, 51, 59, 68, 72], "case": [4, 19, 26, 33, 38, 44, 45, 47, 51, 59], "slverr": 4, "beat": [4, 11, 60], "arbitrari": 4, "place": [4, 19, 32, 33, 58], "s_axi_rdata": 4, "respons": [4, 6, 10, 14, 47, 51, 55], "discard": 4, "normal": [4, 51], "depend": [4, 6, 8, 11, 44, 51, 60], "establish": [4, 6, 39], "maintain": [4, 51, 54, 58], "point": [4, 19, 33, 44, 45], "extern": [4, 68, 77], "lost": [4, 32, 51], "re": [4, 32, 58, 59, 66, 72], "return": [4, 6, 32, 66], "hot": [4, 18, 41], "goe": [4, 41, 51, 59, 66, 72], "down": [4, 14, 19, 32, 33, 41, 44, 47, 51], "space": [4, 10, 18, 19, 25, 32, 33, 39, 42, 51, 54, 59, 69, 73], "reconfigur": [4, 24, 27, 58], "yet": 4, "associ": [4, 41, 44, 45, 51], "start": [4, 41, 51, 58, 60, 66], "bar": [4, 8, 9, 16, 19, 32, 33, 39, 44, 55, 66], "support": [4, 7, 10, 11, 15, 16, 18, 19, 22, 24, 27, 30, 33, 36, 38, 39, 41, 42, 44, 45, 47, 48, 57, 59, 64, 66, 69, 72, 76], "filter": [4, 58], "forward": [4, 8], "translat": [4, 8, 9, 25, 39], "disabl": [4, 6, 9, 11, 16, 18, 19, 32, 33, 39, 41, 44, 51, 55, 59, 73], "custom": [4, 16, 19, 25, 33, 44, 45, 47, 58, 72], "design": [4, 9, 10, 11, 15, 16, 20, 22, 24, 25, 26, 27, 28, 29, 30, 32, 34, 36, 39, 42, 44, 47, 48, 51, 58, 59, 64, 66, 67, 72, 77, 78], "suit": [4, 28, 57], "rp": [4, 19, 33, 41], "applic": [4, 11, 16, 31, 32, 44, 47, 51, 58, 59, 60, 78], "without": [4, 6, 41], "default": [4, 6, 15, 19, 22, 25, 33, 36, 51, 59], "0x0000_0000": 4, "program": [4, 9, 24, 25, 27, 29, 32, 39, 41, 44, 45, 49, 51, 54, 58, 68], "separ": [4, 19, 33, 51, 58], "hit": [4, 47], "accord": [4, 19, 33], "outsid": [4, 47, 72], "rang": [4, 9, 39], "cannot": [4, 44, 58], "recommend": [4, 9, 39, 44, 51], "do": [4, 8, 14, 16, 19, 32, 33, 38, 39, 41, 45, 47, 58, 59, 66, 72], "set_finite_credit": 4, "fals": [4, 58, 72], "infinit": [4, 60], "credit": [4, 14, 16, 19, 25, 32, 33, 44, 45, 47, 49, 51, 54, 55, 60], "advertis": [4, 39], "complex": [4, 26, 29, 42, 71], "finit": 4, "requir": [4, 18, 19, 25, 32, 33, 39, 41, 44, 45, 47, 51, 58, 72], "most": [4, 19, 33], "obei": 4, "caution": [4, 44], "verifi": [4, 19, 25, 33, 49], "function": [4, 14, 39, 44, 45, 55, 59, 73], "output": [4, 14, 19, 24, 27, 33, 44, 47, 49, 58, 68, 73], "s_axi_arreadi": 4, "s_axi_rvalid": 4, "unrespons": 4, "met": [4, 24, 27], "older": 4, "axi_ctl_aclk": 4, "axi_ctl_aclk_out": 4, "puls": 4, "out": [4, 10, 19, 25, 32, 33, 45, 52, 68, 77], "activ": [4, 47, 58, 60], "low": [4, 44, 51], "main": [4, 16], "toggl": 4, "simul": [4, 19, 24, 25, 26, 27, 29, 33, 44, 71, 78], "run": [4, 9, 19, 25, 29, 32, 33, 39, 41, 44, 47, 51, 59, 66, 72], "featur": [4, 14, 19, 22, 25, 26, 33, 36, 45, 51, 55, 58, 59, 64, 66, 72], "captur": [4, 10, 19, 33, 59, 66], "waveform": 4, "access": [4, 6, 14, 39, 44, 58], "abov": [4, 11, 19, 41, 51, 59, 60, 66], "taken": [4, 11, 19, 33, 44, 51, 60], "qdma": [4, 15, 25, 26, 29, 38, 45, 47, 48, 51, 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"sphinx.domains.std": 2, "sphinx.ext.intersphinx": 1, "sphinx.ext.todo": 2, "sphinx.ext.viewcode": 1, "sphinx": 56}}) \ No newline at end of file diff --git a/pciedebug/source/docs/Versal_ACAP_CPM_Mode_for_PCI_Express/versal_acap_cpm_example_designs.rst b/pciedebug/source/docs/Versal_ACAP_CPM_Mode_for_PCI_Express/versal_acap_cpm_example_designs.rst index ae9a19d..9dada3c 100644 --- a/pciedebug/source/docs/Versal_ACAP_CPM_Mode_for_PCI_Express/versal_acap_cpm_example_designs.rst +++ b/pciedebug/source/docs/Versal_ACAP_CPM_Mode_for_PCI_Express/versal_acap_cpm_example_designs.rst @@ -3,28 +3,42 @@ Versal ACAP CPM Example Designs =============================== -* Versal ACAP CPM5 QDMA Simulation Example Design +* Versal Adaptive SoC CPM5 QDMA Simulation Example Design - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm5_qdma -* Versal ACAP CPM4 QDMA Simulation Example Design +* Versal Adaptive SoC CPM4 QDMA Simulation Example Design - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm4_qdma -* Veral ACAP CPM5 BMD Simulation Example Design +* Versal Adaptive SoC CPM5 BMD Simulation Example Design - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm5_bmd -* Veral ACAP CPM4 BMD Simulation Example Design +* Versal Adaptive SoC CPM4 BMD Simulation Example Design - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm4_bmd -* Versal ACAP CPM - Using PCIe Link for Debug - - https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM_PCIe_Debug -* Veral ACAP Tandem PCIe Example Design - - https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_CPM_Tandem_PCIe -* Versal ACAP CPM4/CPM5 AXI Bridge Root Complex Example Design +* Versal Adaptive SoC CPM - Using PCIe Link for Debug + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIe_Debug +* Versal Adaptive SoC CPM Tandem PCIe Example Design + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_Tandem_PCIe +* Versal Adaptive SoC CPM4/CPM5 AXI Bridge Root Complex Example Design - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_Bridge_RP_Design -* Versal ACAP CPM Gen4x8 QDMA Endpoint Example Design - - https://github.com/Xilinx/XilinxCEDStore/tree/2022.2/ced/Xilinx/IPI/Versal_ACAP_CPM_Gen4x8_QDMA_EP_Design -* Versal ACAP CPM5 PCIE PIO Example Design +* Versal Adaptive SoC CPM4 QDMA Gen4x8 MM/ST Example Design + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm4_qdma +* Versal Adaptive SoC CPM4 QDMA Gen4x8 Performance Example Design + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm4_qdma_perf +* Versal Adaptive SoC CPM5 QDMA Dual Ctrl Gen4x8 MM/ST Example Design + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_dual_ctrl +* Versal Adaptive SoC CPM5 QDMA Gen5x8 MM Only Performance Example Design + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_g5x8_mm_perf +* Versal Adaptive SoC CPM5 QDMA Gen4x8 MM/ST Example Design + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_mm_st +* Versal Adaptive SoC CPM5 QDMA Gen4x8 ST Only Performance Design + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_st_only +* Versal Adaptive SoC CPM5 PCIE PIO Example Design - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm5_pcie_pio -* Versal ACAP CPM4 PCIE PIO Example Design +* Versal Adaptive SoC CPM4 PCIE PIO Example Design - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm4_pcie_pio -* Versal ACAP CPM5 PCIE BMD EndPoint Example Design +* Versal Adaptive SoC CPM5 PCIE BMD EndPoint Example Design - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm5_bmd_ep -* Versal ACAP CPM4 PCIE BMD EndPoint Example Design - - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm4_bmd_ep +* Versal Adaptive SoC CPM4 PCIE BMD EndPoint Example Design + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm4_bmd_ep +* Versal Adaptive SoC CPM5 QDMA Dual Ctrl Gen5x8 Performance Example Design (Part Based) + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design_PartBased/cpm5_qdma_g5x8_dual_perf +* Versal Adaptive SoC CPM5 QDMA Gen5x8 ST Performance Example Design (Part Based) + - https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design_PartBased/cpm5_qdma_g5x8_st_perf