From 23c3f82a87a405d996ad6e3b096ca9352314adf1 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Wed, 31 Jan 2024 10:36:52 +0000 Subject: [PATCH 1/3] [Tests] Temporarily re-enable SWG exception for bnn_w2_a2_cnv_Pynq-Z1 test --- tests/end2end/test_end2end_bnn_pynq.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index b296dad827..9fb41ec78e 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -653,7 +653,13 @@ def test_set_fifo_depths(self, topology, wbits, abits, board): prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "ipgen_" + board) model = load_test_checkpoint_or_skip(prev_chkpt_name) test_fpga_part = get_build_env(board, target_clk_ns)["part"] - model = model.transform(InsertAndSetFIFODepths(test_fpga_part, target_clk_ns)) + if topology == "cnv" and wbits == 2 and abits == 2 and board == "Pynq-Z1": + # Enabling swg_exception for this single test case. Disabling the exception results in a design + # that exceeds the resources of the Pynq-Z1 board. In future this should be revisited and handled + # correctly as the swg_exception is poorly justified. + model = model.transform(InsertAndSetFIFODepths(test_fpga_part, target_clk_ns, swg_exception=True)) + else: + model = model.transform(InsertAndSetFIFODepths(test_fpga_part, target_clk_ns)) fifo_layers = model.get_nodes_by_op_type("StreamingFIFO") assert len(fifo_layers) > 0 model.save(get_checkpoint_name(topology, wbits, abits, "fifodepth_" + board)) From 562d153b96c96ac28968d01a9f09b2be9471ea17 Mon Sep 17 00:00:00 2001 From: johnnoel Date: Wed, 31 Jan 2024 13:37:50 +0000 Subject: [PATCH 2/3] [Tests] Fix fpgadataflow split large fifos test --- tests/fpgadataflow/test_split_large_fifos.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/fpgadataflow/test_split_large_fifos.py b/tests/fpgadataflow/test_split_large_fifos.py index 3061696a68..653e1e7896 100644 --- a/tests/fpgadataflow/test_split_large_fifos.py +++ b/tests/fpgadataflow/test_split_large_fifos.py @@ -54,7 +54,7 @@ def fetch_test_model(topology, wbits=2, abits=2): def get_folding_cfg(depth=65536): cfg = dict() cfg["Defaults"] = dict() - for i in range(3): + for i in range(4): key = "StreamingFIFO_" + str(i) cfg[key] = {"depth": depth, "ram_style": "auto", "impl_style": "vivado"} return cfg From a884e11ff52023e68a0f798c47bf777bacb873df Mon Sep 17 00:00:00 2001 From: johnnoel Date: Wed, 31 Jan 2024 13:48:05 +0000 Subject: [PATCH 3/3] Fix linting --- tests/end2end/test_end2end_bnn_pynq.py | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/tests/end2end/test_end2end_bnn_pynq.py b/tests/end2end/test_end2end_bnn_pynq.py index 9fb41ec78e..db065fec42 100644 --- a/tests/end2end/test_end2end_bnn_pynq.py +++ b/tests/end2end/test_end2end_bnn_pynq.py @@ -654,10 +654,12 @@ def test_set_fifo_depths(self, topology, wbits, abits, board): model = load_test_checkpoint_or_skip(prev_chkpt_name) test_fpga_part = get_build_env(board, target_clk_ns)["part"] if topology == "cnv" and wbits == 2 and abits == 2 and board == "Pynq-Z1": - # Enabling swg_exception for this single test case. Disabling the exception results in a design - # that exceeds the resources of the Pynq-Z1 board. In future this should be revisited and handled - # correctly as the swg_exception is poorly justified. - model = model.transform(InsertAndSetFIFODepths(test_fpga_part, target_clk_ns, swg_exception=True)) + # Enabling swg_exception for this single test case. Disabling the exception results in + # a design that exceeds the resources of the Pynq-Z1 board. In future this should be + # revisited and handled correctly as the swg_exception is poorly justified. + model = model.transform( + InsertAndSetFIFODepths(test_fpga_part, target_clk_ns, swg_exception=True) + ) else: model = model.transform(InsertAndSetFIFODepths(test_fpga_part, target_clk_ns)) fifo_layers = model.get_nodes_by_op_type("StreamingFIFO")