- Synopsis
-
Ensures that all preceding instructions retire earlier than this instruction and all subsequent instructions retire later than this instruction and clears the pipeline when this instruction retires.
- Mnemonic
-
th.sync.i
- Encoding
{reg:[
{ bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] },
{ bits: 5, name: 0x0 },
{ bits: 3, name: 0x0, attr: ['CMO'] },
{ bits: 5, name: 0x0 },
{ bits: 5, name: 0x1A, attr: ['SYNC.I'] },
{ bits: 7, name: 0x00 },
]}
- Description
-
Besides the synopsis of th.sync, this instruction flushes the pipeline of current hart which means all subsequent instructions should be re-fectched after this instruction retires. This instruction is the only mechanism to ensure that all explicit memory accesses or cache operations visible to a hart will also be visible to its instruction fetches.
- Operation
out_of_order_barrier()
pipeline_flush()- Permission
-
This instruction can be executed in all privilege levels.
- Exceptions
-
This instruction does not trigger any exceptions.
- Included in
| Extension |
|---|
XTheadSync ([xtheasync]) |