| counter | LUlargev1w1 | LUlargev1w128 | LUlargev2w128 | LUlargev3w1 | LUlargev3w128 | LUlargev3w256 |
|---|---|---|---|---|---|---|
| duration | 26375.0000 | 22525.0000 | 22443.0000 | 30806.0000 | 21846.0000 | 18425.0000 |
| task-clock | 26504.6500 | 22659.3000 | 22526.3100 | 30899.7200 | 21911.7400 | 18490.0900 |
| cycles | 92.5634 | 79.0345 | 78.6444 | 107.9251 | 76.5048 | 64.5657 |
| stalled-cycles-backend | 0.0000 | 0.0509 | 0.0651 | 0.0000 | 0.0000 | 0.0000 |
| stalled-cycles-frontend | 0.0538 | 0.0499 | 0.0470 | 0.0618 | 0.0453 | 0.0415 |
| iTLB-load-misses | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| iTLB-loads | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| instructions | 367.2206 | 184.7312 | 184.6110 | 275.5152 | 138.1665 | 69.8570 |
| branch-instructions | 45.9260 | 23.0771 | 23.1137 | 45.9071 | 23.0308 | 11.6358 |
| branch-misses | 0.0282 | 0.0304 | 0.0219 | 0.0249 | 0.0224 | 0.0223 |
| ex_ret_ops | 321.5804 | 161.5737 | 161.7814 | 229.8741 | 115.4702 | 58.5382 |
| ex_div_busy | 0.0034 | 0.0029 | 0.0029 | 0.0040 | 0.0028 | 0.0024 |
| ex_ret_mmx_fp_instr.sse_instr | 229.1013 | 114.7269 | 114.9389 | 137.4060 | 68.9391 | 34.6064 |
| fp_ret_sse_avx_ops.all | 91.5596 | 91.7087 | 91.7822 | 91.4057 | 91.6120 | 91.5981 |
| fp_num_mov_elim_scal_op.sse_mov_ops | 0.0449 | 0.0172 | 0.0089 | 0.0000 | 0.0000 | 0.0000 |
| fp_num_mov_elim_scal_op.sse_mov_ops_elim | 0.0440 | 0.0173 | 0.0089 | 0.0000 | 0.0000 | 0.0000 |
| fp_ret_sse_avx_ops.add_sub_flops | 45.8872 | 45.8792 | 45.9697 | 0.0122 | 0.0026 | 0.0025 |
| fp_ret_sse_avx_ops.mult_flops | 45.9231 | 45.8438 | 45.9442 | 0.0246 | 0.0164 | 0.0172 |
| fp_ret_sse_avx_ops.mac_flops | 0.0000 | 0.0000 | 0.0000 | 91.8114 | 91.5859 | 91.8217 |
| fp_ret_sse_avx_ops.div_flops | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| de_dis_cops_from_decoder.disp_op_type.any_fp_dispatch | 230.3780 | 115.5506 | 115.4733 | 138.2715 | 69.4219 | 35.1039 |
| de_dis_cops_from_decoder.disp_op_type.any_integer_dispatch | 93.5298 | 47.6897 | 47.2706 | 93.1689 | 47.0691 | 24.3033 |
| cache-misses | 0.5401 | 0.4875 | 0.4953 | 0.6009 | 0.6692 | 0.6646 |
| cache-references | 20.3993 | 21.4778 | 21.4468 | 19.0846 | 21.9246 | 21.1738 |
| all_data_cache_accesses | 138.3182 | 69.5695 | 69.3532 | 137.9900 | 69.4882 | 35.1035 |
| L1-dcache-load-misses | 10.9412 | 10.8973 | 10.8640 | 11.0542 | 10.9397 | 10.9716 |
| L1-dcache-loads | 137.8861 | 77.6149 | 77.9594 | 137.9212 | 78.1004 | 48.0293 |
| L1-dcache-prefetches | 6.9356 | 3.8578 | 3.8005 | 10.0403 | 3.6810 | 3.8806 |
| L1-icache-load-misses | 0.0006 | 0.0009 | 0.0008 | 0.0005 | 0.0006 | 0.0008 |
| L1-icache-loads | 0.0613 | 0.0872 | 0.0628 | 0.0845 | 0.0615 | 0.0813 |
| l2_cache_accesses_from_dc_misses | 10.9462 | 10.8508 | 10.8647 | 11.0572 | 10.9389 | 10.9811 |
| l2_cache_hits_from_dc_misses | 9.5586 | 9.3315 | 9.3738 | 10.4328 | 9.1964 | 8.8820 |
| l2_cache_misses_from_dc_misses | 0.1335 | 0.1718 | 0.1702 | 0.1298 | 0.1799 | 0.2655 |
| dTLB-load-misses | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
| dTLB-loads | 0.0071 | 0.0068 | 0.0066 | 0.0073 | 0.0069 | 0.0066 |
| ls_dispatch.ld_dispatch | 92.1505 | 46.3732 | 46.3236 | 92.0155 | 46.2536 | 23.4490 |
| ls_dispatch.ld_st_dispatch | 0.0029 | 0.0025 | 0.0025 | 0.0033 | 0.0024 | 0.0020 |
| ls_dispatch.store_dispatch | 46.0141 | 23.1283 | 23.0938 | 45.9977 | 23.0678 | 11.6331 |