test/Makefile COMPILE_ARGS += -I$(SRC_DIR) needed to make verilog include work

[dlmiles]

https://github.com/TinyTapeout/tt09-verilog-template/blob/main/test/Makefile#L15

COMPILE_ARGS += -I$(SRC_DIR)

This line should be available to both pre-synth and post-impl (gate-level) testing.

Since splitting the src/** and test/** the use of verilog include "file.v" is broken if the test bench is picking up configuration options from such an included file.

I would expect a testbench to have full visibility of the main sources it is testing.