From e7e1e3b0ef02601ad0e19599f527529446897d5d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Sun, 15 Sep 2024 09:26:57 +0200 Subject: [PATCH] sram: fakeram vs. mock SRAM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- openroad.bzl | 73 +- sram/.gitignore | 1 + sram/BUILD | 105 ++ sram/README.md | 31 + sram/fakeram/constraints-sram.sdc | 9 + sram/fakeram/sdq_17x64.lef | 1304 +++++++++++++++++++++ sram/fakeram/sdq_17x64.lib | 1684 ++++++++++++++++++++++++++++ sram/fakeram/sdq_17x64.sv | 36 + sram/fakeram/top.v | 17 + sram/megaboom/constraints-sram.sdc | 11 + sram/megaboom/constraints-top.sdc | 13 + sram/megaboom/sdq_17x64.sv | 18 + sram/megaboom/top.v | 21 + 13 files changed, 3318 insertions(+), 5 deletions(-) create mode 100644 sram/.gitignore create mode 100644 sram/BUILD create mode 100644 sram/README.md create mode 100644 sram/fakeram/constraints-sram.sdc create mode 100644 sram/fakeram/sdq_17x64.lef create mode 100644 sram/fakeram/sdq_17x64.lib create mode 100644 sram/fakeram/sdq_17x64.sv create mode 100644 sram/fakeram/top.v create mode 100644 sram/megaboom/constraints-sram.sdc create mode 100644 sram/megaboom/constraints-top.sdc create mode 100644 sram/megaboom/sdq_17x64.sv create mode 100644 sram/megaboom/top.v diff --git a/openroad.bzl b/openroad.bzl index 672f425..6ba5d32 100644 --- a/openroad.bzl +++ b/openroad.bzl @@ -1215,6 +1215,8 @@ STAGE_IMPLS = [ ABSTRACT_IMPL = struct(stage = "generate_abstract", impl = orfs_abstract) +ALL_STAGES = ["synth", "floorplan", "place", "cts", "grt", "route", "final", "generate_abstract"] + # A stage argument is used in one or more stages. This is metainformation # about the ORFS code that there is no known nice way for ORFS to # provide. @@ -1233,7 +1235,7 @@ STAGE_ARGS_USES = { "TNS_END_PERCENT": ["cts", "floorplan", "grt"], "SKIP_CTS_REPAIR_TIMING": ["cts"], "CORE_MARGIN": ["floorplan"], - "SKIP_REPORT_METRICS": ["all"], + "SKIP_REPORT_METRICS": ["floorplan", "place", "cts", "grt", "route", "final"], "SYNTH_HIERARCHICAL": ["synth"], "RTLMP_FLOW": ["floorplan"], "MACRO_PLACE_HALO": ["floorplan"], @@ -1247,6 +1249,48 @@ STAGE_ARGS_USES = { "ROUTING_LAYER_ADJUSTMENT": ["place", "grt", "route", "final"], "FILL_CELLS": ["route"], "TAPCELL_TCL": ["floorplan"], + "ADDITIONAL_LEFS": ALL_STAGES, + "ADDITIONAL_LIBS": ALL_STAGES, +} + +def flatten(xs): + """Flattens a nested list iteratively. + + Args: + xs: A list that may contain other lists, maximum two levels + Returns: + A flattened list. + """ + result = [] + for x in xs: + if type(x) == "list": + for y in x: + if type(y) == "list": + fail("Nested lists are not supported") + else: + result.append(y) + else: + result.append(x) + return result + + +def set(iterable): + """Creates a set-like collection from an iterable. + + Args: + iterable: An iterable containing elements. + Returns: + A list with unique elements. + """ + unique_dict = {} + for item in iterable: + unique_dict[item] = True + return list(unique_dict.keys()) + +STAGE_TO_VARIABLES = { + stage: [variable for variable, stages in STAGE_ARGS_USES.items() + if stage in stages] + for stage in ALL_STAGES } def get_stage_args(stage, stage_args, args): @@ -1266,6 +1310,21 @@ def get_stage_args(stage, stage_args, args): } | stage_args.get(stage, {})) +def get_sources(stage, stage_sources, sources): + """Returns the sources for a specific stage. + + Args: + stage: The stage name. + stage_sources: the dictionary of stages with each stage having a list of sources + sources: a dictionary of variable names with a list of sources to a stage + Returns: + A list of sources for the stage. + """ + return set(stage_sources.get(stage, []) + + flatten([source_list for variable, source_list in sources.items() + if variable in STAGE_TO_VARIABLES[stage]])) + + def _deep_dict_copy(d): new_d = dict(d) for k, v in new_d.items(): @@ -1278,6 +1337,7 @@ def _mock_area_targets( steps, verilog_files = [], macros = [], + sources = {}, stage_sources = {}, stage_args = {}, args = {}, @@ -1307,7 +1367,7 @@ def _mock_area_targets( synth_step.impl( name = "{}_{}_mock_area".format(name_variant, synth_step.stage), arguments = get_stage_args(synth_step.stage, stage_args, args), - data = stage_sources.get(synth_step.stage, []), + data = get_sources(synth_step.stage, stage_sources, sources), deps = macros, module_top = name, variant = mock_variant, @@ -1341,7 +1401,7 @@ def _mock_area_targets( name = "{}_{}{}".format(name_variant, step.stage, suffix), src = "{}_{}_mock_area".format(name_variant, prev.stage, suffix), arguments = get_stage_args(step.stage, stage_args, args), - data = stage_sources.get(step.stage, []), + data = get_sources(step.stage, stage_sources, sources), variant = mock_variant, visibility = visibility, **extra_args @@ -1356,6 +1416,7 @@ def orfs_flow( name, verilog_files = [], macros = [], + sources = {}, stage_sources = {}, stage_args = {}, args = {}, @@ -1370,6 +1431,7 @@ def orfs_flow( name: name of the macro target verilog_files: list of verilog sources of the design macros: list of macros required to run physical design flow for this design + sources: dictionary keyed by ORFS variables with lists of sources stage_sources: dictionary keyed by ORFS stages with lists of stage-specific sources stage_args: dictionary keyed by ORFS stages with lists of stage-specific arguments args: dictionary of additional arguments to the flow, automatically assigned to stages @@ -1392,7 +1454,7 @@ def orfs_flow( synth_step.impl( name = "{}_{}".format(name_variant, synth_step.stage), arguments = get_stage_args(synth_step.stage, stage_args, args), - data = stage_sources.get(synth_step.stage, []), + data = get_sources(synth_step.stage, stage_sources, sources), deps = macros, module_top = name, variant = variant, @@ -1409,7 +1471,7 @@ def orfs_flow( name = "{}_{}".format(name_variant, step.stage), src = "{}_{}".format(name_variant, prev.stage), arguments = get_stage_args(step.stage, stage_args, args), - data = stage_sources.get(step.stage, []), + data = get_sources(step.stage, stage_sources, sources), variant = variant, visibility = visibility, ) @@ -1427,6 +1489,7 @@ def orfs_flow( steps, verilog_files, macros, + sources, stage_sources, stage_args, args, diff --git a/sram/.gitignore b/sram/.gitignore new file mode 100644 index 0000000..567609b --- /dev/null +++ b/sram/.gitignore @@ -0,0 +1 @@ +build/ diff --git a/sram/BUILD b/sram/BUILD new file mode 100644 index 0000000..9f7b2f6 --- /dev/null +++ b/sram/BUILD @@ -0,0 +1,105 @@ +load("//:openroad.bzl", "orfs_flow") + +FAST_SETTINGS = { + "REMOVE_ABC_BUFFERS": "1", + "SKIP_REPORT_METRICS": "1", + "SKIP_CTS_REPAIR_TIMING": "1", + "SKIP_INCREMENTAL_REPAIR": "1", +} + +orfs_flow( + name = "sdq_17x64", + abstract_stage = "grt", + mock_area = 0.95, + args = FAST_SETTINGS | { + "SDC_FILE": "$(location //sram:fakeram/constraints-sram.sdc)", + "CORE_UTILIZATION": "20", + "CORE_MARGIN": "2", + "MACRO_PLACE_HALO": "30 30", + "PLACE_DENSITY": "0.25", + }, + stage_sources = { + "synth": ["//sram:fakeram/constraints-sram.sdc"], + }, + verilog_files = ["//sram:fakeram/sdq_17x64.sv"], +) + +orfs_flow( + name = "top", + abstract_stage = "grt", + macros = ["//sram:sdq_17x64_generate_abstract"], + args = FAST_SETTINGS | { + "SDC_FILE": "$(location //sram:fakeram/constraints-sram.sdc)", + "DIE_AREA": "0 0 100 100", + "CORE_AREA": "2 2 98 98", + "RTLMP_FLOW": "True", + "CORE_MARGIN": "2", + "MACRO_PLACE_HALO": "2 2", + }, + stage_sources = { + "synth": ["//sram:fakeram/constraints-sram.sdc"], + }, + verilog_files = ["//sram:fakeram/top.v"], +) + +# buildifier: disable=duplicated-name +orfs_flow( + name = "top", + variant="fakeram", + abstract_stage = "grt", + args = FAST_SETTINGS | { + "SDC_FILE": "$(location //sram:fakeram/constraints-sram.sdc)", + "DIE_AREA": "0 0 30 30", + "CORE_AREA": "2 2 28 28", + "RTLMP_FLOW": "True", + "CORE_MARGIN": "2", + "MACRO_PLACE_HALO": "2 2", + "ADDITIONAL_LEFS": "$(location //sram:fakeram/sdq_17x64.lef)", + "ADDITIONAL_LIBS": "$(location //sram:fakeram/sdq_17x64.lib)", + }, + sources = { + "ADDITIONAL_LEFS" : ["//sram:fakeram/sdq_17x64.lef"], + "ADDITIONAL_LIBS" : ["//sram:fakeram/sdq_17x64.lib"], + "SDC_FILE": ["//sram:fakeram/constraints-sram.sdc"], + }, + verilog_files = ["//sram:fakeram/top.v"], +) + +# buildifier: disable=duplicated-name +orfs_flow( + name = "sdq_17x64", + variant = "megaboom", + abstract_stage = "grt", + mock_area = 0.95, + args = FAST_SETTINGS | { + "SDC_FILE": "$(location //sram:megaboom/constraints-sram.sdc)", + "CORE_UTILIZATION": "20", + "CORE_MARGIN": "2", + "MACRO_PLACE_HALO": "30 30", + "PLACE_DENSITY": "0.25", + }, + stage_sources = { + "synth": ["//sram:megaboom/constraints-sram.sdc"], + }, + verilog_files = ["//sram:megaboom/sdq_17x64.sv"], +) + +# buildifier: disable=duplicated-name +orfs_flow( + name = "top", + abstract_stage = "grt", + variant = "megaboom", + macros = ["//sram:sdq_17x64_megaboom_generate_abstract"], + args = FAST_SETTINGS | { + "SDC_FILE": "$(location //sram:megaboom/constraints-top.sdc)", + "DIE_AREA": "0 0 100 100", + "CORE_AREA": "2 2 98 98", + "RTLMP_FLOW": "True", + "CORE_MARGIN": "2", + "MACRO_PLACE_HALO": "2 2", + }, + stage_sources = { + "synth": ["//sram:megaboom/constraints-top.sdc"], + }, + verilog_files = ["//sram:megaboom/top.v"], +) diff --git a/sram/README.md b/sram/README.md new file mode 100644 index 0000000..5fd74c4 --- /dev/null +++ b/sram/README.md @@ -0,0 +1,31 @@ +fakeram vs. mock SRAM +===================== + +fakeram is a .lib, .lef and .v file generated by the fakeram tool. + +mocked SRAM takes as input the design's behavioral model Verilog file and is used to generate a .lef and .lib file. + +Mock SRAM based on fakeram's behavioral .v file +----------------------------------------------- + +The .v file generated by fakeram does not build with yosys unmodified. The fakeram/sdq_17x64.sv has been manually pruned until it passed yosys. + + bazel run //sram:top_grt `pwd`/build + build/make gui_grt + +fakeram +------- + +There is a problem with this setup: there is no clock visible in the OpenROAD GUI. A problem with the fakeram .lib file? + + bazel run //sram:top_fakeram_grt `pwd`/build + build/make gui_grt + + +MegaBoom mock SRAM +------------------ + +A mock SRAM based on the MegaBoom behavioral Verilog. + + bazel run //sram:top_megaboom_grt `pwd`/build + build/make gui_grt diff --git a/sram/fakeram/constraints-sram.sdc b/sram/fakeram/constraints-sram.sdc new file mode 100644 index 0000000..6fee7cd --- /dev/null +++ b/sram/fakeram/constraints-sram.sdc @@ -0,0 +1,9 @@ +set clk_name clk +set clk_port_name clk +set clk_period 400 + +if { [llength [all_registers]] > 0} { + source $env(PLATFORM_DIR)/constraints.sdc +} else { + puts "The design is gutted when mocking floorplan" +} diff --git a/sram/fakeram/sdq_17x64.lef b/sram/fakeram/sdq_17x64.lef new file mode 100644 index 0000000..d21d786 --- /dev/null +++ b/sram/fakeram/sdq_17x64.lef @@ -0,0 +1,1304 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO sdq_17x64 + PROPERTY width 64 ; + PROPERTY depth 17 ; + PROPERTY banks 1 ; + FOREIGN sdq_17x64 0 0 ; + SYMMETRY X Y R90 ; + SIZE 13.490 BY 14.000 ; + CLASS BLOCK ; + PIN rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.024 0.072 ; + END + END rd_out[0] + PIN rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.144 0.024 0.168 ; + END + END rd_out[1] + PIN rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.240 0.024 0.264 ; + END + END rd_out[2] + PIN rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.336 0.024 0.360 ; + END + END rd_out[3] + PIN rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.432 0.024 0.456 ; + END + END rd_out[4] + PIN rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.528 0.024 0.552 ; + END + END rd_out[5] + PIN rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.624 0.024 0.648 ; + END + END rd_out[6] + PIN rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.720 0.024 0.744 ; + END + END rd_out[7] + PIN rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.816 0.024 0.840 ; + END + END rd_out[8] + PIN rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.912 0.024 0.936 ; + END + END rd_out[9] + PIN rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.008 0.024 1.032 ; + END + END rd_out[10] + PIN rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.104 0.024 1.128 ; + END + END rd_out[11] + PIN rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.200 0.024 1.224 ; + END + END rd_out[12] + PIN rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.296 0.024 1.320 ; + END + END rd_out[13] + PIN rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.392 0.024 1.416 ; + END + END rd_out[14] + PIN rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.488 0.024 1.512 ; + END + END rd_out[15] + PIN rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.584 0.024 1.608 ; + END + END rd_out[16] + PIN rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.680 0.024 1.704 ; + END + END rd_out[17] + PIN rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.776 0.024 1.800 ; + END + END rd_out[18] + PIN rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.872 0.024 1.896 ; + END + END rd_out[19] + PIN rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.968 0.024 1.992 ; + END + END rd_out[20] + PIN rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.064 0.024 2.088 ; + END + END rd_out[21] + PIN rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.160 0.024 2.184 ; + END + END rd_out[22] + PIN rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.256 0.024 2.280 ; + END + END rd_out[23] + PIN rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.352 0.024 2.376 ; + END + END rd_out[24] + PIN rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.448 0.024 2.472 ; + END + END rd_out[25] + PIN rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.544 0.024 2.568 ; + END + END rd_out[26] + PIN rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.640 0.024 2.664 ; + END + END rd_out[27] + PIN rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.736 0.024 2.760 ; + END + END rd_out[28] + PIN rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.832 0.024 2.856 ; + END + END rd_out[29] + PIN rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.928 0.024 2.952 ; + END + END rd_out[30] + PIN rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.024 0.024 3.048 ; + END + END rd_out[31] + PIN rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.120 0.024 3.144 ; + END + END rd_out[32] + PIN rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.216 0.024 3.240 ; + END + END rd_out[33] + PIN rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.312 0.024 3.336 ; + END + END rd_out[34] + PIN rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.408 0.024 3.432 ; + END + END rd_out[35] + PIN rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.504 0.024 3.528 ; + END + END rd_out[36] + PIN rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.600 0.024 3.624 ; + END + END rd_out[37] + PIN rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.696 0.024 3.720 ; + END + END rd_out[38] + PIN rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.792 0.024 3.816 ; + END + END rd_out[39] + PIN rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.888 0.024 3.912 ; + END + END rd_out[40] + PIN rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.984 0.024 4.008 ; + END + END rd_out[41] + PIN rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.080 0.024 4.104 ; + END + END rd_out[42] + PIN rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.176 0.024 4.200 ; + END + END rd_out[43] + PIN rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.272 0.024 4.296 ; + END + END rd_out[44] + PIN rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.368 0.024 4.392 ; + END + END rd_out[45] + PIN rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.464 0.024 4.488 ; + END + END rd_out[46] + PIN rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.560 0.024 4.584 ; + END + END rd_out[47] + PIN rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.656 0.024 4.680 ; + END + END rd_out[48] + PIN rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.752 0.024 4.776 ; + END + END rd_out[49] + PIN rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.848 0.024 4.872 ; + END + END rd_out[50] + PIN rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.944 0.024 4.968 ; + END + END rd_out[51] + PIN rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.040 0.024 5.064 ; + END + END rd_out[52] + PIN rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.136 0.024 5.160 ; + END + END rd_out[53] + PIN rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.232 0.024 5.256 ; + END + END rd_out[54] + PIN rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.328 0.024 5.352 ; + END + END rd_out[55] + PIN rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.424 0.024 5.448 ; + END + END rd_out[56] + PIN rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.520 0.024 5.544 ; + END + END rd_out[57] + PIN rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.616 0.024 5.640 ; + END + END rd_out[58] + PIN rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.712 0.024 5.736 ; + END + END rd_out[59] + PIN rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.808 0.024 5.832 ; + END + END rd_out[60] + PIN rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.904 0.024 5.928 ; + END + END rd_out[61] + PIN rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.000 0.024 6.024 ; + END + END rd_out[62] + PIN rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.096 0.024 6.120 ; + END + END rd_out[63] + PIN wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.432 0.024 6.456 ; + END + END wd_in[0] + PIN wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.528 0.024 6.552 ; + END + END wd_in[1] + PIN wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.624 0.024 6.648 ; + END + END wd_in[2] + PIN wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.720 0.024 6.744 ; + END + END wd_in[3] + PIN wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.816 0.024 6.840 ; + END + END wd_in[4] + PIN wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.912 0.024 6.936 ; + END + END wd_in[5] + PIN wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.008 0.024 7.032 ; + END + END wd_in[6] + PIN wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.104 0.024 7.128 ; + END + END wd_in[7] + PIN wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.200 0.024 7.224 ; + END + END wd_in[8] + PIN wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.296 0.024 7.320 ; + END + END wd_in[9] + PIN wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.392 0.024 7.416 ; + END + END wd_in[10] + PIN wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.488 0.024 7.512 ; + END + END wd_in[11] + PIN wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.584 0.024 7.608 ; + END + END wd_in[12] + PIN wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.680 0.024 7.704 ; + END + END wd_in[13] + PIN wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.776 0.024 7.800 ; + END + END wd_in[14] + PIN wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.872 0.024 7.896 ; + END + END wd_in[15] + PIN wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.968 0.024 7.992 ; + END + END wd_in[16] + PIN wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.064 0.024 8.088 ; + END + END wd_in[17] + PIN wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.160 0.024 8.184 ; + END + END wd_in[18] + PIN wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.256 0.024 8.280 ; + END + END wd_in[19] + PIN wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.352 0.024 8.376 ; + END + END wd_in[20] + PIN wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.448 0.024 8.472 ; + END + END wd_in[21] + PIN wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.544 0.024 8.568 ; + END + END wd_in[22] + PIN wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.640 0.024 8.664 ; + END + END wd_in[23] + PIN wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.736 0.024 8.760 ; + END + END wd_in[24] + PIN wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.832 0.024 8.856 ; + END + END wd_in[25] + PIN wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.928 0.024 8.952 ; + END + END wd_in[26] + PIN wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.024 0.024 9.048 ; + END + END wd_in[27] + PIN wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.120 0.024 9.144 ; + END + END wd_in[28] + PIN wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.216 0.024 9.240 ; + END + END wd_in[29] + PIN wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.312 0.024 9.336 ; + END + END wd_in[30] + PIN wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.408 0.024 9.432 ; + END + END wd_in[31] + PIN wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.504 0.024 9.528 ; + END + END wd_in[32] + PIN wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.600 0.024 9.624 ; + END + END wd_in[33] + PIN wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.696 0.024 9.720 ; + END + END wd_in[34] + PIN wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.792 0.024 9.816 ; + END + END wd_in[35] + PIN wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.888 0.024 9.912 ; + END + END wd_in[36] + PIN wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.984 0.024 10.008 ; + END + END wd_in[37] + PIN wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.080 0.024 10.104 ; + END + END wd_in[38] + PIN wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.176 0.024 10.200 ; + END + END wd_in[39] + PIN wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.272 0.024 10.296 ; + END + END wd_in[40] + PIN wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.368 0.024 10.392 ; + END + END wd_in[41] + PIN wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.464 0.024 10.488 ; + END + END wd_in[42] + PIN wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.560 0.024 10.584 ; + END + END wd_in[43] + PIN wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.656 0.024 10.680 ; + END + END wd_in[44] + PIN wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.752 0.024 10.776 ; + END + END wd_in[45] + PIN wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.848 0.024 10.872 ; + END + END wd_in[46] + PIN wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.944 0.024 10.968 ; + END + END wd_in[47] + PIN wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.040 0.024 11.064 ; + END + END wd_in[48] + PIN wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.136 0.024 11.160 ; + END + END wd_in[49] + PIN wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.232 0.024 11.256 ; + END + END wd_in[50] + PIN wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.328 0.024 11.352 ; + END + END wd_in[51] + PIN wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.424 0.024 11.448 ; + END + END wd_in[52] + PIN wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.520 0.024 11.544 ; + END + END wd_in[53] + PIN wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.616 0.024 11.640 ; + END + END wd_in[54] + PIN wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.712 0.024 11.736 ; + END + END wd_in[55] + PIN wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.808 0.024 11.832 ; + END + END wd_in[56] + PIN wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.904 0.024 11.928 ; + END + END wd_in[57] + PIN wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.000 0.024 12.024 ; + END + END wd_in[58] + PIN wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.096 0.024 12.120 ; + END + END wd_in[59] + PIN wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.192 0.024 12.216 ; + END + END wd_in[60] + PIN wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.288 0.024 12.312 ; + END + END wd_in[61] + PIN wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.384 0.024 12.408 ; + END + END wd_in[62] + PIN wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.480 0.024 12.504 ; + END + END wd_in[63] + PIN addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.816 0.024 12.840 ; + END + END addr_in[0] + PIN addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.912 0.024 12.936 ; + END + END addr_in[1] + PIN addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.008 0.024 13.032 ; + END + END addr_in[2] + PIN addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.104 0.024 13.128 ; + END + END addr_in[3] + PIN addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.200 0.024 13.224 ; + END + END addr_in[4] + PIN we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.536 0.024 13.560 ; + END + END we_in + PIN ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.632 0.024 13.656 ; + END + END ce_in + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.728 0.024 13.752 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.048 0.000 13.442 0.096 ; + RECT 0.048 0.768 13.442 0.864 ; + RECT 0.048 1.536 13.442 1.632 ; + RECT 0.048 2.304 13.442 2.400 ; + RECT 0.048 3.072 13.442 3.168 ; + RECT 0.048 3.840 13.442 3.936 ; + RECT 0.048 4.608 13.442 4.704 ; + RECT 0.048 5.376 13.442 5.472 ; + RECT 0.048 6.144 13.442 6.240 ; + RECT 0.048 6.912 13.442 7.008 ; + RECT 0.048 7.680 13.442 7.776 ; + RECT 0.048 8.448 13.442 8.544 ; + RECT 0.048 9.216 13.442 9.312 ; + RECT 0.048 9.984 13.442 10.080 ; + RECT 0.048 10.752 13.442 10.848 ; + RECT 0.048 11.520 13.442 11.616 ; + RECT 0.048 12.288 13.442 12.384 ; + RECT 0.048 13.056 13.442 13.152 ; + RECT 0.048 13.824 13.442 13.920 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.048 0.384 13.442 0.480 ; + RECT 0.048 1.152 13.442 1.248 ; + RECT 0.048 1.920 13.442 2.016 ; + RECT 0.048 2.688 13.442 2.784 ; + RECT 0.048 3.456 13.442 3.552 ; + RECT 0.048 4.224 13.442 4.320 ; + RECT 0.048 4.992 13.442 5.088 ; + RECT 0.048 5.760 13.442 5.856 ; + RECT 0.048 6.528 13.442 6.624 ; + RECT 0.048 7.296 13.442 7.392 ; + RECT 0.048 8.064 13.442 8.160 ; + RECT 0.048 8.832 13.442 8.928 ; + RECT 0.048 9.600 13.442 9.696 ; + RECT 0.048 10.368 13.442 10.464 ; + RECT 0.048 11.136 13.442 11.232 ; + RECT 0.048 11.904 13.442 12.000 ; + RECT 0.048 12.672 13.442 12.768 ; + RECT 0.048 13.440 13.442 13.536 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 13.490 14.000 ; + LAYER M2 ; + RECT 0 0 13.490 14.000 ; + LAYER M3 ; + RECT 0 0 13.490 14.000 ; + LAYER M4 ; + RECT 0 0 13.490 14.000 ; + END +END sdq_17x64 + +END LIBRARY diff --git a/sram/fakeram/sdq_17x64.lib b/sram/fakeram/sdq_17x64.lib new file mode 100644 index 0000000..c0473bc --- /dev/null +++ b/sram/fakeram/sdq_17x64.lib @@ -0,0 +1,1684 @@ +library (sdq_17x64) { + /* Models written by mk_SRAM_lib.py */ + delay_model : table_lookup; + comment : ""; + date : "$Date: Sun Apr 18 12:26:29 2021 $"; + revision : "1.0"; + capacitive_load_unit (1,pf); + current_unit : "1mA"; + leakage_power_unit : "1nW"; + pulling_resistance_unit : "1kohm"; + time_unit : "1ns"; + voltage_unit : "1V"; + voltage_map (VDD, 0.7); + voltage_map (VSS, 0); + voltage_map (GND, 0); + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.005; + default_input_pin_cap : 0.005; + default_leakage_power_density : 0; + default_max_transition : 6; + default_output_pin_cap : 0; + in_place_swap_mode : match_footprint; + input_threshold_pct_fall : 50; + input_threshold_pct_rise : 50; + nom_process : 1; + nom_temperature : 25; + nom_voltage : 0.7; + output_threshold_pct_fall : 50; + output_threshold_pct_rise : 50; + slew_derate_from_library : 0.5; + slew_lower_threshold_pct_fall : 30; + slew_lower_threshold_pct_rise : 30; + slew_upper_threshold_pct_fall : 70; + slew_upper_threshold_pct_rise : 70; + operating_conditions (PVT_0P7V_25C) { + process : 1; + temperature : 25; + voltage : 0.7; + } + default_operating_conditions : PVT_0P7V_25C; + bus_naming_style : "%s[%d]"; + type (bus_rd_out_63_0) { + base_type : array; + data_type : bit; + bit_width : 64; + bit_from : 63; + bit_to : 0; + downto : true; + } + type (bus_addr_in_4_0) { + base_type : array; + data_type : bit; + bit_width : 5; + bit_from : 4; + bit_to : 0; + downto : true; + } + type (bus_wd_in_63_0) { + base_type : array; + data_type : bit; + bit_width : 64; + bit_from : 63; + bit_to : 0; + downto : true; + } + lu_table_template (constraint_template_7x7_x1) { + variable_1 : constrained_pin_transition; + variable_2 : related_pin_transition; + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + index_2 ("0.001, 0.00144, 0.00288, 0.00576, 0.01152, 0.02304, 0.04608"); + } + lu_table_template (delay_template_7x7_x1) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + index_2 ("0.00072, 0.00144, 0.00288, 0.00576, 0.01152, 0.02304, 0.04608"); + } + lu_table_template (input_net_transition_template) { + variable_1 : input_net_transition; + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + } + lu_table_template (mpw_constraint_template_7x7_x1) { + variable_1 : constrained_pin_transition; + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + } + power_lut_template (passive_output_power_template_7x1_x1) { + variable_1 : total_output_net_capacitance; + index_1 ("0.00072, 0.00144, 0.00288, 0.00576, 0.01152, 0.02304, 0.04608"); + } + power_lut_template (passive_power_template_7x1_x1) { + variable_1 : input_transition_time; + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + } + power_lut_template (power_template_7x7_x1) { + variable_1 : input_transition_time; + variable_2 : total_output_net_capacitance; + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + index_2 ("0.00072, 0.00144, 0.00288, 0.00576, 0.01152, 0.02304, 0.04608"); + } + cell (sdq_17x64) { + area : 0; + cell_leakage_power : 0; + dont_use : true; + interface_timing : true; + pg_pin (VDD) { + direction : inout; + pg_type : primary_power; + voltage_name : "VDD"; + } + pg_pin (VSS) { + direction : inout; + pg_type : primary_ground; + voltage_name : "VSS"; + } + pin (clk) { + clock : true; + direction : input; + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.04608; + capacitance : 0.00566251; + rise_capacitance : 0.00566251; + rise_capacitance_range (0.00466588, 0.00566251); + fall_capacitance : 0.00564129; + fall_capacitance_range (0.00469789, 0.00564129); + timing () { + related_pin : "clk"; + timing_type : min_pulse_width; + rise_constraint (mpw_constraint_template_7x7_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0.00422393, 0.0048147, 0.00574119, 0.00739732, 0.00965464, 0.0122747, 0.0153581" \ + ); + } + fall_constraint (mpw_constraint_template_7x7_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0.00425459, 0.00516788, 0.00688609, 0.00958839, 0.0137206, 0.0208117, 0.0328713" \ + ); + } + } + timing () { + related_pin : "clk"; + timing_type : minimum_period; + rise_constraint (mpw_constraint_template_7x7_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_constraint (mpw_constraint_template_7x7_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + } + internal_power () { + when : "we_in"; + related_pg_pin : VDD; + rise_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0.186927, 0.186927, 0.186927, 0.186927, 0.186927, 0.186927, 0.186927" \ + ); + } + } + internal_power () { + when : "we_in"; + related_pg_pin : VSS; + rise_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0.132678, 0.132678, 0.132678, 0.132678, 0.132678, 0.132678, 0.132678" \ + ); + } + } + internal_power () { + when : "!we_in"; + related_pg_pin : VDD; + rise_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "1.44236, 1.44236, 1.44236, 1.44236, 1.44236, 1.44236, 1.44236" \ + ); + } + fall_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0.373495, 0.373495, 0.373495, 0.373495, 0.373495, 0.373495, 0.373495" \ + ); + } + } + internal_power () { + when : "!we_in"; + related_pg_pin : VSS; + rise_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "2.11495, 2.11495, 2.11495, 2.11495, 2.11495, 2.11495, 2.11495" \ + ); + } + fall_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0.360267, 0.360267, 0.360267, 0.360267, 0.360267, 0.360267, 0.360267" \ + ); + } + } + } + bus (wd_in) { + bus_type : bus_wd_in_63_0; + direction : input; + pin (wd_in[63]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[62]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[61]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[60]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[59]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[58]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[57]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[56]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[55]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[54]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[53]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[52]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[51]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[50]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[49]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[48]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[47]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[46]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[45]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[44]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[43]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[42]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[41]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[40]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[39]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[38]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[37]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[36]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[35]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[34]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[33]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[32]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[31]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[30]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[29]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[28]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[27]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[26]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[25]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[24]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[23]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[22]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[21]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[20]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[19]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[18]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[17]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[16]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[15]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[14]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[13]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[12]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[11]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[10]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[9]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[8]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[7]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[6]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[5]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[4]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[3]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[2]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[1]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (wd_in[0]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + timing () { + related_pin : "clk"; + timing_type : hold_rising; + rise_constraint (constraint_template_7x7_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + index_2 ("0.001, 0.00144, 0.00288, 0.00576, 0.01152, 0.02304, 0.04608"); + values ( \ + "0.0210602, 0.0211955, 0.0215259, 0.0222146, 0.0234972, 0.0253227, 0.0272651", \ + "0.0200509, 0.0201875, 0.0205179, 0.0212067, 0.0224832, 0.0243148, 0.0262511", \ + "0.0182013, 0.0183379, 0.0186683, 0.0193571, 0.020633, 0.0224651, 0.0243977", \ + "0.0153871, 0.0155227, 0.0158531, 0.0165419, 0.0178241, 0.01965, 0.021592", \ + "0.0115576, 0.0116941, 0.0120246, 0.0127133, 0.0139893, 0.0158214, 0.0176936", \ + "0.00668419, 0.00682077, 0.00715121, 0.00783996, 0.00911593, 0.010948, 0.0127832", \ + "0.00151536, 0.00165194, 0.00198237, 0.00267112, 0.0039471, 0.00577921, 0.00761436" \ + ); + } + fall_constraint (constraint_template_7x7_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + index_2 ("0.001, 0.00144, 0.00288, 0.00576, 0.01152, 0.02304, 0.04608"); + values ( \ + "0.0192692, 0.0193941, 0.0196972, 0.020417, 0.0216834, 0.0235071, 0.0253749", \ + "0.0180984, 0.0182233, 0.0185265, 0.0192463, 0.0205127, 0.0223364, 0.0242042", \ + "0.0159479, 0.0160728, 0.016376, 0.0170958, 0.0183622, 0.0201858, 0.0220536", \ + "0.0125236, 0.0126485, 0.0129516, 0.0136715, 0.0149379, 0.0167615, 0.0186293", \ + "0.00765554, 0.00778043, 0.0080836, 0.00880341, 0.0100698, 0.0118935, 0.0137613", \ + "0.000632663, 0.000757555, 0.00106073, 0.00178053, 0.00304693, 0.00487059, 0.00673839", \ + "-0.00936694, -0.00924205, -0.00893888, -0.00821907, -0.00695267, -0.00512901, -0.00326121" \ + ); + } + } + timing () { + related_pin : "clk"; + timing_type : setup_rising; + rise_constraint (constraint_template_7x7_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + index_2 ("0.001, 0.00144, 0.00288, 0.00576, 0.01152, 0.02304, 0.04608"); + values ( \ + "-0.00623806, -0.00630952, -0.00644446, -0.00729797, -0.00846323, -0.010353, -0.0124091", \ + "-0.00522084, -0.0052923, -0.0054407, -0.00629421, -0.00745947, -0.00934921, -0.0113919", \ + "-0.00329589, -0.00336735, -0.00352074, -0.00437301, -0.00553952, -0.00742926, -0.00946696", \ + "-0.000288842, -0.0003603, -0.000494315, -0.00134783, -0.00251309, -0.00440283, -0.00645991", \ + "0.00398833, 0.00391688, 0.0037592, 0.00291122, 0.00174043, -0.000149314, -0.00218274", \ + "0.00969183, 0.00962038, 0.00940639, 0.00861472, 0.00738761, 0.00549787, 0.00352076", \ + "0.0168676, 0.0167962, 0.0166378, 0.0157905, 0.014619, 0.0127292, 0.0106965" \ + ); + } + fall_constraint (constraint_template_7x7_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + index_2 ("0.001, 0.00144, 0.00288, 0.00576, 0.01152, 0.02304, 0.04608"); + values ( \ + "-0.00424381, -0.00436786, -0.00438919, -0.00523762, -0.00641281, -0.00830491, -0.0102437", \ + "-0.0030952, -0.00312271, -0.00324058, -0.00408901, -0.0052164, -0.0071563, -0.00909513", \ + "-0.00088623, -0.000939231, -0.00103161, -0.00188005, -0.00303292, -0.00494733, -0.00688617", \ + "0.00278752, 0.00269871, 0.00264214, 0.0017937, 0.000618518, -0.00127358, -0.00321242", \ + "0.00819828, 0.00807423, 0.0080529, 0.00720447, 0.00602928, 0.00413718, 0.00219835", \ + "0.0161645, 0.0160405, 0.0160191, 0.0151707, 0.0139955, 0.0121034, 0.0101646", \ + "0.0272868, 0.0272879, 0.027077, 0.0262577, 0.0251942, 0.0231613, 0.0212225" \ + ); + } + } + internal_power () { + related_pg_pin : VDD; + rise_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + fall_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "3.7561e-05, 3.7561e-05, 3.7561e-05, 3.7561e-05, 3.7561e-05, 3.7561e-05, 3.7561e-05" \ + ); + } + } + internal_power () { + related_pg_pin : VSS; + rise_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "3.40917e-05, 3.40917e-05, 3.40917e-05, 3.40917e-05, 3.40917e-05, 3.40917e-05, 3.40917e-05" \ + ); + } + fall_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0, 0, 0, 0, 0, 0, 0" \ + ); + } + } + } + pin (ce_in) { + direction : input; + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + timing () { + related_pin : "clk"; + timing_type : hold_rising; + rise_constraint (constraint_template_7x7_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + index_2 ("0.001, 0.00144, 0.00288, 0.00576, 0.01152, 0.02304, 0.04608"); + values ( \ + "0.00641295, 0.00651685, 0.00685905, 0.0076929, 0.00919421, 0.0113985, 0.0143977", \ + "0.0064176, 0.0065215, 0.0068637, 0.00769755, 0.00919887, 0.0114032, 0.0144023", \ + "0.00641486, 0.00651876, 0.00686096, 0.00769481, 0.00919613, 0.0114005, 0.0143996", \ + "0.00642068, 0.00652458, 0.00686677, 0.00770062, 0.00920194, 0.0114063, 0.0144054", \ + "0.00641605, 0.00651995, 0.00686214, 0.00769599, 0.00919731, 0.0114016, 0.0144008", \ + "0.00641969, 0.00652359, 0.00686579, 0.00769964, 0.00920096, 0.0114053, 0.0144044", \ + "0.00641638, 0.00652028, 0.00686248, 0.00769633, 0.00919765, 0.011402, 0.0144011" \ + ); + } + fall_constraint (constraint_template_7x7_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + index_2 ("0.001, 0.00144, 0.00288, 0.00576, 0.01152, 0.02304, 0.04608"); + values ( \ + "0.00563349, 0.00575263, 0.00615206, 0.0069749, 0.00860909, 0.01095, 0.0141786", \ + "0.00562924, 0.00574838, 0.00614781, 0.00697065, 0.00860484, 0.0109457, 0.0141744", \ + "0.0056337, 0.00575284, 0.00615226, 0.00697511, 0.00860929, 0.0109502, 0.0141788", \ + "0.00562875, 0.00574789, 0.00614731, 0.00697016, 0.00860434, 0.0109452, 0.0141739", \ + "0.00562748, 0.00574662, 0.00614604, 0.00696889, 0.00860307, 0.0109439, 0.0141726", \ + "0.00562871, 0.00574785, 0.00614727, 0.00697012, 0.0086043, 0.0109452, 0.0141738", \ + "0.00563394, 0.00575308, 0.0061525, 0.00697535, 0.00860953, 0.0109504, 0.0141791" \ + ); + } + } + timing () { + related_pin : "clk"; + timing_type : setup_rising; + rise_constraint (constraint_template_7x7_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + index_2 ("0.001, 0.00144, 0.00288, 0.00576, 0.01152, 0.02304, 0.04608"); + values ( \ + "0, 0, 0, 0, 0, 0, 0", \ + "0, 0, 0, 0, 0, 0, 0", \ + "0, 0, 0, 0, 0, 0, 0", \ + "0, 0, 0, 0.0321671, 0.0321714, 0.0321648, 0.0321698", \ + "0, 0, 0, 0.0372257, 0.03723, 0.0372235, 0.0372284", \ + "0, 0, 0, 0.0426341, 0.0426384, 0.0426318, 0.0426368", \ + "0, 0, 0, 0.0493822, 0.0493865, 0.0493799, 0.0493849" \ + ); + } + fall_constraint (constraint_template_7x7_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + index_2 ("0.001, 0.00144, 0.00288, 0.00576, 0.01152, 0.02304, 0.04608"); + values ( \ + "0.0393436, 0.0393389, 0.0393371, 0.0393388, 0.0393431, 0.0393368, 0.0393413", \ + "0.0397967, 0.039792, 0.0397902, 0.0397919, 0.0397962, 0.0397898, 0.0397944", \ + "0.0412523, 0.0412475, 0.0412458, 0.0412474, 0.0412518, 0.0412454, 0.04125", \ + "0.0446211, 0.0446164, 0.0446146, 0.0446163, 0.0446206, 0.0446143, 0.0446188", \ + "0.0496734, 0.0496686, 0.0496669, 0.0496685, 0.0496728, 0.0496665, 0.0496711", \ + "0.057134, 0.0571292, 0.0571275, 0.0571291, 0.0571334, 0.0571271, 0.0571317", \ + "0.0678901, 0.0678854, 0.0678836, 0.0678853, 0.0678896, 0.0678833, 0.0678878" \ + ); + } + } + internal_power () { + related_pg_pin : VDD; + rise_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0.0069561, 0.0069561, 0.0069561, 0.0069561, 0.0069561, 0.0069561, 0.0069561" \ + ); + } + fall_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0.00808243, 0.00808243, 0.00808243, 0.00808243, 0.00808243, 0.00808243, 0.00808243" \ + ); + } + } + internal_power () { + related_pg_pin : VSS; + rise_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0.00990845, 0.00990845, 0.00990845, 0.00990845, 0.00990845, 0.00990845, 0.00990845" \ + ); + } + fall_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0.0076021, 0.0076021, 0.0076021, 0.0076021, 0.0076021, 0.0076021, 0.0076021" \ + ); + } + } + } + pin (we_in) { + direction : input; + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + timing () { + related_pin : "clk"; + timing_type : hold_rising; + rise_constraint (constraint_template_7x7_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + index_2 ("0.001, 0.00144, 0.00288, 0.00576, 0.01152, 0.02304, 0.04608"); + values ( \ + "0.00641435, 0.00646868, 0.00689118, 0.00769399, 0.00910335, 0.0113997, 0.0143991", \ + "0.0064136, 0.00646792, 0.00689043, 0.00769324, 0.0091026, 0.0113989, 0.0143984", \ + "0.0064122, 0.00646652, 0.00688902, 0.00769184, 0.0091012, 0.0113975, 0.014397", \ + "0.00641628, 0.0064706, 0.00689311, 0.00769592, 0.00910528, 0.0114016, 0.0144011", \ + "0.00641686, 0.00647119, 0.00689369, 0.00769651, 0.00910586, 0.0114022, 0.0144017", \ + "0.00641631, 0.00647064, 0.00689314, 0.00769595, 0.00910531, 0.0114016, 0.0144011", \ + "0.00641242, 0.00646675, 0.00688925, 0.00769206, 0.00910142, 0.0113977, 0.0143972" \ + ); + } + fall_constraint (constraint_template_7x7_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + index_2 ("0.001, 0.00144, 0.00288, 0.00576, 0.01152, 0.02304, 0.04608"); + values ( \ + "0.00563278, 0.00575874, 0.00615272, 0.00697588, 0.00861261, 0.0109511, 0.0141802", \ + "0.00562704, 0.00575299, 0.00614698, 0.00697014, 0.00860687, 0.0109453, 0.0141745", \ + "0.00563276, 0.00575871, 0.0061527, 0.00697586, 0.00861259, 0.0109511, 0.0141802", \ + "0.00563163, 0.00575759, 0.00615158, 0.00697474, 0.00861146, 0.0109499, 0.0141791", \ + "0.00563396, 0.00575991, 0.0061539, 0.00697706, 0.00861378, 0.0109523, 0.0141814", \ + "0.00563228, 0.00575823, 0.00615222, 0.00697538, 0.00861211, 0.0109506, 0.0141797", \ + "0.00563373, 0.00575968, 0.00615367, 0.00697683, 0.00861356, 0.010952, 0.0141812" \ + ); + } + } + timing () { + related_pin : "clk"; + timing_type : setup_rising; + rise_constraint (constraint_template_7x7_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + index_2 ("0.001, 0.00144, 0.00288, 0.00576, 0.01152, 0.02304, 0.04608"); + values ( \ + "0.0112791, 0.0112803, 0.0112814, 0.0112796, 0.0112829, 0.0112763, 0.0112807", \ + "0.0121447, 0.0121459, 0.012147, 0.0121451, 0.0121484, 0.0121418, 0.0121463", \ + "0.013946, 0.0139472, 0.0139483, 0.0139465, 0.0139498, 0.0139431, 0.0139476", \ + "0.0166916, 0.0166928, 0.0166939, 0.016692, 0.0166953, 0.0166887, 0.0166931", \ + "0.0206937, 0.0206949, 0.020696, 0.0206942, 0.0206975, 0.0206909, 0.0206953", \ + "0.0259203, 0.0259215, 0.0259226, 0.0259208, 0.0259241, 0.0259175, 0.0259219", \ + "0.0319974, 0.0319986, 0.0319997, 0.0319979, 0.0320012, 0.0319946, 0.031999" \ + ); + } + fall_constraint (constraint_template_7x7_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + index_2 ("0.001, 0.00144, 0.00288, 0.00576, 0.01152, 0.02304, 0.04608"); + values ( \ + "0.014076, 0.0140772, 0.0140782, 0.0140749, 0.0140745, 0.0140755, 0.0140774", \ + "0.0151448, 0.015146, 0.015147, 0.0151437, 0.0151432, 0.0151443, 0.0151462", \ + "0.0172826, 0.0172838, 0.0172848, 0.0172815, 0.017281, 0.0172821, 0.017284", \ + "0.0209582, 0.0209593, 0.0209604, 0.020957, 0.0209566, 0.0209576, 0.0209596", \ + "0.0262313, 0.0262324, 0.0262335, 0.0262301, 0.0262297, 0.0262308, 0.0262327", \ + "0.0340026, 0.0340037, 0.0340048, 0.0340014, 0.034001, 0.0340021, 0.034004", \ + "0.0448327, 0.0448338, 0.0448349, 0.0448315, 0.0448311, 0.0448322, 0.0448341" \ + ); + } + } + internal_power () { + related_pg_pin : VDD; + rise_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0.000290756, 0.000290756, 0.000290756, 0.000290756, 0.000290756, 0.000290756, 0.000290756" \ + ); + } + fall_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0.000338406, 0.000338406, 0.000338406, 0.000338406, 0.000338406, 0.000338406, 0.000338406" \ + ); + } + } + internal_power () { + related_pg_pin : VSS; + rise_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0.000430543, 0.000430543, 0.000430543, 0.000430543, 0.000430543, 0.000430543, 0.000430543" \ + ); + } + fall_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0.000209809, 0.000209809, 0.000209809, 0.000209809, 0.000209809, 0.000209809, 0.000209809" \ + ); + } + } + } + bus (addr_in) { + bus_type : bus_addr_in_4_0; + direction : input; + pin (addr_in[4]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (addr_in[3]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (addr_in[2]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (addr_in[1]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + pin (addr_in[0]) { + related_ground_pin : VSS; + related_power_pin : VDD; + max_transition : 0.32; + capacitance : 0.000318915; + rise_capacitance : 0.000318915; + rise_capacitance_range (0.000277789, 0.000318915); + fall_capacitance : 0.00031886; + fall_capacitance_range (0.000272947, 0.00031886); + } + timing () { + related_pin : "clk"; + timing_type : hold_rising; + rise_constraint (constraint_template_7x7_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + index_2 ("0.001, 0.00144, 0.00288, 0.00576, 0.01152, 0.02304, 0.04608"); + values ( \ + "0.00639999, 0.00652306, 0.00689893, 0.00768751, 0.00920766, 0.0114214, 0.0143699", \ + "0.00639816, 0.00652123, 0.0068971, 0.00768758, 0.00920583, 0.0114214, 0.01437", \ + "0.00639717, 0.00652024, 0.00689612, 0.00768555, 0.00920485, 0.0114194, 0.014368", \ + "0.00639932, 0.00652239, 0.00689827, 0.00768685, 0.009207, 0.0114207, 0.0143693", \ + "0.006393, 0.00651771, 0.00689194, 0.00768602, 0.00920067, 0.0114199, 0.0143685", \ + "0.00639495, 0.00651802, 0.00689389, 0.00768578, 0.00920263, 0.0114196, 0.0143682", \ + "0.00639953, 0.0065226, 0.00689847, 0.00768648, 0.00920721, 0.0114157, 0.0143642" \ + ); + } + fall_constraint (constraint_template_7x7_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + index_2 ("0.001, 0.00144, 0.00288, 0.00576, 0.01152, 0.02304, 0.04608"); + values ( \ + "0.00562845, 0.00575319, 0.00614979, 0.00697184, 0.00859671, 0.0109522, 0.0141734", \ + "0.00563023, 0.00575497, 0.00615156, 0.00697361, 0.00859849, 0.0109539, 0.0141752", \ + "0.00563123, 0.00575597, 0.00615256, 0.00697461, 0.00859948, 0.0109549, 0.0141762", \ + "0.00563062, 0.00575536, 0.00615196, 0.006974, 0.00859888, 0.0109543, 0.0141756", \ + "0.00562576, 0.0057505, 0.00614709, 0.00696914, 0.00859402, 0.0109495, 0.0141707", \ + "0.00562643, 0.00575117, 0.00614777, 0.00696981, 0.00859469, 0.0109501, 0.0141714", \ + "0.00562759, 0.00575233, 0.00614893, 0.00697097, 0.00859585, 0.0109513, 0.0141725" \ + ); + } + } + timing () { + related_pin : "clk"; + timing_type : setup_rising; + rise_constraint (constraint_template_7x7_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + index_2 ("0.001, 0.00144, 0.00288, 0.00576, 0.01152, 0.02304, 0.04608"); + values ( \ + "0.0477869, 0.047692, 0.047371, 0.046683, 0.0454258, 0.0454251, 0.0454201", \ + "0.0486908, 0.0485958, 0.0482748, 0.0475869, 0.046227, 0.0457285, 0.0457235", \ + "0.0504688, 0.0503739, 0.0500528, 0.0493649, 0.0480051, 0.0470487, 0.0470437", \ + "0.0532756, 0.0531806, 0.0528596, 0.0521717, 0.0508118, 0.0499592, 0.0499542", \ + "0.0573723, 0.0572773, 0.0569563, 0.0562684, 0.0549085, 0.0539666, 0.0539617", \ + "0.0629215, 0.0628265, 0.0625055, 0.0618176, 0.0604578, 0.0592055, 0.0592005", \ + "0.069743, 0.069648, 0.069327, 0.0686391, 0.0672793, 0.06595, 0.065945" \ + ); + } + fall_constraint (constraint_template_7x7_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + index_2 ("0.001, 0.00144, 0.00288, 0.00576, 0.01152, 0.02304, 0.04608"); + values ( \ + "0.0474327, 0.047433, 0.0474326, 0.047434, 0.0474398, 0.0474399, 0.0474318", \ + "0.0482648, 0.0482651, 0.0482647, 0.048266, 0.0482719, 0.0482719, 0.0482639", \ + "0.0501257, 0.050126, 0.0501256, 0.050127, 0.0501328, 0.0501329, 0.0501248", \ + "0.0536384, 0.0536388, 0.0536383, 0.0536397, 0.0536455, 0.0536456, 0.0536376", \ + "0.0588398, 0.0588402, 0.0588397, 0.0588411, 0.0588469, 0.058847, 0.058839", \ + "0.0664326, 0.066433, 0.0664325, 0.0664339, 0.0664397, 0.0664398, 0.0664318", \ + "0.0760889, 0.0760892, 0.0760888, 0.0760902, 0.076096, 0.0760961, 0.076088" \ + ); + } + } + internal_power () { + related_pg_pin : VDD; + rise_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0.00471622, 0.00471622, 0.00471622, 0.00471622, 0.00471622, 0.00471622, 0.00471622" \ + ); + } + fall_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0.00620875, 0.00620875, 0.00620875, 0.00620875, 0.00620875, 0.00620875, 0.00620875" \ + ); + } + } + internal_power () { + related_pg_pin : VSS; + rise_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0.00490932, 0.00490932, 0.00490932, 0.00490932, 0.00490932, 0.00490932, 0.00490932" \ + ); + } + fall_power (passive_power_template_7x1_x1) { + index_1 ("0.005, 0.01, 0.02, 0.04, 0.08, 0.16, 0.32"); + values ( \ + "0.00604381, 0.00604381, 0.00604381, 0.00604381, 0.00604381, 0.00604381, 0.00604381" \ + ); + } + } + } + bus (rd_out) { + bus_type : bus_rd_out_63_0; + direction : output; + pin (rd_out[63]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[62]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[61]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[60]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[59]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[58]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[57]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[56]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[55]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[54]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[53]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[52]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[51]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[50]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[49]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[48]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[47]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[46]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[45]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[44]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[43]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[42]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[41]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[40]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[39]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[38]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[37]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[36]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[35]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[34]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[33]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[32]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[31]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[30]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[29]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[28]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[27]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[26]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[25]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[24]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[23]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[22]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[21]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[20]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[19]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[18]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[17]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[16]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[15]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[14]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[13]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[12]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[11]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[10]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[9]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[8]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[7]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[6]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[5]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[4]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[3]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[2]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[1]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + pin (rd_out[0]) { + related_ground_pin : VSS; + related_power_pin : VDD; + } + max_capacitance : 368.64; + output_voltage : default_VDD_VSS_output; + timing () { + related_pin : "clk"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_7x7_x1) { + index_1 ("5, 10, 20, 40, 80, 160, 320"); + index_2 ("5.76, 11.52, 23.04, 46.08, 92.16, 184.32, 368.64"); + values ( \ + "78.9236, 85.6487, 98.3056, 123.3545, 173.0190, 272.3320, 470.9740", \ + "80.4253, 87.1664, 99.8430, 124.9154, 174.6280, 274.3100, 473.1290", \ + "83.4952, 90.2340, 102.9467, 127.9445, 177.6250, 276.9640, 475.7390", \ + "89.4188, 96.1306, 108.8588, 133.8696, 183.7090, 283.0220, 481.1160", \ + "99.0377, 105.8277, 118.5880, 143.5528, 193.4470, 292.9910, 492.0340", \ + "112.7103, 119.6741, 132.3848, 157.2370, 207.0540, 306.3060, 504.9450", \ + "131.5852, 139.0667, 151.9373, 176.6550, 226.5740, 325.3730, 524.3560" \ + ); + } + rise_transition (delay_template_7x7_x1) { + index_1 ("5, 10, 20, 40, 80, 160, 320"); + index_2 ("5.76, 11.52, 23.04, 46.08, 92.16, 184.32, 368.64"); + values ( \ + "19.9604, 33.3838, 60.5592, 115.965, 227.305, 451.654, 896.404", \ + "19.9868, 33.4321, 60.754, 116.299, 227.064, 451.146, 893.703", \ + "19.9601, 33.3303, 60.7642, 116.014, 226.948, 450.389, 894.379", \ + "20.2008, 33.3092, 60.7249, 115.992, 227.706, 450.768, 893.662", \ + "21.7629, 34.4188, 61.2863, 116.073, 227.04, 451.294, 894.47", \ + "24.6994, 36.6542, 62.7539, 116.748, 228.441, 451.854, 895.913", \ + "30.1305, 41.1106, 65.7316, 118.902, 229.74, 451.604, 894.335" \ + ); + } + cell_fall (delay_template_7x7_x1) { + index_1 ("5, 10, 20, 40, 80, 160, 320"); + index_2 ("5.76, 11.52, 23.04, 46.08, 92.16, 184.32, 368.64"); + values ( \ + "81.4437, 87.1019, 97.1148, 116.1230, 153.9891, 229.0570, 378.8210", \ + "82.8062, 88.4608, 98.4772, 117.5408, 155.1090, 230.2950, 380.2270", \ + "85.8330, 91.4817, 101.5156, 120.5720, 158.3550, 233.4500, 383.0840", \ + "91.8366, 97.5050, 107.5579, 126.6378, 164.5360, 239.6580, 389.2010", \ + "102.3177, 108.0948, 118.1873, 137.2922, 174.8790, 250.0190, 400.1170", \ + "116.5743, 122.8349, 133.3237, 152.4996, 189.9830, 265.2710, 415.2340", \ + "135.0926, 142.0885, 153.1585, 172.6200, 210.2880, 284.8460, 434.7650" \ + ); + } + fall_transition (delay_template_7x7_x1) { + index_1 ("5, 10, 20, 40, 80, 160, 320"); + index_2 ("5.76, 11.52, 23.04, 46.08, 92.16, 184.32, 368.64"); + values ( \ + "17.1281, 26.551, 45.5376, 84.0561, 162.072, 320.663, 633.815", \ + "17.1533, 26.5502, 45.3372, 84.0753, 162.263, 319.207, 635.033", \ + "17.134, 26.5695, 45.4274, 83.9203, 162.254, 320.686, 635.776", \ + "17.2832, 26.6588, 45.5933, 84.0645, 162.268, 320.445, 634.845", \ + "18.9647, 27.841, 46.3678, 84.1981, 162.376, 319.217, 634.338", \ + "22.8999, 31.3298, 49.1466, 86.045, 163.081, 320.9, 635.77", \ + "28.8432, 36.8596, 53.3885, 89.3229, 165.016, 321.344, 634.159" \ + ); + } + } + internal_power () { + related_pin : "clk"; + related_pg_pin : VDD; + rise_power (power_template_7x7_x1) { + index_1 ("5, 10, 20, 40, 80, 160, 320"); + index_2 ("5.76, 11.52, 23.04, 46.08, 92.16, 184.32, 368.64"); + values ( \ + "0.419708, 0.43837, 0.439502, 0.456328, 0.462601, 0.463865, 0.457025", \ + "0.413705, 0.435363, 0.437017, 0.459371, 0.456921, 0.459801, 0.429526", \ + "0.407494, 0.427198, 0.437272, 0.440717, 0.44813, 0.454887, 0.424958", \ + "0.393602, 0.404071, 0.419689, 0.442021, 0.451188, 0.453407, 0.415949", \ + "0.395126, 0.404235, 0.427665, 0.432703, 0.440888, 0.453438, 0.446126", \ + "0.422525, 0.427163, 0.436683, 0.434597, 0.45837, 0.467771, 0.460774", \ + "0.508681, 0.498589, 0.504745, 0.51025, 0.505478, 0.514044, 0.488179" \ + ); + } + fall_power (power_template_7x7_x1) { + index_1 ("5, 10, 20, 40, 80, 160, 320"); + index_2 ("5.76, 11.52, 23.04, 46.08, 92.16, 184.32, 368.64"); + values ( \ + "0.690286, 0.704812, 0.715019, 0.720713, 0.723619, 0.725052, 0.72546", \ + "0.682689, 0.696983, 0.707383, 0.714666, 0.721584, 0.723686, 0.719262", \ + "0.670468, 0.687785, 0.702035, 0.710386, 0.712944, 0.714897, 0.71629", \ + "0.665285, 0.679743, 0.692552, 0.702161, 0.708305, 0.71112, 0.713348", \ + "0.671107, 0.682283, 0.695975, 0.70649, 0.714134, 0.717882, 0.720057", \ + "0.704833, 0.709421, 0.719324, 0.729487, 0.739263, 0.74488, 0.747507", \ + "0.79301, 0.786748, 0.7902, 0.798776, 0.808398, 0.814909, 0.819131" \ + ); + } + } + internal_power () { + related_pin : "clk"; + related_pg_pin : VSS; + rise_power (power_template_7x7_x1) { + index_1 ("5, 10, 20, 40, 80, 160, 320"); + index_2 ("5.76, 11.52, 23.04, 46.08, 92.16, 184.32, 368.64"); + values ( \ + "0.641731, 0.656346, 0.667234, 0.673323, 0.676314, 0.677674, 0.678152", \ + "0.635139, 0.663334, 0.662348, 0.667734, 0.671748, 0.673499, 0.673353", \ + "0.625364, 0.638522, 0.654597, 0.66211, 0.667135, 0.669701, 0.668333", \ + "0.614131, 0.635431, 0.640128, 0.651156, 0.656489, 0.662299, 0.664463", \ + "0.61731, 0.629573, 0.639399, 0.653491, 0.661618, 0.665793, 0.667713", \ + "0.642826, 0.648685, 0.658225, 0.670882, 0.681396, 0.68924, 0.690294", \ + "0.725965, 0.721777, 0.725352, 0.734271, 0.744433, 0.753016, 0.758334" \ + ); + } + fall_power (power_template_7x7_x1) { + index_1 ("5, 10, 20, 40, 80, 160, 320"); + index_2 ("5.76, 11.52, 23.04, 46.08, 92.16, 184.32, 368.64"); + values ( \ + "0.46955, 0.492262, 0.492273, 0.507652, 0.497101, 0.508131, 0.483094", \ + "0.465681, 0.478836, 0.485372, 0.50265, 0.51074, 0.490554, 0.502813", \ + "0.453834, 0.473707, 0.487939, 0.501866, 0.488684, 0.503406, 0.49415", \ + "0.449365, 0.463047, 0.471782, 0.489691, 0.483159, 0.496067, 0.489488", \ + "0.453889, 0.466515, 0.47074, 0.484707, 0.512381, 0.484506, 0.500513", \ + "0.491383, 0.495113, 0.500003, 0.506757, 0.520096, 0.533993, 0.520673", \ + "0.573595, 0.565057, 0.567612, 0.572227, 0.587985, 0.58244, 0.559324" \ + ); + } + } + } + } +} diff --git a/sram/fakeram/sdq_17x64.sv b/sram/fakeram/sdq_17x64.sv new file mode 100644 index 0000000..c74cd4a --- /dev/null +++ b/sram/fakeram/sdq_17x64.sv @@ -0,0 +1,36 @@ +module sdq_17x64 +( + rd_out, + addr_in, + we_in, + wd_in, + clk, + ce_in +); + parameter BITS = 64; + parameter WORD_DEPTH = 17; + parameter ADDR_WIDTH = 5; + parameter corrupt_mem_on_X_p = 1; + + output reg [BITS-1:0] rd_out; + input [ADDR_WIDTH-1:0] addr_in; + input we_in; + input [BITS-1:0] wd_in; + input clk; + input ce_in; + + reg [BITS-1:0] mem [0:WORD_DEPTH-1]; + + integer j; + + always @(posedge clk) + begin + if (we_in) + begin + mem[addr_in] <= wd_in; + end + // read + rd_out <= mem[addr_in]; + end + +endmodule diff --git a/sram/fakeram/top.v b/sram/fakeram/top.v new file mode 100644 index 0000000..24b2eaf --- /dev/null +++ b/sram/fakeram/top.v @@ -0,0 +1,17 @@ +module top ( + input [16:0] addr_in, + input we_in, + input [63:0] wd_in, + output [63:0] rd_out, + input clk, + input ce_in + ); + sdq_17x64 u_sdq_17x64 ( + .rd_out(rd_out), + .addr_in(addr_in), + .we_in(we_in), + .wd_in(wd_in), + .clk(clk), + .ce_in(ce_in) + ); +endmodule diff --git a/sram/megaboom/constraints-sram.sdc b/sram/megaboom/constraints-sram.sdc new file mode 100644 index 0000000..83e7b08 --- /dev/null +++ b/sram/megaboom/constraints-sram.sdc @@ -0,0 +1,11 @@ +set clk_name R0_clk +set clk_port_name R0_clk +set clk_period 400 + +if { [llength [all_registers]] > 0} { + source $env(PLATFORM_DIR)/constraints.sdc +} else { + puts "The design is gutted when mocking floorplan" +} + +create_clock -period $clk_period -name W0_clk [get_ports W0_clk] diff --git a/sram/megaboom/constraints-top.sdc b/sram/megaboom/constraints-top.sdc new file mode 100644 index 0000000..9d29e64 --- /dev/null +++ b/sram/megaboom/constraints-top.sdc @@ -0,0 +1,13 @@ +set clk_name clock +set clk_port_name clock +set clk_period 50 + +set in2reg_max 160 +set reg2out_max 50 +set in2out_max 350 + +if { [llength [all_registers]] > 0} { + source $env(PLATFORM_DIR)/constraints.sdc +} else { + puts "The design is gutted when mocking floorplan" +} diff --git a/sram/megaboom/sdq_17x64.sv b/sram/megaboom/sdq_17x64.sv new file mode 100644 index 0000000..79aad37 --- /dev/null +++ b/sram/megaboom/sdq_17x64.sv @@ -0,0 +1,18 @@ +module sdq_17x64( + input [4:0] R0_addr, + input R0_en, + R0_clk, + output [63:0] R0_data, + input [4:0] W0_addr, + input W0_en, + W0_clk, + input [63:0] W0_data +); + + reg [63:0] Memory[0:16]; + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + end // always @(posedge) + assign R0_data = R0_en ? Memory[R0_addr] : 64'bx; +endmodule diff --git a/sram/megaboom/top.v b/sram/megaboom/top.v new file mode 100644 index 0000000..e69a5fb --- /dev/null +++ b/sram/megaboom/top.v @@ -0,0 +1,21 @@ +module top( + input clock, + input [4:0] R0_addr, + input R0_en, + output [63:0] R0_data, + input [4:0] W0_addr, + input W0_en, + input [63:0] W0_data +); + sdq_17x64 u_sdq_17x64 ( + .R0_addr(R0_addr), + .R0_en(R0_en), + .R0_clk(clock), // Use the same clock for read + .R0_data(R0_data), + .W0_addr(W0_addr), + .W0_en(W0_en), + .W0_clk(clock), // Use the same clock for write + .W0_data(W0_data) + ); + +endmodule