Clock tree shows weird

[Blebowski]

Hello,
I am playing with OpenROAD again after some time, and I am running into some problems with clock tree viewer.
I am trying to go step-by-step from the manual (not using ORFS), so that I learn how does the tool works.

I do something like:

define_corners min typ max
read_lef -tech <tech_lef>
read_lef -library <std_cells_lef>
read_liberty -corner min <min_corner.lib>
read_liberty -corner max <max_corner.lib>
read_liberty -corner typ <typ_corner.lib>
read_verilog <netlist_with_no_macros.v>
link_design ts_sha_256_top

set_wire_rc -resistance 0.002464 -capacitance 0.000171
create_clock -period 12.5 [get_ports clk]
initialize_floorplan -die_area {0 0 190 190} -core_area {10 10 180 180} -site <SITE_NAME>
make_tracks
place_pins -ver_layers ME2 -hor_layers ME3 -random -min_distance_in_tracks

add_global_connection -net VDD -pin_pattern {^VDD$} -power
add_global_connection -net VSS -pin_pattern {^VSS$} -ground

set_voltage_domain -name VDD_1V2 -power VDD -ground VSS

define_pdn_grid -name "Core"


add_pdn_stripe -layer ME1 -followpins -width 0.2

add_pdn_ring -grid "Core" -layers {ME4 ME5} -widths 4.5 -spacings 1.0 -core_offsets {0 0} -add_connect

add_pdn_stripe -layer ME4 -width 1.5 -pitch 20 -offset 0 -extend_to_core_ring
add_pdn_stripe -layer ME5 -width 1.5 -pitch 20 -offset 0 -extend_to_core_ring

add_pdn_connect -layers {ME1 ME4}
add_pdn_connect -layers {ME1 ME5}

pdngen

global_placement -routability_driven -timing_driven

puts "Clock tree synthesis"
clock_tree_synthesis -buf_list CKBUFM4UM

puts "Detailed placement"
detailed_placement

After running this script, I click on "Update" in Clock tree viewer. However, the CTS viewer shows only vertical grey rectangle
on its left side. Using "Fit" does not help/work. Can someone please advice me on what I am doing wrong ?