Compiling First New Design

[JeffRocchio]

If this is the wrong place to ask this question, please advise.

Trying to get OpenLane running for my 1st attempt at a new design, but failing. (And I should probably note that I'm a software guy with a hardware interest, so very, very inexperienced in all this at this point.)

For the 'new design' I am simply trying to replicate the pre-existing inverter.v demo design so that I have a proven design to work with. Therefore, simply trying to prove that I can make a new design structure and compile it. But I can't seem to do even this simple thing. So any help I can get getting through this very 1st stage would be greatly appreciated!

Am running on fedora linux release 35. Installed OpenLane just fine and ran the test script just fine. Am now trying to just prove I can run my own designs.

SO - here is my sequence of actions leading to failure (I have tried about a half-dozen variations, all with the same failure mode - the below is my, shall we say, 'baseline' failure sequence):

First - prove I can compile a pre-existing demo design. In docker I execute:
OpenLane Container (41ed003):/openlane$ ./flow.tcl -design inverter
And it runs/compiles all just fine.

I initiate my own design:
./flow.tcl -design jeff_2ndTry -init_design_config -add_to_designs

Then I add a src directory and empty jeff_2ndTry.v file. So I have the following:
designs/jeff_2ndtTry
├── config.json
├── src
├─├── jeff_2ndTry.v

In my text editor I copy/paste the entire contents of designs/inverter/src/inverter.v to my designs/jeff_2ndTry/src/jeff_2ndTry.v verilog file.
In my text editor I copy/paste the entire contents of designs/inverter/config.json to my designs/jeff_2ndTry/config.json file; then edit the first and last lines of the json file to replace 'inverter' with 'jeff_2ndTry.'

Contents of designs/jeff_2ndTry/src/jeff_2ndTry.v and designs/jeff_2ndTry/config.json provided below the output error listing.

Then in docker I execute:

OpenLane Container (41ed003):/openlane$ ./flow.tcl -design jeff_2ndTry
OpenLane 41ed0036c3dc77961a34005fc7e4494881f0a07f
All rights reserved. (c) 2020-2022 Efabless Corporation and contributors.
Available under the Apache License, version 2.0. See the LICENSE file for more details.

[INFO]: Using configuration in 'designs/jeff_2ndTry/config.json'...
[INFO]: PDK Root: /home/jroc/Dropbox/projects/MakeChip/OpenLane/pdks
[INFO]: Process Design Kit: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Optimization Standard Cell Library: sky130_fd_sc_hd
[INFO]: Run Directory: /openlane/designs/jeff_2ndTry/runs/RUN_2022.10.29_19.48.05
[INFO]: Preparing LEF files for the nom corner...
[INFO]: Preparing LEF files for the min corner...
[INFO]: Preparing LEF files for the max corner...
[STEP 1]
[INFO]: Running Synthesis (log: designs/jeff_2ndTry/runs/RUN_2022.10.29_19.48.05/logs/synthesis/1-synthesis.log)...
[ERROR]: during executing: "yosys -c /openlane/scripts/yosys/synth.tcl -l /openlane/designs/jeff_2ndTry/runs/RUN_2022.10.29_19.48.05/logs/synthesis/1-synthesis.log |& tee /dev/null"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Verilog-2005 frontend: /openlane/designs/jeff_2ndTry/src/jeff_2ndTry.v
ERROR: No such module: jeff_2ndTry
child process exited abnormally

[INFO]: Saving current set of views in 'designs/jeff_2ndTry/runs/RUN_2022.10.29_19.48.05/results/final'...
[INFO]: Generating final set of reports...
[INFO]: Created manufacturability report at 'designs/jeff_2ndTry/runs/RUN_2022.10.29_19.48.05/reports/manufacturability.rpt'.
[INFO]: Created metrics report at 'designs/jeff_2ndTry/runs/RUN_2022.10.29_19.48.05/reports/metrics.csv'.
[INFO]: Saving runtime environment...
[ERROR]: Flow failed.

    while executing
"flow_fail"
    (procedure "try_catch" line 17)
    invoked from within
"try_catch $::env(SYNTH_BIN)  -c $::env(SYNTH_SCRIPT)  -l $arg_values(-log) |& tee $::env(TERMINAL_OUTPUT)"
    (procedure "run_yosys" line 38)
    invoked from within
"run_yosys -log $log"
    (procedure "run_synthesis" line 13)
    invoked from within
"[lindex $step_exe 0] [lindex $step_exe 1] "
    (procedure "run_non_interactive_mode" line 52)
    invoked from within
"run_non_interactive_mode {*}$argv"
    invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
    if { [info exists arg_values(-file)] } {
        run_file [file nor..."
    (file "./flow.tcl" line 411)
OpenLane Container (41ed003):/openlane$

designs/jeff_2ndTry/config.json

{
    "DESIGN_NAME": "jeff_2ndTry",
    "VERILOG_FILES": "dir::src/*.v",
    "CLOCK_TREE_SYNTH": false,
    "CLOCK_PORT": null,
    "PL_RANDOM_GLB_PLACEMENT": true,
    "FP_SIZING": "absolute",
    "DIE_AREA": "0 0 34.5 57.12",
    "PL_TARGET_DENSITY": 0.75,
    "FP_PDN_AUTO_ADJUST": false,
    "FP_PDN_VPITCH": 25,
    "FP_PDN_HPITCH": 25,
    "FP_PDN_VOFFSET": 5,
    "FP_PDN_HOFFSET": 5,
    "DIODE_INSERTION_STRATEGY": 3,
    "TEST_POTENTIALLY_MALICIOUS_VARIABLE": "{}{}{}{}}}}{{{\"\"\"''''",
    "TEST_EXTERNAL_GLOB": "dir::../jeff_2ndTry/src/*"
}

designs/jeff_2ndTry/src/jeff_2ndTry.v

// Jeff 2nd Try
//
// Copyright 2020 Matt Venn
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//      http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

`default_nettype none
module inverter (
    input wire in,
    output out );

    assign out = !in;

endmodule

[vijayank88]

@JeffRocchio
Your source file module name need to updated as well.

Use below format.

module jeff_2ndTry (
    input wire in,
    output out );

    assign out = !in;

endmodule

[JeffRocchio]

Right, of course! That module is going to be used/referenced throughout the remainder of the flow. Silly me. It works fine now.

(It's like creating an object in a C++ file for use elsewhere; it's the name of the object that matters, not the name of the file it's defined in).

Thanks for your help Vijayin.