Combinational design no clock

[jimbo1990]

Hi,

I was wondering if somebody could help me with a couple of problems I have with openlane.

1. Is it possible to implement a Purley combinational design without a clock. I noticed that the required variables in the config files are clk period and clk port however I don't have a clock in the design.
2. I would like to generate power reports based on switching activity of the combinational circuit. That's to say I would like to put data on the input ports and calculate estimated power consumption (without clock frequency) is this possible?.

Thank you in advance.

[vijayank88]

@jimbo1990
For clock less design you can define config.tcl in following way:

# turn off clock
set ::env(CLOCK_TREE_SYNTH) 0
set ::env(CLOCK_PORT) ""

Built-in example here: https://github.com/The-OpenROAD-Project/OpenLane/blob/master/designs/inverter/config.tcl