From abc4fafcadde66607e7aca935a6bd86d561ef8ae Mon Sep 17 00:00:00 2001 From: sai krishna pidugu <103561542+spidugu444@users.noreply.github.com> Date: Sun, 5 Feb 2023 23:53:35 +0530 Subject: [PATCH 1/7] Added riscv-arch tests in smoke-tests.sh --- cva6/regress/smoke-tests.sh | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/cva6/regress/smoke-tests.sh b/cva6/regress/smoke-tests.sh index 1e69c8e1f3..fe2770212e 100644 --- a/cva6/regress/smoke-tests.sh +++ b/cva6/regress/smoke-tests.sh @@ -18,6 +18,8 @@ source ./cva6/regress/install-cva6.sh source ./cva6/regress/install-riscv-dv.sh source ./cva6/regress/install-riscv-compliance.sh source ./cva6/regress/install-riscv-tests.sh +source ./cva6/regress/install-riscv-isa-sim.sh +source ./cva6/regress/install-riscv-arch-test.sh if ! [ -n "$DV_SIMULATORS" ]; then DV_SIMULATORS=vcs-testharness,spike @@ -27,6 +29,8 @@ cd cva6/sim/ python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml --test rv64ui-v-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS +python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml --test rv64i_m-add-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-isa-sim/arch_test_target/spike/link.ld +python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-isa-sim/arch_test_target/spike/link.ld python3 cva6.py --testlist=../tests/testlist_custom.yaml --test custom_test_template --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c\ --gcc_opts "-g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" From dd4cd4e7c28fd608713af32ffa983c08e5cd4c8a Mon Sep 17 00:00:00 2001 From: sai krishna pidugu <103561542+spidugu444@users.noreply.github.com> Date: Sun, 5 Feb 2023 23:54:49 +0530 Subject: [PATCH 2/7] Updated riscv-isa-sim.patch in install-riscv-sim.sh --- cva6/regress/install-riscv-isa-sim.sh | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/cva6/regress/install-riscv-isa-sim.sh b/cva6/regress/install-riscv-isa-sim.sh index a8fd15007a..795dce32b0 100644 --- a/cva6/regress/install-riscv-isa-sim.sh +++ b/cva6/regress/install-riscv-isa-sim.sh @@ -11,14 +11,19 @@ if ! [ -n "$RISCV_ISA_SIM" ]; then RISCV_ISA_SIM="https://github.com/riscv-software-src/riscv-isa-sim.git" RISCV_ISA_SIM_BRANCH="master" RISCV_ISA_SIM_HASH="b9fc8e4e9087a6064dfcc627efabbe3fd4bdc309" + RISCV_ISA_SIM_PATCH="../../../cva6/regress/riscv-isa-sim.patch" fi echo $RISCV_ISA_SIM echo $RISCV_ISA_SIM_BRANCH echo $RISCV_ISA_SIM_HASH +echo $RISCV_ISA_SIM_PATCH if ! [ -d cva6/tests/riscv-isa-sim ]; then git clone $RISCV_ISA_SIM -b $RISCV_ISA_SIM_BRANCH cva6/tests/riscv-isa-sim cd cva6/tests/riscv-isa-sim; git checkout $RISCV_ISA_SIM_HASH; + if [ -f "$RISCV_ISA_SIM_PATCH" ]; then + git apply $RISCV_ISA_SIM_PATCH + fi cd - fi From 19013024974ada92972160cc85b6c330aa85c9db Mon Sep 17 00:00:00 2001 From: sai krishna pidugu <103561542+spidugu444@users.noreply.github.com> Date: Sun, 5 Feb 2023 23:55:58 +0530 Subject: [PATCH 3/7] Added riscv-isa-sim.patch file used to control riscv-arch-test simulation --- cva6/regress/riscv-isa-sim.patch | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 cva6/regress/riscv-isa-sim.patch diff --git a/cva6/regress/riscv-isa-sim.patch b/cva6/regress/riscv-isa-sim.patch new file mode 100644 index 0000000000..26cc20c6be --- /dev/null +++ b/cva6/regress/riscv-isa-sim.patch @@ -0,0 +1,15 @@ +diff --git a/arch_test_target/spike/model_test.h b/arch_test_target/spike/model_test.h +index e968e43a..7628af51 100644 +--- a/arch_test_target/spike/model_test.h ++++ b/arch_test_target/spike/model_test.h +@@ -23,6 +23,7 @@ + li x1, 1; \ + write_tohost: \ + sw x1, tohost, t1; \ ++ ecall + self_loop: j self_loop; + + #define RVMODEL_BOOT +-- +2.39.0 + From 8473f7f52906cb9144fa0ef66a3aeb5827b6f4cd Mon Sep 17 00:00:00 2001 From: sai krishna pidugu <103561542+spidugu444@users.noreply.github.com> Date: Sun, 5 Feb 2023 23:57:08 +0530 Subject: [PATCH 4/7] Added testlist file for riscv-arch-test suite --- ...st_riscv-arch-test-cv64a6_imafdc_sv39.yaml | 682 +++++++++--------- 1 file changed, 361 insertions(+), 321 deletions(-) diff --git a/cva6/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml b/cva6/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml index 38d8b06aee..f2dc87e8cb 100644 --- a/cva6/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml +++ b/cva6/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml @@ -32,705 +32,745 @@ #- import: /target/rv64imc/testlist.yaml -- test: rv64im-add-01 +##I +- test: rv64i_m-add-01 iterations: 1 path_var: TESTS_PATH - path_root: ROOT_PROJECT gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/add-01.S -- test: rv64im-addi-01 +- test: rv64i_m-addi-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/addi-01.S -- test: rv64im-addiw-01 +- test: rv64i_m-addiw-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/addiw-01.S -- test: rv64im-addw-01 +- test: rv64i_m-addw-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/addw-01.S -- test: rv64im-addw-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/addw-01.S - -- test: rv64im-and-01 +- test: rv64i_m-and-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/and-01.S -- test: rv64im-andi-01 +- test: rv64i_m-andi-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/andi-01.S -- test: rv64im-auipc-01 +- test: rv64i_m-auipc-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/auipc-01.S -- test: rv64im-beq-01 +- test: rv64i_m-beq-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/beq-01.S -- test: rv64im-bge-01 +- test: rv64i_m-bge-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/bge-01.S -- test: rv64im-bgeu-01 +- test: rv64i_m-bgeu-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/bgeu-01.S -- test: rv64im-blt-01 +- test: rv64i_m-blt-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/blt-01.S -- test: rv64im-bltu-01 - iterations: 0 +- test: rv64i_m-bltu-01 + iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/bltu-01.S -- test: rv64im-bne-01 +- test: rv64i_m-bne-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/bne-01.S -- test: rv64im-fence-01 +- test: rv64i_m-fence-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/fence-01.S -- test: rv64im-jal-01 +- test: rv64i_m-jal-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/jal-01.S -- test: rv64im-jalr-01 +- test: rv64i_m-jalr-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/jalr-01.S -- test: rv64im-lb-align-01 +- test: rv64i_m-lb-align01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lb-align-01.S -- test: rv64im-lbu-align-01 +- test: rv64i_m-lbu-align01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lbu-align-01.S -- test: rv64im-ld-align-01 +- test: rv64i_m-ld-align01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/ld-align-01.S -- test: rv64im-lh-align-01 +- test: rv64i_m-lh-align01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lh-align-01.S -- test: rv64im-lhu-align-01 +- test: rv64i_m-lhu-align01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lhu-align-01.S -- test: rv64im-lui-01 +- test: rv64i_m-lui iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lui-01.S -- test: rv64im-lw-align-01 +- test: rv64i_m-lw-align01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lw-align-01.S -- test: rv64im-lwu-align-01 +- test: rv64i_m-lb-align01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lwu-align-01.S + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lb-align-01.S -- test: rv64im-or-01 +- test: rv64i_m-or iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/or-01.S - -- test: rv64im-ori-01 + +- test: rv64i_m-ori iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/ori-01.S - -- test: rv64im-sb-align-01 + +- test: rv64i_m-sb-align01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sb-align-01.S - -- test: rv64im-sd-align-01 + +- test: rv64i_m-sd-align01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sd-align-01.S - -- test: rv64im-sh-align-01 + +- test: rv64i_m-sh-align01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sh-align-01.S - -- test: rv64im-sll-01 + +- test: rv64i_m-sw-align01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sw-align-01.S + +- test: rv64i_m-sll iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sll-01.S - -- test: rv64im-slli-01 + +- test: rv64i_m-slli iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/slli-01.S - -- test: rv64im-slliw-01 + +- test: rv64i_m-slliw iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/slliw-01.S - -- test: rv64im-sllw-01 + +- test: rv64i_m-sllw iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sllw-01.S - -- test: rv64im-slt-01 + +- test: rv64i_m-slt iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/slt-01.S - -- test: rv64im-slti-01 + +- test: rv64i_m-slti iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/slti-01.S - -- test: rv64im-sltiu-01 + +- test: rv64i_m-sltiu iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sltiu-01.S - -- test: rv64im-sltu-01 + +- test: rv64i_m-sltu iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sltu-01.S - -- test: rv64im-sra-01 + +- test: rv64i_m-sra iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sra-01.S - -- test: rv64im-srai-01 + +- test: rv64i_m-srai iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srai-01.S - -- test: rv64im-sraiw-01 + +- test: rv64i_m-sraiw iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sraiw-01.S - -- test: rv64im-sraw-01 + +- test: rv64i_m-sraw iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sraw-01.S - -- test: rv64im-srl-01 + +- test: rv64i_m-srl iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srl-01.S - -- test: rv64im-srli-01 + +- test: rv64i_m-srli iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srli-01.S - -- test: rv64im-srliw-01 + +- test: rv64i_m-srliw iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srliw-01.S - -- test: rv64im-srlw-01 + +- test: rv64i_m-srlw iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srlw-01.S - -- test: rv64im-sub-01 + +- test: rv64i_m-sub iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sub-01.S - -- test: rv64im-subw-01 + +- test: rv64i_m-subw iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/subw-01.S - -- test: rv64im-sw-align-01 - iterations: 1 - path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sw-align-01.S - -- test: rv64im-xor-01 + +- test: rv64i_m-xor iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/xor-01.S - -- test: rv64im-xori-01 + +- test: rv64i_m-xori iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/xori-01.S -- test: rv64im-cadd-01 + #M +- test: rv64i_m-div-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cadd-01.S - -- test: rv64im-caddi4spn-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/div-01.S + +- test: rv64i_m-divu-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddi4spn-01.S - -- test: rv64im-caddi16sp-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/divu-01.S + +- test: rv64i_m-divuw-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddi16sp-01.S - -- test: rv64im-caddi-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/divuw-01.S + +- test: rv64i_m-divw-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddi-01.S - -- test: rv64im-caddiw-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/divw-01.S + +- test: rv64i_m-mul-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddiw-01.S - -- test: rv64im-caddw-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mul-01.S + +- test: rv64i_m-mulh-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddw-01.S - -- test: rv64im-cand-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mulh-01.S + +- test: rv64i_m-mulhsu-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cand-01.S - -- test: rv64im-candi-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mulhsu-01.S + +- test: rv64i_m-mulhu-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/candi-01.S - -- test: rv64im-cbeqz-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mulhu-01.S + +- test: rv64i_m-mulw-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cbeqz-01.S - -- test: rv64im-cbnez-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mulw-01.S + +- test: rv64i_m-rem-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cbnez-01.S - -- test: rv64im-cebreak-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/rem-01.S + +- test: rv64i_m-remu-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cebreak-01.S - -- test: rv64im-cj-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/remu-01.S + +- test: rv64i_m-remuw-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cj-01.S - -- test: rv64im-cjalr-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/remuw-01.S + +- test: rv64i_m-remw-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cjalr-01.S - -- test: rv64im-cjr-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/remw-01.S + + #C +- test: rv64i_m-cadd-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cjr-01.S - -- test: rv64im-cld-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cadd-01.S + +- test: rv64i_m-caddi-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cld-01.S - -- test: rv64im-cldsp-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddi-01.S + +- test: rv64i_m-caddi16sp-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cldsp-01.S - -- test: rv64im-cli-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddi16sp-01.S + +- test: rv64i_m-caddi4spn-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cli-01.S - -- test: rv64im-clui-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddi4spn-01.S + +- test: rv64i_m-caddiw-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/clui-01.S - -- test: rv64im-clw-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddiw-01.S + +- test: rv64i_m-caddw-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/clw-01.S - -- test: rv64im-clwsp-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddw-01.S + +- test: rv64i_m-cand-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/clwsp-01.S - -- test: rv64im-cmv-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cand-01.S + +- test: rv64i_m-candi-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cmv-01.S - -- test: rv64im-cnop-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/candi-01.S + +- test: rv64i_m-cbeqz-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cnop-01.S - -- test: rv64im-cor-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cbeqz-01.S + +- test: rv64i_m-cbnez-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cor-01.S - -- test: rv64im-csd-01 - iterations: 1 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cbnez-01.S + +- test: rv64i_m-cebreak-01 + iterations: 0 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csd-01.S - -- test: rv64im-csdsp-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cebreak-01.S + +- test: rv64i_m-cj-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csdsp-01.S - -- test: rv64im-cslli-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cj-01.S + +- test: rv64i_m-cjalr-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cslli-01.S - -- test: rv64im-csrai-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cjalr-01.S + +- test: rv64i_m-cjr-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csrai-01.S - -- test: rv64im-csrli-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cjr-01.S + +- test: rv64i_m-cld-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csrli-01.S - -- test: rv64im-csub-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cld-01.S + +- test: rv64i_m-cldsp-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csub-01.S - -- test: rv64im-csubw-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cldsp-01.S + +- test: rv64i_m-cli-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csubw-01.S - -- test: rv64im-csw-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cli-01.S + +- test: rv64i_m-clui-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csw-01.S - -- test: rv64im-cswsp-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/clui-01.S + +- test: rv64i_m-clw-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cswsp-01.S - -- test: rv64im-cxor-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/clw-01.S + +- test: rv64i_m-clwsp-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cxor-01.S + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/clwsp-01.S -- test: rv64im-div-01 +- test: rv64i_m-cmv-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/div-01.S - -- test: rv64im-divu-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cmv-01.S + +- test: rv64i_m-cnop-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/divu-01.S - -- test: rv64im-divuw-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cnop-01.S + +- test: rv64i_m-cor-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/divuw-01.S - -- test: rv64im-divw-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cor-01.S + +- test: rv64i_m-csd-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/divw-01.S - -- test: rv64im-mul-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csd-01.S + +- test: rv64i_m-csdsp-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mul-01.S - -- test: rv64im-mulh-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csdsp-01.S + +- test: rv64i_m-cslli-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mulh-01.S - -- test: rv64im-mulhsu-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cslli-01.S + +- test: rv64i_m-csrai-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mulhsu-01.S - -- test: rv64im-mulhu-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csrai-01.S + +- test: rv64i_m-csrli-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mulhu-01.S - -- test: rv64im-mulw-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csrli-01.S + +- test: rv64i_m-csub-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mulw-01.S - -- test: rv64im-rem-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csub-01.S + +- test: rv64i_m-csubw-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/rem-01.S - -- test: rv64im-remu-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csubw-01.S + +- test: rv64i_m-csw-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/remu-01.S - -- test: rv64im-remuw-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csw-01.S + +- test: rv64i_m-cswsp-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/remuw-01.S - -- test: rv64im-remw-01 + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cswsp-01.S + +- test: rv64i_m-cxor-01 iterations: 1 path_var: TESTS_PATH gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/M/src/remw-01.S + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cxor-01.S -- test: rv64im-ebreak - iterations: 1 +#D +- test: rv64i_m-fcvt.d.l_b25-01 + iterations: 0 path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/ebreak.S - -- test: rv64im-ecall - iterations: 1 + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.d.l_b25-01.S + +- test: rv64i_m-fcvt.d.l_b26-01 + iterations: 0 path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/ecall.S - -- test: rv64im-misalign1-jalr-01 - iterations: 1 + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.d.l_b26-01.S + +- test: rv64i_m-fcvt.d.lu_b25-01 + iterations: 0 path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign1-jalr-01.S - -- test: rv64im-misalign2-jalr-01 - iterations: 1 + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.d.lu_b25-01.S + +- test: rv64i_m-fcvt.d.lu_b26-01 + iterations: 0 path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign2-jalr-01.S - -- test: rv64im-misalign-beq-01 - iterations: 1 + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.d.lu_b26-01.S + +- test: rv64i_m-fcvt.l.d_b1-01 + iterations: 0 path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-beq-01.S - -- test: rv64im-misalign-bge-01 - iterations: 1 + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b1-01.S + +- test: rv64i_m-fcvt.l.d_b22-01.S + iterations: 0 path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-bge-01.S - -- test: rv64im-misalign-bgeu-01 - iterations: 1 + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b22-01.S + +- test: rv64i_m-fcvt.l.d_b23-01.S + iterations: 0 path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-bgeu-01.S - -- test: rv64im-misalign-blt-01 - iterations: 1 + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b23-01.S + +- test: rv64i_m-fcvt.l.d_b24-01 + iterations: 0 path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-blt-01.S - -- test: rv64im-misalign-bltu-01 - iterations: 1 + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b24-01.S + +- test: rv64i_m-fcvt.l.d_b27-01 + iterations: 0 path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-bltu-01.S - -- test: rv64im-misalign-bne-01 - iterations: 1 + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b27-01.S + +- test: rv64i_m-fcvt.l.d_b28-01 + iterations: 0 path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-bne-01.S + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b28-01.S -- test: rv64im-misalign-jal-01 - iterations: 1 +- test: rv64i_m-fcvt.l.d_b29-01 + iterations: 0 path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-jal-01.S - -- test: rv64im-misalign-ld-01 - iterations: 1 + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b29-01.S + +- test: rv64i_m-fcvt.lu.d_b1-01 + iterations: 0 path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-ld-01.S - -- test: rv64im-misalign-lh-01 - iterations: 1 + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b1-01.S + +- test: rv64i_m-fcvt.lu.d_b22-01 + iterations: 0 path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-lh-01.S - -- test: rv64im-misalign-lhu-01 - iterations: 1 + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b22-01.S + +- test: rv64i_m-fcvt.lu.d_b23-01 + iterations: 0 path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-lhu-01.S - -- test: rv64im-misalign-lw-01 - iterations: 1 + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b23-01.S + +- test: rv64i_m-fcvt.lu.d_b24-01 + iterations: 0 path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-lw-01.S + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b24-01.S -- test: rv64im-misalign-lwu-01 - iterations: 1 +- test: rv64i_m-fcvt.lu.d_b27-01 + iterations: 0 path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-lwu-01.S - -- test: rv64im-misalign-sd-01 - iterations: 1 + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b27-01.S + +- test: rv64i_m-fcvt.lu.d_b28-01 + iterations: 0 path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-sd-01.S - -- test: rv64im-misalign-sh-01 - iterations: 1 + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b28-01.S + +- test: rv64i_m-fcvt.lu.d_b29-01 + iterations: 0 path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-sh-01.S - -- test: rv64im-misalign-sw-01 - iterations: 1 + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b29-01.S + +- test: rv64i_m-fmv.d.x_b25-01 + iterations: 0 path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/misalign-sw-01.S + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.d.x_b25-01.S -- test: rv64im-Fencei - iterations: 1 +- test: rv64i_m-fmv.d.x_b26-01 + iterations: 0 path_var: TESTS_PATH - gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/Zifencei/src/Fencei.S \ No newline at end of file + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.d.x_b26-01.S + +- test: rv64i_m-fmv.x.d_b1-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b1-01.S + +- test: rv64i_m-fmv.x.d_b22-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b22-01.S + +- test: rv64i_m-fmv.x.d_b23-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b23-01.S + +- test: rv64i_m-fmv.x.d_b24-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b24-01.S + +- test: rv64i_m-fmv.x.d_b27-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b27-01.S + +- test: rv64i_m-fmv.x.d_b28-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b28-01.S + +- test: rv64i_m-fmv.x.d_b29-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b29-01.S + From 5ae8ba8ed19f5ea9cbad480cddd6e6f4d25b746e Mon Sep 17 00:00:00 2001 From: sai krishna pidugu <103561542+spidugu444@users.noreply.github.com> Date: Sun, 5 Feb 2023 23:57:58 +0530 Subject: [PATCH 5/7] Added testlist file for riscv-arch-test suite --- .../testlist_riscv-arch-test-cv32a60x.yaml | 472 ++++++++++++++++++ 1 file changed, 472 insertions(+) create mode 100644 cva6/tests/testlist_riscv-arch-test-cv32a60x.yaml diff --git a/cva6/tests/testlist_riscv-arch-test-cv32a60x.yaml b/cva6/tests/testlist_riscv-arch-test-cv32a60x.yaml new file mode 100644 index 0000000000..cc68013832 --- /dev/null +++ b/cva6/tests/testlist_riscv-arch-test-cv32a60x.yaml @@ -0,0 +1,472 @@ +# Copyright Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- +## C +- test: rv32im-cadd-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cadd-01.S + +- test: rv32im-caddi-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/caddi-01.S + +- test: rv32im-caddi16sp-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/caddi16sp-01.S + +- test: rv32im-caddi4spn-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/caddi4spn-01.S + +- test: rv32im-cand-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cand-01.S + +- test: rv32im-candi-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/candi-01.S + +- test: rv32im-cbeqz-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cbeqz-01.S + +- test: rv32im-cbnez-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cbnez-01.S + +- test: rv32im-cebreak-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cebreak-01.S + +- test: rv32im-cj-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cj-01.S + +- test: rv32im-cjal-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cjal-01.S + +- test: rv32im-cjalr-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cjalr-01.S + +- test: rv32im-cjr-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cjr-01.S + +- test: rv32im-cli-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cli-01.S + +- test: rv32im-clui-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/clui-01.S + +- test: rv32im-clw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/clw-01.S + +- test: rv32im-clwsp-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/clwsp-01.S + +- test: rv32im-cmv-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cmv-01.S + +- test: rv32im-cnop-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cnop-01.S + +- test: rv32im-cor-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cor-01.S + +- test: rv32im-cslli-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cslli-01.S + +- test: rv32im-csrai-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csrai-01.S + +- test: rv32im-csrli-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csrli-01.S + +- test: rv32im-csub-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csub-01.S + +- test: rv32im-csw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csw-01.S + +- test: rv32im-cswsp-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cswsp-01.S + +- test: rv32im-cxor-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cxor-01.S + + # I +- test: rv32im-add-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/add-01.S + +- test: rv32im-addi-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/addi-01.S + +- test: rv32im-and-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/and-01.S + +- test: rv32im-andi-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/andi-01.S + +- test: rv32im-auipc-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/auipc-01.S + +- test: rv32im-beq-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/beq-01.S + +- test: rv32im-bge-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bge-01.S + +- test: rv32im-bgeu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bgeu-01.S + +- test: rv32im-blt-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/blt-01.S + +- test: rv32im-bltu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bltu-01.S + +- test: rv32im-bne-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bne-01.S + +- test: rv32im-fence-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/fence-01.S + +- test: rv32im-jal-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jal-01.S + +- test: rv32im-jalr-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jalr-01.S + +- test: rv32im-lb-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lb-align-01.S + +- test: rv32im-lbu-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lbu-align-01.S + +- test: rv32im-lh-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lh-align-01.S + +- test: rv32im-lhu-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lhu-align-01.S + +- test: rv32im-lui-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lui-01.S + +- test: rv32im-lw-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lw-align-01.S + +- test: rv32im-or-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/or-01.S + +- test: rv32im-ori-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/ori-01.S + +- test: rv32im-sb-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sb-align-01.S + +- test: rv32im-sh-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sh-align-01.S + +- test: rv32im-sll-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sll-01.S + +- test: rv32im-slli-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slli-01.S + +- test: rv32im-slt-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slt-01.S + +- test: rv32im-slti-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slti-01.S + +- test: rv32im-sltiu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sltiu-01.S + +- test: rv32im-sltu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sltu-01.S + +- test: rv32im-sra-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sra-01.S + +- test: rv32im-srai-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srai-01.S + +- test: rv32im-srl-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srl-01.S + +- test: rv32im-srli-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srli-01.S + +- test: rv32im-sub-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sub-01.S + +- test: rv32im-sw-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sw-align-01.S + +- test: rv32im-xor-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/xor-01.S + +- test: rv32im-xori-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/xori-01.S + + # M +- test: rv32im-div-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/M/src/div-01.S + +- test: rv32im-divu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/M/src/divu-01.S + +- test: rv32im-mul-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mul-01.S + +- test: rv32im-mulh-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mulh-01.S + +- test: rv32im-mulhsu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mulhsu-01.S + +- test: rv32im-mulhu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mulhu-01.S + +- test: rv32im-rem-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/M/src/rem-01.S + +- test: rv32im-remu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-arch-test/riscv-test-suite/env/ -I/riscv-isa-sim/arch_test_target/spike/" + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/M/src/remu-01.S + From 32e525662eac519ead6aa81c5928e565c59d889d Mon Sep 17 00:00:00 2001 From: JeanRochCoulon Date: Mon, 6 Feb 2023 08:35:31 +0100 Subject: [PATCH 6/7] Gather the 32 bit tests together --- cva6/regress/smoke-tests.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cva6/regress/smoke-tests.sh b/cva6/regress/smoke-tests.sh index fe2770212e..78dfd86773 100644 --- a/cva6/regress/smoke-tests.sh +++ b/cva6/regress/smoke-tests.sh @@ -30,7 +30,6 @@ python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.ya python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml --test rv64i_m-add-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-isa-sim/arch_test_target/spike/link.ld -python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-isa-sim/arch_test_target/spike/link.ld python3 cva6.py --testlist=../tests/testlist_custom.yaml --test custom_test_template --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c\ --gcc_opts "-g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" @@ -38,6 +37,7 @@ make -C ../../core-v-cores/cva6 clean make clean_all python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-add --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS +python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-isa-sim/arch_test_target/spike/link.ld make -C ../../core-v-cores/cva6 clean make clean_all From 0b317e17043b4301a9ef377ccc3e7aa7d71e432e Mon Sep 17 00:00:00 2001 From: sai krishna pidugu <103561542+spidugu444@users.noreply.github.com> Date: Mon, 6 Feb 2023 17:27:30 +0530 Subject: [PATCH 7/7] Updated cva6.yml by adding pub_riscv-arch-test task --- .gitlab-ci/cva6.yml | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/.gitlab-ci/cva6.yml b/.gitlab-ci/cva6.yml index b9442f7d2f..5dbfcd1000 100644 --- a/.gitlab-ci/cva6.yml +++ b/.gitlab-ci/cva6.yml @@ -158,6 +158,33 @@ pub_smoke: paths: - artifacts/reports/*.yml +pub_riscv_arch_test: + stage: two + extends: + - .template_job_short_ci + needs: + - job: pub_smoke + artifacts: false + parallel: + matrix: + - DV_TARGET: [cv64a6_imafdc_sv39, cv32a60x] + variables: + DV_SIMULATORS: "veri-testharness,spike" + DASHBOARD_JOB_TITLE: "arch_test $DV_TARGET" + DASHBOARD_JOB_DESCRIPTION: "Compliance regression suite" + DASHBOARD_SORT_INDEX: 0 + DASHBOARD_JOB_CATEGORY: "Test suites" + script: + - mkdir -p artifacts/reports + - python3 .gitlab-ci/scripts/report_fail.py + - echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC + - source cva6/regress/dv-riscv-arch-test.sh + - python3 .gitlab-ci/scripts/report_simu.py cva6/sim/logfile.log + artifacts: + when: always + paths: + - "artifacts/reports/*.yml" + pub_hwconfig: stage: two extends: