From 896f75f5bfab8ac4d75e50324dbe857b1e523ca3 Mon Sep 17 00:00:00 2001
From: Vaughn Betz <vaughn@eecg.utoronto.ca>
Date: Tue, 28 Nov 2023 19:06:18 -0500
Subject: [PATCH 01/12] Updating k6_N10_40nm.xml and adding
 k6_N10_sparse_crossbar_40nm.xml. These architectures are now more heavily
 commented and suitable for work in a grad course (ECE 1756). I cut the logic
 block areas to something more reasonable for a simple architecture like this;
 the area numbers for the logic blocks and the local mux delays for the sparse
 architecture are based on coarse scaling / guessing so they aren't extremely
 accurate.

---
 vtr_flow/arch/timing/k6_N10_40nm.xml          | 178 +++++----
 .../timing/k6_N10_sparse_crossbar_40nm.xml    | 348 ++++++++++++++++++
 2 files changed, 451 insertions(+), 75 deletions(-)
 create mode 100644 vtr_flow/arch/timing/k6_N10_sparse_crossbar_40nm.xml

diff --git a/vtr_flow/arch/timing/k6_N10_40nm.xml b/vtr_flow/arch/timing/k6_N10_40nm.xml
index 711e4825539..07e017ad7d4 100644
--- a/vtr_flow/arch/timing/k6_N10_40nm.xml
+++ b/vtr_flow/arch/timing/k6_N10_40nm.xml
@@ -4,27 +4,38 @@
   - 40 nm technology
   - General purpose logic block: 
     K = 6, N = 10
-  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+  - Routing architecture: L = 4, fc_in = 0.15, fc_out = 0.15
+  - Unidirectional (mux-based) routing
+
 
   Details on Modelling:
 
   Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.  This architecture has no fracturable LUTs nor any heterogeneous blocks.
-
+  The delays and areas are based on a mix of values from commercial 40 nm
+  FPGAs with a comparable architecture and 40 nm interconnect and 
+  transistor models.
 
   Authors: Jason Luu, Jeff Goeders, Vaughn Betz
 -->
 <architecture>
   <!-- 
        ODIN II specific config begins 
-       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
-       ".model [type_of_block]") that this architecture supports.
-
-       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
-       already special structures in blif (.names, .input, .output, and .latch) 
-       that describe them.
+       This part of the architecture file describes the "primitives" 
+       that exist in a device to the synthesis tool used to "elaborate" 
+       verilog into these primitives (which is called ODIN-II).
+       Basic LUTs, I/Os and FFs are built into the language used by this 
+       flow (blif keywords .names, .input, .output and .latch), so they 
+       don't have to be described here.
+    
+       For this lab you are also given the benchmark netlists after 
+       synthesis is complete (in the blif directory), so you don't need 
+       to run ODIN II.
   -->
   <models>
   </models>
+  <!-- ODIN II specific config ends -->
+
+  <!-- Descritions of the physical tiles that exist on the die begins -->
   <tiles>
     <tile name="io" area="0">
       <sub_tile name="io" capacity="8">
@@ -34,7 +45,15 @@
         <input name="outpad" num_pins="1"/>
         <output name="inpad" num_pins="1"/>
         <clock name="clock" num_pins="1"/>
-        <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+        <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.15"/>
+      <!-- IOs go on the periphery of the FPGA in this 
+           architecture. Since I don't want to define four 
+           different physical I/Os for the left, right, top, 
+           and bottom sides just say each pin of the I/O 
+           block is accessible from all four sides so we can
+           reach routing channels on some side of the block
+           no matter which side of the chip we're on.
+        -->
         <pinlocations pattern="custom">
           <loc side="left">io.outpad io.inpad io.clock</loc>
           <loc side="top">io.outpad io.inpad io.clock</loc>
@@ -43,21 +62,42 @@
         </pinlocations>
       </sub_tile>
     </tile>
-    <tile name="clb" area="53894">
+
+    <!-- Define general purpose logic block (CLB) begin -->
+          <!-- Area below is for everything inside the
+                logic block (LUTs, FFs, intra-cluster 
+                routing). It's a bit on the low side given the large crossbars in this
+                architecture - more appropriate for a lower-cost
+                FPGA with smaller transistors and narrower metal.
+                -->
+    <tile name="clb" area="18000">
+      <!-- We can place a clustered block of type clb on a tile location 
+           of type clb.
+           -->
       <sub_tile name="clb">
         <equivalent_sites>
           <site pb_type="clb" pin_mapping="direct"/>
         </equivalent_sites>
+
+      <!-- We have a full crossbar between the cluster inputs and the 
+           LUT inputs, so the router can route to *any* input or from
+           *any* output on the logic block.  Hence mark the logic block
+           inputs as fully logically equivalent (swappable by the router) and also the
+           logic block outputs as logically equivalent, which means
+           they can also be swapped by the router.
+           -->
+
         <input name="I" num_pins="40" equivalent="full"/>
         <output name="O" num_pins="10" equivalent="instance"/>
         <clock name="clk" num_pins="1"/>
-        <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+        <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.15"/>
         <pinlocations pattern="spread"/>
       </sub_tile>
     </tile>
   </tiles>
-  <!-- ODIN II specific config ends -->
-  <!-- Physical descriptions begin -->
+  <!-- Physical tile descriptions end -->
+  
+  <!-- Chip layout (in terms of where tiles are) begins -->
   <layout>
     <auto_layout aspect_ratio="1.0">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
@@ -67,22 +107,11 @@
       <fill type="clb" priority="10"/>
     </auto_layout>
   </layout>
+  <!-- Chip layout ends -->
+
+  <!-- Electrical and inter-cluster (general) routing description begins -->
   <device>
-    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
-			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
-			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
-			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
-			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
-			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
-			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
-	                     by 2.5x when looking up in Jeff's tables.
-			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
-			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
-			     4x minimum drive strength buffer. -->
+    <!-- Some area and timing parameters -->
     <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
     <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
      	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
@@ -92,49 +121,61 @@
       <x distr="uniform" peak="1.000000"/>
       <y distr="uniform" peak="1.000000"/>
     </chan_width_distr>
+
+    <!-- Define the switch block pattern (pattern of switches between inter-tile routing wires)
+         The Wilton switch block is a sample pattern; you can use custom switch blocks for more control -->
     <switch_block type="wilton" fs="3"/>
+
+    <!-- Set which switch to use for input connection blocks. Only affects timing and area, not connectivity -->
     <connection_block input_switch_name="ipin_cblock"/>
   </device>
   <switchlist>
     <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
 	       book area formula. This means the mux transistors are about 5x minimum drive strength.
 	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
-	       2.5x when looking up in Jeff's tables.
-	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
-	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. 
+	       -->
     <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
     <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
     <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
   </switchlist>
   <segmentlist>
     <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
-			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
-			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+          Wires of this pitch will fit over a 90 nm
+          high logic tile (which is about the height of a Stratix IV logic tile).
+          I'm using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. 
+          length below is in units of logic blocks, and Rmetal and Cmetal are
+          per logic block passed, so wire delay adapts automatically if you change the
+          length=? value.   -->
+
+    <!-- Currently only one type of routing wire, which
+         is of length 4 and has switches to every connection
+         box (4 of them) and switch box (5 of them) 
+         it passes. You can change wirelengths just by changing the length="?" values
+         and changing the number of 1's (or 0's) in the <sb type and <cb type lines to
+         match the number of switch blocks and connection blocks a wire of that length
+         would span. -->
     <segment freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
       <mux name="0"/>
       <sb type="pattern">1 1 1 1 1</sb>
       <cb type="pattern">1 1 1 1</cb>
     </segment>
   </segmentlist>
+  <!-- Electrical and inter-cluster routing description ends -->
+
+  <!-- Description of the capabilities (number of BLEs, modes) and local interconnect in
+       each type of complex (clustered) block (e.g. LBs) begins
+    -->
   <complexblocklist>
     <!-- Define I/O pads begin -->
-    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
     <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
     <pb_type name="io">
       <input name="outpad" num_pins="1"/>
       <output name="inpad" num_pins="1"/>
       <clock name="clock" num_pins="1"/>
       <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
+	     The delays below are to and from registers in the I/O (and generally I/Os are registered 
+	     today).
 	     -->
       <mode name="inpad">
         <pb_type name="inpad" blif_model=".input" num_pb="1">
@@ -156,25 +197,17 @@
           </direct>
         </interconnect>
       </mode>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- IOs go on the periphery of the FPGA, for consistency, 
-          make it physically equivalent on all sides so that only one definition of I/Os is needed.
-          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-        -->
-      <!-- Place I/Os on the sides of the FPGA -->
+
+      <!-- Not modeling I/O power for now -->
       <power method="ignore"/>
     </pb_type>
     <!-- Define I/O pads ends -->
+
     <!-- Define general purpose logic block (CLB) begin -->
-    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
-	   area is 60 L^2 yields a tile area of 84375 MWTAs.
-	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
-	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
-	   block. Note that the crossbar / local interconnect is considered part of the logic block
-	   area in this analysis. That is a lower proportion of of routing area than most academics
-	   assume, but note that the total routing area really includes the crossbar, which would push
-	   routing area up significantly, we estimate into the ~70% range. 
-	   -->
+          <!-- Area below is for everything inside the
+                logic block (LUTs, FFs, intra-cluster 
+                routing).  
+           -->
     <pb_type name="clb">
       <input name="I" num_pins="40" equivalent="full"/>
       <output name="O" num_pins="10" equivalent="instance"/>
@@ -198,22 +231,16 @@
               <input name="in" num_pins="6" port_class="lut_in"/>
               <output name="out" num_pins="1" port_class="lut_out"/>
               <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
+              <!-- These are the delay per LUT input on a Stratix IV LUT.
+                   The average is 261 ps, and inputs earlier in the mux tree are slower.
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
                   82e-12
                   173e-12
                   261e-12
                   263e-12
                   398e-12
                   397e-12
-                  -->
-              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                261e-12
-                261e-12
-                261e-12
-                261e-12
-                261e-12
-                261e-12
               </delay_matrix>
             </pb_type>
             <!-- Define flip-flop -->
@@ -224,6 +251,10 @@
               <T_setup value="66e-12" port="ff.D" clock="clk"/>
               <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
             </pb_type>
+
+            <!-- many lines below to describe the interconnect
+                 wires, muxes and crossbars inside a cluster.
+              -->
             <interconnect>
               <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
               <direct name="direct2" input="lut6.out" output="ff.D">
@@ -262,15 +293,12 @@
         </complete>
         <complete name="clks" input="clb.clk" output="fle[9:0].clk">
         </complete>
-        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
-               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
-               naive specification).
+
+        <!-- The BLE outputs are directly connected to the
+             CLB (cluster) outputs.  
           -->
         <direct name="clbouts1" input="fle[9:0].out" output="clb.O"/>
       </interconnect>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- Place this general purpose logic block in any unspecified column -->
     </pb_type>
     <!-- Define general purpose logic block (CLB) ends -->
   </complexblocklist>
diff --git a/vtr_flow/arch/timing/k6_N10_sparse_crossbar_40nm.xml b/vtr_flow/arch/timing/k6_N10_sparse_crossbar_40nm.xml
new file mode 100644
index 00000000000..2d6dfad7a7d
--- /dev/null
+++ b/vtr_flow/arch/timing/k6_N10_sparse_crossbar_40nm.xml
@@ -0,0 +1,348 @@
+<!-- 
+  Architecture with no fracturable LUTs
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10
+  - Routing architecture: L = 4, fc_in = 0.15, fc_out = 0.15
+  - Unidirectional (mux-based) routing
+  - Logic block local routing: 
+      - cluster input -> BLE input crossbar 80% depopulated
+      - BLE output -> BLE input (local feedback) crossbar fully populated 
+
+  Details on Modelling:
+
+  Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.  This architecture has no fracturable LUTs nor any heterogeneous blocks.
+  The delays and areas are based on a mix of values from commercial 40 nm
+  FPGAs with a comparable architecture and 40 nm interconnect and 
+  transistor models.
+
+  Authors: Vaughn Betz, Amin Mohaghegh, Jason Luu, Jeff Goeders
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       This part of the architecture file describes the "primitives" 
+       that exist in a device to the synthesis tool used to "elaborate" 
+       verilog into these primitives (which is called ODIN-II).
+       Basic LUTs, I/Os and FFs are built into the language used by this 
+       flow (blif keywords .names, .input, .output and .latch), so they 
+       don't have to be described here.
+    
+       For this lab you are also given the benchmark netlists after 
+       synthesis is complete (in the blif directory), so you don't need 
+       to run ODIN II.
+  -->
+  <models>
+  </models>
+  <!-- ODIN II specific config ends -->
+
+  <!-- Descritions of the physical tiles that exist on the die begins -->
+  <tiles>
+    <tile name="io" area="0">
+      <sub_tile name="io" capacity="8">
+        <equivalent_sites>
+          <site pb_type="io" pin_mapping="direct"/>
+        </equivalent_sites>
+        <input name="outpad" num_pins="1"/>
+        <output name="inpad" num_pins="1"/>
+        <clock name="clock" num_pins="1"/>
+        <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.15"/>
+      <!-- IOs go on the periphery of the FPGA in this 
+           architecture. Since I don't want to define four 
+           different physical I/Os for the left, right, top, 
+           and bottom sides just say each pin of the I/O 
+           block is accessible from all four sides so we can
+           reach routing channels on some side of the block
+           no matter which side of the chip we're on.
+        -->
+        <pinlocations pattern="custom">
+          <loc side="left">io.outpad io.inpad io.clock</loc>
+          <loc side="top">io.outpad io.inpad io.clock</loc>
+          <loc side="right">io.outpad io.inpad io.clock</loc>
+          <loc side="bottom">io.outpad io.inpad io.clock</loc>
+        </pinlocations>
+      </sub_tile>
+    </tile>
+
+    <!-- Define general purpose logic block (CLB) begin -->
+          <!-- Area below is for everything inside the
+                logic block (LUTs, FFs, intra-cluster 
+                routing). It's a bit on the low side given the large crossbars in this
+                architecture - more appropriate for a lower-cost
+                FPGA with smaller transistors and narrower metal.
+                Compared to an architecture with a fully populated 
+                crossbar the logic block area is about 35% smaller.
+                -->
+    <tile name="clb" area="12500">
+      <!-- We can place a clustered block of type clb on a tile location 
+           of type clb.
+           -->
+      <sub_tile name="clb">
+        <equivalent_sites>
+          <site pb_type="clb" pin_mapping="direct"/>
+        </equivalent_sites>
+
+      <!-- We have a full crossbar between the cluster inputs and the 
+           LUT inputs, so the router can route to *any* input or from
+           *any* output on the logic block.  Hence mark the logic block
+           inputs as fully logically equivalent (swappable by the router) and also the
+           logic block outputs as logically equivalent, which means
+           they can also be swapped by the router.
+           -->
+
+        <input name="I0" num_pins="7" equivalent="full"/>
+        <input name="I1" num_pins="7" equivalent="full"/>
+        <input name="I2" num_pins="7" equivalent="full"/>
+        <input name="I3" num_pins="7" equivalent="full"/>
+        <input name="I4" num_pins="7" equivalent="full"/>
+        <input name="I5" num_pins="5" equivalent="full"/>
+        <output name="O" num_pins="10" equivalent="instance"/>
+        <clock name="clk" num_pins="1"/>
+        <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.15"/>
+        <pinlocations pattern="spread"/>
+      </sub_tile>
+    </tile>
+  </tiles>
+  <!-- Physical tile descriptions end -->
+  
+  <!-- Chip layout (in terms of where tiles are) begins -->
+  <layout>
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
+  </layout>
+  <!-- Chip layout ends -->
+
+  <!-- Electrical and inter-cluster (general) routing description begins -->
+  <device>
+    <!-- Some area and timing parameters -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+
+    <!-- Define the switch block pattern (pattern of switches between inter-tile routing wires)
+         The Wilton switch block is a sample pattern; you can use custom switch blocks for more control -->
+    <switch_block type="wilton" fs="3"/>
+
+    <!-- Set which switch to use for input connection blocks. Only affects timing and area, not connectivity -->
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. 
+	       -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+          Wires of this pitch will fit over a 90 nm
+          high logic tile (which is about the height of a Stratix IV logic tile).
+          I'm using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. 
+          length below is in units of logic blocks, and Rmetal and Cmetal are
+          per logic block passed, so wire delay adapts automatically if you change the
+          length=? value.   -->
+
+    <!-- Currently only one type of routing wire, which
+         is of length 4 and has switches to every connection
+         box (4 of them) and switch box (5 of them) 
+         it passes. You can change wirelengths just by changing the length="?" values
+         and changing the number of 1's (or 0's) in the <sb type and <cb type lines to
+         match the number of switch blocks and connection blocks a wire of that length
+         would span. -->
+    <segment freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <!-- Electrical and inter-cluster routing description ends -->
+
+  <!-- Description of the capabilities (number of BLEs, modes) and local interconnect in
+       each type of complex (clustered) block (e.g. LBs) begins
+    -->
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <clock name="clock" num_pins="1"/>
+      <!-- IOs can operate as either inputs or outputs.
+	     The delays below are to and from registers in the I/O (and generally I/Os are registered 
+	     today).
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- Not modeling I/O power for now -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+
+    <!-- Define general purpose logic block (CLB) begin -->
+          <!-- Area below is for everything inside the
+                logic block (LUTs, FFs, intra-cluster 
+                routing).  
+           -->
+    <pb_type name="clb">
+      <input name="I0" num_pins="7" equivalent="full"/>
+      <input name="I1" num_pins="7" equivalent="full"/>
+      <input name="I2" num_pins="7" equivalent="full"/>
+      <input name="I3" num_pins="7" equivalent="full"/>
+      <input name="I4" num_pins="7" equivalent="full"/>
+      <input name="I5" num_pins="5" equivalent="full"/>
+      <output name="O" num_pins="10" equivalent="instance"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe basic logic element.  
+             Each basic logic element has a 6-LUT that can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <output name="out" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- 6-LUT mode definition begin -->
+        <mode name="n1_lut6">
+          <!-- Define 6-LUT mode -->
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define LUT -->
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the delay per LUT input on a Stratix IV LUT.
+                   The average is 261 ps, and inputs earlier in the mux tree are slower.
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+              </delay_matrix>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+
+            <!-- many lines below to describe the interconnect
+                 wires, muxes and crossbars inside a cluster.
+              -->
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- 6-LUT mode definition end -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a sparse crossbar to get logical equivalence at inputs of CLB 
+		     The delays below come from Stratix IV. the delay through a connection block
+		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+		     delay within the crossbar is 95 ps. Since we're using smaller crossbars than 
+                     Stratix IV in this sparse architecture we further reduce the delay to 70 ps. 
+		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+		     to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="pin0_mux" input="clb.I0" output="fle[9:0].in[0:0]">
+         <delay_constant max="70e-12" in_port="clb.I0" out_port="fle[9:0].in[0:0]"/>
+        </complete>
+        <complete name="pin1_mux" input="clb.I1" output="fle[9:0].in[1:1]">
+         <delay_constant max="70e-12" in_port="clb.I1" out_port="fle[9:0].in[1:1]"/>
+        </complete>
+        <complete name="pin2_mux" input="clb.I2" output="fle[9:0].in[2:2]">
+         <delay_constant max="70e-12" in_port="clb.I2" out_port="fle[9:0].in[2:2]"/>
+        </complete>
+        <complete name="pin3_mux" input="clb.I3" output="fle[9:0].in[3:3]">
+         <delay_constant max="70e-12" in_port="clb.I3" out_port="fle[9:0].in[3:3]"/>
+        </complete>
+        <complete name="pin4_mux" input="clb.I4" output="fle[9:0].in[4:4]">
+         <delay_constant max="70e-12" in_port="clb.I4" out_port="fle[9:0].in[4:4]"/>
+        </complete>
+        <complete name="pin5_mux" input="clb.I5" output="fle[9:0].in[5:5]">
+         <delay_constant max="70e-12" in_port="clb.I5" out_port="fle[9:0].in[5:5]"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+
+        <!-- The BLE outputs are directly connected to the
+             CLB (cluster) outputs.  
+          -->
+        <direct name="clbouts1" input="fle[9:0].out" output="clb.O"/>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+  <power>
+    <local_interconnect C_wire="2.5e-10"/>
+    <mux_transistor_size mux_transistor_size="3"/>
+    <FF_size FF_size="4"/>
+    <LUT_transistor_size LUT_transistor_size="4"/>
+  </power>
+  <clocks>
+    <clock buffer_size="auto" C_wire="2.5e-10"/>
+  </clocks>
+</architecture>

From bf664cde74e60e0a6b5a6aa79ecaad7cda7f822d Mon Sep 17 00:00:00 2001
From: Vaughn Betz <vaughn@eecg.utoronto.ca>
Date: Fri, 1 Dec 2023 18:38:50 -0500
Subject: [PATCH 02/12] Updating vtr_reg_nightly1/vpr_mcnc_equiv golden results
 to lower logic block area due to arch file update for 1756

---
 .../config/golden_results.txt                 | 40 +++++++++----------
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
index 5705eff7e4e..41b165a6fee 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
@@ -1,20 +1,20 @@
- arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
- k6_N10_40nm.xml	  alu4.pre-vpr.blif	  common	  6.73	  vpr	  62.10 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  96	  14	  -1	  -1	  success	  574ed3d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T03:32:29	  gh-actions-runner-vtr-auto-spawned1	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  63588	  14	  8	  926	  934	  0	  478	  118	  12	  12	  144	  clb	  auto	  24.5 MiB	  0.47	  4884	  62.1 MiB	  0.23	  0.01	  4.44219	  -30.3043	  -4.44219	  nan	  0.42	  0.0021903	  0.00183391	  0.0980152	  0.0855769	  46	  7149	  37	  5.3894e+06	  5.17382e+06	  394751.	  2741.33	  2.91	  0.891781	  0.775897	  6951	  23	  5053	  20987	  796351	  133240	  5.13954	  nan	  -33.4983	  -5.13954	  0	  0	  505417.	  3509.84	  0.18	  0.40	  0.153733	  0.137135	 
- k6_N10_40nm.xml	  apex2.pre-vpr.blif	  common	  9.07	  vpr	  63.96 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  114	  38	  -1	  -1	  success	  574ed3d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T03:32:29	  gh-actions-runner-vtr-auto-spawned1	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  65500	  39	  3	  1113	  1117	  0	  655	  156	  13	  13	  169	  clb	  auto	  26.4 MiB	  0.59	  7870	  64.0 MiB	  0.43	  0.01	  5.12206	  -15.0309	  -5.12206	  nan	  0.52	  0.00289627	  0.00246029	  0.157442	  0.136647	  64	  12583	  35	  6.52117e+06	  6.14392e+06	  645515.	  3819.62	  3.68	  0.899611	  0.773936	  12262	  22	  7328	  35867	  1657301	  241927	  5.33547	  nan	  -15.7436	  -5.33547	  0	  0	  804841.	  4762.37	  0.30	  0.68	  0.225833	  0.202698	 
- k6_N10_40nm.xml	  apex4.pre-vpr.blif	  common	  7.88	  vpr	  62.30 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  95	  9	  -1	  -1	  success	  574ed3d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T03:32:29	  gh-actions-runner-vtr-auto-spawned1	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  63800	  9	  19	  897	  916	  0	  536	  123	  12	  12	  144	  clb	  auto	  24.5 MiB	  0.51	  6406	  62.3 MiB	  0.27	  0.01	  4.42576	  -73.6135	  -4.42576	  nan	  0.43	  0.00211173	  0.00180373	  0.101799	  0.0895754	  64	  11175	  39	  5.3894e+06	  5.11993e+06	  539713.	  3748.01	  3.77	  0.867445	  0.755659	  9917	  26	  6242	  32065	  1470557	  218968	  4.79093	  nan	  -80.7921	  -4.79093	  0	  0	  673071.	  4674.10	  0.24	  0.62	  0.203706	  0.183701	 
- k6_N10_40nm.xml	  bigkey.pre-vpr.blif	  common	  10.48	  vpr	  63.88 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  94	  229	  -1	  -1	  success	  574ed3d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T03:32:29	  gh-actions-runner-vtr-auto-spawned1	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  65416	  263	  197	  1372	  1603	  1	  490	  554	  17	  17	  289	  io	  auto	  26.1 MiB	  0.38	  4483	  63.9 MiB	  0.84	  0.02	  2.49496	  -621.054	  -2.49496	  2.49496	  1.04	  0.0029709	  0.00266535	  0.260983	  0.232834	  34	  7614	  24	  1.21262e+07	  5.06604e+06	  661981.	  2290.59	  4.73	  1.11739	  1.00043	  7244	  21	  2385	  12332	  703755	  133974	  2.79302	  2.79302	  -731.649	  -2.79302	  0	  0	  811075.	  2806.49	  0.38	  0.41	  0.196736	  0.179503	 
- k6_N10_40nm.xml	  clma.pre-vpr.blif	  common	  35.38	  vpr	  87.80 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  380	  62	  -1	  -1	  success	  574ed3d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T03:32:29	  gh-actions-runner-vtr-auto-spawned1	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  89912	  383	  82	  3674	  4077	  1	  2327	  845	  22	  22	  484	  clb	  auto	  50.6 MiB	  2.00	  31688	  87.8 MiB	  4.28	  0.03	  7.64354	  -320.974	  -7.64354	  7.64354	  1.93	  0.00658555	  0.00575777	  1.08369	  0.922836	  86	  50397	  34	  2.15576e+07	  2.04797e+07	  2.58188e+06	  5334.46	  15.28	  3.76643	  3.19334	  45664	  30	  23171	  103951	  5310888	  689348	  8.00174	  8.00174	  -356.375	  -8.00174	  0	  0	  3.23937e+06	  6692.90	  1.00	  1.61	  0.578299	  0.50914	 
- k6_N10_40nm.xml	  des.pre-vpr.blif	  common	  8.43	  vpr	  61.79 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  99	  256	  -1	  -1	  success	  574ed3d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T03:32:29	  gh-actions-runner-vtr-auto-spawned1	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  63276	  256	  245	  954	  1199	  0	  610	  600	  18	  18	  324	  io	  auto	  23.6 MiB	  0.30	  4929	  61.8 MiB	  0.65	  0.01	  3.47311	  -656.936	  -3.47311	  nan	  1.12	  0.00280662	  0.00259873	  0.181055	  0.166188	  32	  8273	  43	  1.37969e+07	  5.33551e+06	  718733.	  2218.31	  2.66	  0.732007	  0.679636	  7084	  18	  2745	  6851	  371614	  80901	  4.07972	  nan	  -758.692	  -4.07972	  0	  0	  879796.	  2715.42	  0.41	  0.25	  0.13524	  0.127392	 
- k6_N10_40nm.xml	  diffeq.pre-vpr.blif	  common	  6.66	  vpr	  62.50 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  97	  64	  -1	  -1	  success	  574ed3d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T03:32:29	  gh-actions-runner-vtr-auto-spawned1	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  64000	  64	  39	  1371	  1410	  1	  553	  200	  12	  12	  144	  clb	  auto	  24.7 MiB	  0.41	  3679	  62.5 MiB	  0.31	  0.01	  4.82442	  -961.44	  -4.82442	  4.82442	  0.42	  0.00239893	  0.00203237	  0.124701	  0.108675	  40	  5108	  26	  5.3894e+06	  5.22772e+06	  346969.	  2409.51	  1.91	  0.793996	  0.68999	  4725	  22	  3170	  10542	  393579	  69153	  5.25727	  5.25727	  -1077.47	  -5.25727	  0	  0	  435722.	  3025.85	  0.18	  0.29	  0.165918	  0.148986	 
- k6_N10_40nm.xml	  dsip.pre-vpr.blif	  common	  8.98	  vpr	  63.57 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  95	  229	  -1	  -1	  success	  574ed3d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T03:32:29	  gh-actions-runner-vtr-auto-spawned1	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  65092	  229	  197	  1370	  1567	  1	  535	  521	  16	  16	  256	  io	  auto	  25.8 MiB	  0.40	  4561	  63.6 MiB	  0.86	  0.02	  2.5005	  -628.06	  -2.5005	  2.5005	  0.89	  0.00334002	  0.00304005	  0.274314	  0.245709	  38	  7841	  24	  1.05632e+07	  5.11993e+06	  632420.	  2470.39	  3.55	  1.17098	  1.0567	  7234	  21	  2954	  12412	  674078	  134874	  2.86759	  2.86759	  -738.271	  -2.86759	  0	  0	  795593.	  3107.78	  0.35	  0.41	  0.198071	  0.181997	 
- k6_N10_40nm.xml	  elliptic.pre-vpr.blif	  common	  27.44	  vpr	  75.48 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  230	  131	  -1	  -1	  success	  574ed3d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T03:32:29	  gh-actions-runner-vtr-auto-spawned1	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  77292	  131	  114	  3421	  3535	  1	  1217	  475	  18	  18	  324	  clb	  auto	  38.4 MiB	  1.11	  11570	  75.5 MiB	  1.37	  0.02	  6.53834	  -3919.35	  -6.53834	  6.53834	  1.16	  0.00619897	  0.00541421	  0.469367	  0.399191	  52	  19846	  29	  1.37969e+07	  1.23956e+07	  1.06130e+06	  3275.60	  8.32	  2.62385	  2.24634	  17638	  27	  8530	  40930	  2146023	  314235	  7.29077	  7.29077	  -4559.02	  -7.29077	  0	  0	  1.39738e+06	  4312.90	  0.73	  1.18	  0.567664	  0.500941	 
- k6_N10_40nm.xml	  ex1010.pre-vpr.blif	  common	  34.18	  vpr	  78.71 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  302	  10	  -1	  -1	  success	  574ed3d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T03:32:29	  gh-actions-runner-vtr-auto-spawned1	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  80600	  10	  10	  2659	  2669	  0	  1417	  322	  20	  20	  400	  clb	  auto	  42.2 MiB	  1.81	  26744	  78.7 MiB	  1.58	  0.02	  6.13037	  -60.5222	  -6.13037	  nan	  1.59	  0.00849131	  0.00704769	  0.544255	  0.466669	  94	  47980	  40	  1.74617e+07	  1.6276e+07	  2.27873e+06	  5696.83	  21.77	  3.67277	  3.11612	  42286	  31	  14568	  90613	  5743576	  639376	  6.64251	  nan	  -64.9523	  -6.64251	  0	  0	  2.85166e+06	  7129.14	  0.89	  1.61	  0.453105	  0.398577	 
- k6_N10_40nm.xml	ex5p.pre-vpr.blif	common	4.88	vpr	60.52 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	78	8	-1	-1	success	v8.0.0-7841-g74dc1fc14-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-197-generic x86_64	2023-06-08T03:59:32	redacted.eecg.utoronto.ca	/home/redacted/vtr-verilog-to-routing/vtr_flow/tasks	61976	8	63	761	824	0	443	149	11	11	121	clb	auto	22.7 MiB	0.22	4463	60.5 MiB	0.11	0.00	3.76649	-161.881	-3.76649	nan	0.19	0.000590885	0.000466147	0.0315968	0.0270149	68	6642	32	4.36541e+06	4.20373e+06	471571.	3897.28	2.80	0.460993	0.396642	6273	24	4716	21787	907950	138607	3.98923	nan	-180.549	-3.98923	0	0	579861.	4792.24	0.12	0.21	0.0712433	0.0650243	
- k6_N10_40nm.xml	  frisc.pre-vpr.blif	  common	  33.81	  vpr	  74.96 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  240	  20	  -1	  -1	  success	  574ed3d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T03:32:29	  gh-actions-runner-vtr-auto-spawned1	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  76764	  20	  116	  3175	  3291	  1	  1254	  376	  18	  18	  324	  clb	  auto	  38.0 MiB	  1.17	  15538	  75.0 MiB	  1.46	  0.02	  7.84117	  -4191.88	  -7.84117	  7.84117	  1.19	  0.0074489	  0.00630636	  0.559765	  0.484374	  68	  26158	  40	  1.37969e+07	  1.29346e+07	  1.39738e+06	  4312.90	  17.07	  4.27847	  3.66049	  21737	  27	  9074	  38700	  2043537	  292479	  8.98443	  8.98443	  -4756.73	  -8.98443	  0	  0	  1.71505e+06	  5293.36	  0.82	  1.17	  0.582609	  0.512788	 
- k6_N10_40nm.xml	  misex3.pre-vpr.blif	  common	  6.79	  vpr	  61.49 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  87	  14	  -1	  -1	  success	  574ed3d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T03:32:29	  gh-actions-runner-vtr-auto-spawned1	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  62968	  14	  14	  828	  842	  0	  488	  115	  12	  12	  144	  clb	  auto	  23.6 MiB	  0.43	  4813	  61.5 MiB	  0.17	  0.01	  4.15972	  -54.4381	  -4.15972	  nan	  0.42	  0.00201964	  0.00169484	  0.0677982	  0.0597447	  50	  7415	  30	  5.3894e+06	  4.68878e+06	  421775.	  2928.99	  2.60	  0.700258	  0.608016	  7122	  38	  6126	  27888	  1140071	  180016	  4.78724	  nan	  -61.1197	  -4.78724	  0	  0	  539713.	  3748.01	  0.20	  0.60	  0.229754	  0.204855	 
- k6_N10_40nm.xml	  pdc.pre-vpr.blif	  common	  34.32	  vpr	  79.66 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  307	  16	  -1	  -1	  success	  574ed3d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T03:32:29	  gh-actions-runner-vtr-auto-spawned1	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  81572	  16	  40	  2839	  2879	  0	  1501	  363	  20	  20	  400	  clb	  auto	  43.2 MiB	  1.57	  25581	  79.7 MiB	  1.81	  0.03	  6.08664	  -222.907	  -6.08664	  nan	  1.56	  0.00929983	  0.00777603	  0.622507	  0.530418	  86	  42950	  30	  1.74617e+07	  1.65455e+07	  2.10771e+06	  5269.28	  20.07	  4.51046	  3.81592	  37535	  22	  13138	  75558	  3768186	  483931	  6.62739	  nan	  -240.231	  -6.62739	  0	  0	  2.64451e+06	  6611.28	  0.82	  1.18	  0.383771	  0.344257	 
- k6_N10_40nm.xml	  s298.pre-vpr.blif	  common	  5.99	  vpr	  60.67 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  77	  4	  -1	  -1	  success	  574ed3d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T03:32:29	  gh-actions-runner-vtr-auto-spawned1	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  62128	  4	  6	  726	  732	  1	  378	  87	  11	  11	  121	  clb	  auto	  23.0 MiB	  0.38	  3746	  60.7 MiB	  0.14	  0.00	  5.69531	  -46.7942	  -5.69531	  5.69531	  0.33	  0.00150828	  0.00126634	  0.0599851	  0.052828	  46	  5716	  28	  4.36541e+06	  4.14984e+06	  324627.	  2682.87	  2.25	  0.603521	  0.526506	  5546	  25	  3653	  18859	  752757	  117703	  6.64257	  6.64257	  -54.8549	  -6.64257	  0	  0	  415439.	  3433.38	  0.15	  0.36	  0.141144	  0.127507	 
- k6_N10_40nm.xml	  s38584.1.pre-vpr.blif	  common	  36.85	  vpr	  84.20 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  368	  38	  -1	  -1	  success	  574ed3d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T03:32:29	  gh-actions-runner-vtr-auto-spawned1	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  86224	  39	  304	  4677	  4982	  1	  2229	  711	  22	  22	  484	  clb	  auto	  47.2 MiB	  1.42	  16136	  84.2 MiB	  2.73	  0.04	  4.49676	  -2912.49	  -4.49676	  4.49676	  1.96	  0.00950826	  0.00810046	  0.843709	  0.7225	  48	  23783	  47	  2.15576e+07	  1.9833e+07	  1.52497e+06	  3150.75	  9.06	  4.19377	  3.60403	  21525	  24	  12017	  33433	  1604566	  281349	  5.25783	  5.25783	  -3268.18	  -5.25783	  0	  0	  1.95947e+06	  4048.49	  0.99	  1.16	  0.704932	  0.625994	 
- k6_N10_40nm.xml	  seq.pre-vpr.blif	  common	  7.85	  vpr	  62.98 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  103	  41	  -1	  -1	  success	  574ed3d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T03:32:29	  gh-actions-runner-vtr-auto-spawned1	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  64492	  41	  35	  1006	  1041	  0	  588	  179	  13	  13	  169	  clb	  auto	  25.5 MiB	  0.53	  6864	  63.0 MiB	  0.31	  0.01	  4.55829	  -122.245	  -4.55829	  nan	  0.45	  0.00216787	  0.00182917	  0.109454	  0.0947367	  60	  11800	  30	  6.52117e+06	  5.55108e+06	  604386.	  3576.25	  3.46	  0.824134	  0.712479	  10420	  28	  5732	  26479	  1133536	  174578	  4.78956	  nan	  -138.554	  -4.78956	  0	  0	  756297.	  4475.13	  0.27	  0.54	  0.205964	  0.18393	 
- k6_N10_40nm.xml	  spla.pre-vpr.blif	  common	  25.10	  vpr	  74.51 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  245	  16	  -1	  -1	  success	  574ed3d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T03:32:29	  gh-actions-runner-vtr-auto-spawned1	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  76300	  16	  46	  2232	  2278	  0	  1154	  307	  18	  18	  324	  clb	  auto	  37.2 MiB	  1.18	  16824	  74.5 MiB	  1.24	  0.02	  5.96403	  -190.27	  -5.96403	  nan	  1.15	  0.00731693	  0.00618791	  0.432052	  0.367843	  66	  28635	  48	  1.37969e+07	  1.3204e+07	  1.36437e+06	  4211.00	  11.57	  2.87708	  2.44999	  26370	  26	  10237	  58399	  2817912	  380547	  6.23707	  nan	  -215.709	  -6.23707	  0	  0	  1.68162e+06	  5190.19	  0.73	  1.48	  0.578526	  0.513502	 
- k6_N10_40nm.xml	  tseng.pre-vpr.blif	  common	  6.11	  vpr	  63.50 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  110	  52	  -1	  -1	  success	  574ed3d-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-5.10.35-v8 x86_64	  2023-02-09T03:32:29	  gh-actions-runner-vtr-auto-spawned1	  /root/vtr-verilog-to-routing/vtr-verilog-to-routing	  65024	  52	  122	  1461	  1583	  1	  509	  284	  13	  13	  169	  clb	  auto	  25.7 MiB	  0.36	  3115	  63.5 MiB	  0.31	  0.01	  4.30484	  -1155.24	  -4.30484	  4.30484	  0.52	  0.00239921	  0.00206728	  0.112625	  0.0977054	  30	  5558	  39	  6.52117e+06	  5.92834e+06	  338182.	  2001.08	  1.60	  0.596931	  0.520382	  4412	  22	  2802	  8038	  312820	  65313	  5.10917	  5.10917	  -1299.77	  -5.10917	  0	  0	  415024.	  2455.76	  0.18	  0.27	  0.172664	  0.155536	 
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	crit_path_total_internal_heap_pushes	crit_path_total_internal_heap_pops	crit_path_total_external_heap_pushes	crit_path_total_external_heap_pops	crit_path_total_external_SOURCE_pushes	crit_path_total_external_SOURCE_pops	crit_path_total_internal_SOURCE_pushes	crit_path_total_internal_SOURCE_pops	crit_path_total_external_SINK_pushes	crit_path_total_external_SINK_pops	crit_path_total_internal_SINK_pushes	crit_path_total_internal_SINK_pops	crit_path_total_external_IPIN_pushes	crit_path_total_external_IPIN_pops	crit_path_total_internal_IPIN_pushes	crit_path_total_internal_IPIN_pops	crit_path_total_external_OPIN_pushes	crit_path_total_external_OPIN_pops	crit_path_total_internal_OPIN_pushes	crit_path_total_internal_OPIN_pops	crit_path_total_external_CHANX_pushes	crit_path_total_external_CHANX_pops	crit_path_total_internal_CHANX_pushes	crit_path_total_internal_CHANX_pops	crit_path_total_external_CHANY_pushes	crit_path_total_external_CHANY_pops	crit_path_total_internal_CHANY_pushes	crit_path_total_internal_CHANY_pops	crit_path_rt_node_SOURCE_pushes	crit_path_rt_node_SINK_pushes	crit_path_rt_node_IPIN_pushes	crit_path_rt_node_OPIN_pushes	crit_path_rt_node_CHANX_pushes	crit_path_rt_node_CHANY_pushes	crit_path_adding_all_rt	crit_path_adding_high_fanout_rt	crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
+k6_N10_40nm.xml	alu4.pre-vpr.blif	common	8.85	vpr	65.21 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	97	14	-1	-1	success	43cb716-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2023-11-29T00:19:13	gh-actions-runner-vtr-auto-spawned48	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	66776	14	8	926	934	0	517	119	12	12	144	clb	auto	27.5 MiB	0.42	5060	9463	1603	7266	594	65.2 MiB	0.23	0.01	4.44089	-32.9892	-4.44089	nan	0.38	0.00254044	0.00222705	0.113656	0.100129	48	7611	34	1.8e+06	1.746e+06	423548.	2941.31	5.13	1.24372	1.08023	11752	84318	-1	6643	26	5088	20390	822141	124311	0	0	822141	124311	14929	8146	0	0	24363	20463	0	0	34606	24369	0	0	81519	23377	0	0	327171	22733	0	0	339553	25223	0	0	14929	0	0	11400	71252	81980	431840	6295	105	4.78771	nan	-35.4033	-4.78771	0	0	546237.	3793.31	0.17	0.43	0.07	-1	-1	0.17	0.178207	0.160578	
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+k6_N10_40nm.xml	misex3.pre-vpr.blif	common	6.42	vpr	64.43 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	86	14	-1	-1	success	43cb716-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2023-11-29T00:19:13	gh-actions-runner-vtr-auto-spawned48	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	65980	14	14	828	842	0	506	114	12	12	144	clb	auto	26.9 MiB	0.39	4991	9498	1639	7280	579	64.4 MiB	0.22	0.00	4.46876	-57.9425	-4.46876	nan	0.36	0.00169352	0.001419	0.104878	0.0923778	48	7962	50	1.8e+06	1.548e+06	423548.	2941.31	2.82	0.779304	0.679838	11752	84318	-1	7361	24	5000	20974	941533	140152	0	0	941533	140152	18439	9485	0	0	24905	21231	0	0	37974	24923	0	0	95734	27820	0	0	369121	26869	0	0	395360	29824	0	0	18439	0	0	17002	66491	87644	526575	3032	82	4.87831	nan	-63.8258	-4.87831	0	0	546237.	3793.31	0.18	0.45	0.08	-1	-1	0.18	0.168237	0.152037	
+k6_N10_40nm.xml	pdc.pre-vpr.blif	common	34.11	vpr	83.09 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	311	16	-1	-1	success	43cb716-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2023-11-29T00:19:13	gh-actions-runner-vtr-auto-spawned48	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	85088	16	40	2839	2879	0	1521	367	20	20	400	clb	auto	46.5 MiB	1.38	25024	75208	19630	52655	2923	83.1 MiB	1.83	0.03	6.30615	-231.732	-6.30615	nan	1.46	0.00913107	0.00764052	0.719912	0.606639	80	41966	37	5.832e+06	5.598e+06	2.04130e+06	5103.26	17.65	4.2229	3.58529	41700	425684	-1	36971	23	13816	80755	4342512	506369	0	0	4342512	506369	54635	21829	0	0	95635	81434	0	0	149387	95650	0	0	262235	67846	0	0	1891530	115938	0	0	1889090	123672	0	0	54635	0	0	62389	489571	521542	2375015	29718	2021	6.62716	nan	-248.252	-6.62716	0	0	2.56833e+06	6420.82	1.16	2.02	0.44	-1	-1	1.16	0.658943	0.57958	
+k6_N10_40nm.xml	s298.pre-vpr.blif	common	5.88	vpr	63.71 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	77	4	-1	-1	success	43cb716-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2023-11-29T00:19:13	gh-actions-runner-vtr-auto-spawned48	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	65240	4	6	726	732	1	405	87	11	11	121	clb	auto	25.9 MiB	0.33	3968	5655	843	4623	189	63.7 MiB	0.16	0.00	6.57849	-52.404	-6.57849	6.57849	0.32	0.00147077	0.0012659	0.0771025	0.0695265	46	6197	32	1.458e+06	1.386e+06	337205.	2786.82	2.45	0.639749	0.561666	9702	66957	-1	5362	24	3319	16618	689562	101885	0	0	689562	101885	13739	5708	0	0	20752	16789	0	0	29932	20775	0	0	70814	18661	0	0	269929	19371	0	0	284396	20581	0	0	13739	0	0	17892	66553	71727	419088	4651	0	7.03332	7.03332	-56.7733	-7.03332	0	0	434556.	3591.37	0.14	0.35	0.06	-1	-1	0.14	0.146613	0.132694	
+k6_N10_40nm.xml	s38584.1.pre-vpr.blif	common	40.28	vpr	87.11 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	376	38	-1	-1	success	43cb716-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2023-11-29T00:19:13	gh-actions-runner-vtr-auto-spawned48	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	89200	39	304	4677	4982	1	2202	719	22	22	484	clb	auto	50.3 MiB	1.25	15904	251801	72090	165646	14065	87.1 MiB	2.55	0.04	5.11515	-2988.21	-5.11515	5.11515	1.84	0.0130429	0.0102585	0.854611	0.714468	48	23477	30	7.2e+06	6.768e+06	1.57648e+06	3257.18	8.51	3.75883	3.21023	40412	322068	-1	21454	23	11443	31954	1678528	267935	0	0	1678528	267935	30368	15963	0	0	43302	35721	0	0	57282	43398	0	0	178188	61387	0	0	648145	54280	0	0	721243	57186	0	0	30368	0	0	23471	41412	42760	265137	1703	1668	5.89175	5.89175	-3342.37	-5.89175	0	0	2.03370e+06	4201.85	0.88	1.12	0.29	-1	-1	0.88	0.627937	0.551619	
+k6_N10_40nm.xml	seq.pre-vpr.blif	common	12.31	vpr	65.94 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	101	41	-1	-1	success	43cb716-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2023-11-29T00:19:13	gh-actions-runner-vtr-auto-spawned48	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	67524	41	35	1006	1041	0	615	177	13	13	169	clb	auto	28.4 MiB	0.51	7055	17537	3342	12249	1946	65.9 MiB	0.29	0.01	4.54382	-128.465	-4.54382	nan	0.49	0.00250396	0.002169	0.112547	0.100094	70	11106	40	2.178e+06	1.818e+06	730287.	4321.22	7.94	1.52535	1.32277	16374	145670	-1	10300	21	5694	26029	1252463	168172	0	0	1252463	168172	23564	10387	0	0	31788	26603	0	0	49451	31813	0	0	103459	30881	0	0	521446	31737	0	0	522755	36751	0	0	23564	0	0	21861	81204	106286	580378	2780	0	4.89633	nan	-138.863	-4.89633	0	0	911935.	5396.06	0.30	0.54	0.14	-1	-1	0.30	0.180571	0.162055	
+k6_N10_40nm.xml	spla.pre-vpr.blif	common	36.45	vpr	77.77 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	241	16	-1	-1	success	43cb716-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2023-11-29T00:19:13	gh-actions-runner-vtr-auto-spawned48	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	79636	16	46	2232	2278	0	1201	303	18	18	324	clb	auto	40.4 MiB	1.07	17239	54204	14031	37076	3097	77.8 MiB	1.20	0.02	5.72672	-199.422	-5.72672	nan	1.16	0.00684016	0.00550636	0.48213	0.402485	70	29848	37	4.608e+06	4.338e+06	1.48298e+06	4577.10	25.11	4.98774	4.18053	31752	300704	-1	25370	21	10274	56745	2833244	351669	0	0	2833244	351669	38665	15227	0	0	69431	57489	0	0	105410	69450	0	0	185552	48558	0	0	1197921	75989	0	0	1236265	84956	0	0	38665	0	0	45159	295888	336083	1476694	20466	1842	6.3426	nan	-218.759	-6.3426	0	0	1.85205e+06	5716.21	0.76	1.35	0.27	-1	-1	0.76	0.482927	0.425167	
+k6_N10_40nm.xml	tseng.pre-vpr.blif	common	5.91	vpr	66.23 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	105	52	-1	-1	success	43cb716-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2023-11-29T00:19:13	gh-actions-runner-vtr-auto-spawned48	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	67816	52	122	1461	1583	1	525	279	13	13	169	clb	auto	28.3 MiB	0.31	3268	48562	12141	33899	2522	66.2 MiB	0.39	0.01	5.07942	-1119.12	-5.07942	5.07942	0.49	0.0026026	0.00235399	0.161243	0.145041	30	5775	40	2.178e+06	1.89e+06	350324.	2072.92	1.69	0.630492	0.560557	12006	67531	-1	4532	28	2786	7936	357048	69089	0	0	357048	69089	6851	4181	0	0	11824	9342	0	0	13727	11831	0	0	44917	16579	0	0	132516	13598	0	0	147213	13558	0	0	6851	0	0	5305	10700	11902	43819	1521	206	5.34055	5.34055	-1240.37	-5.34055	0	0	430798.	2549.10	0.16	0.29	0.06	-1	-1	0.16	0.168159	0.151225	

From 985ebc600177d4c97f48946de3bc3682ee431608 Mon Sep 17 00:00:00 2001
From: amin1377 <amin1377.mohaghegh@gmail.com>
Date: Fri, 16 Aug 2024 09:58:44 -0400
Subject: [PATCH 03/12] [test] update clock alias golden res

---
 .../strong_clock_aliases/config/golden_results.txt        | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt
index 68062e583c5..a5ac81a2c65 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt
@@ -1,4 +1,4 @@
- arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
- timing/k6_N10_40nm.xml	  clock_aliases.blif	  common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	  0.22	  vpr	  56.38 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  4	  1	  -1	  -1	  success	  v8.0.0-6989-g4a9293e1e-dirty	  release IPO VTR_ASSERT_LEVEL=3	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-02-04T01:37:29	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  57728	  1	  4	  28	  32	  2	  10	  9	  4	  4	  16	  clb	  auto	  17.5 MiB	  0.00	  20	  56.4 MiB	  0.00	  0.00	  2.18276	  0	  0	  2.18276	  0.01	  1.8962e-05	  1.3558e-05	  0.000245191	  0.000217063	  8	  18	  4	  215576	  215576	  5503.53	  343.971	  0.01	  0.00299768	  0.00243283	  12	  4	  18	  18	  422	  145	  2.20417	  2.20417	  0	  0	  0	  0	  6317.10	  394.819	  0.00	  0.00	  0.000845095	  0.000768207	 
- timing/k6_N10_40nm.xml	  clock_aliases.blif	  common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	  0.27	  vpr	  56.31 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  4	  1	  -1	  -1	  success	  v8.0.0-6989-g4a9293e1e-dirty	  release IPO VTR_ASSERT_LEVEL=3	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-02-04T01:37:29	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  57664	  1	  4	  28	  32	  2	  10	  9	  4	  4	  16	  clb	  auto	  17.5 MiB	  0.00	  20	  56.3 MiB	  0.00	  0.00	  2.18276	  0	  0	  2.18276	  0.01	  1.974e-05	  1.4252e-05	  0.000246873	  0.0002189	  8	  18	  4	  215576	  215576	  5503.53	  343.971	  0.01	  0.00244336	  0.00196958	  12	  4	  18	  18	  422	  145	  2.20417	  2.20417	  0	  0	  0	  0	  6317.10	  394.819	  0.00	  0.00	  0.000719288	  0.000650332	 
- timing/k6_N10_40nm.xml	  clock_aliases.blif	  common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	  0.29	  vpr	  56.34 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  4	  1	  -1	  -1	  success	  v8.0.0-6989-g4a9293e1e-dirty	  release IPO VTR_ASSERT_LEVEL=3	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-02-04T01:37:29	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  57696	  1	  4	  28	  32	  2	  10	  9	  4	  4	  16	  clb	  auto	  17.5 MiB	  0.01	  20	  56.3 MiB	  0.00	  0.00	  2.18276	  0	  0	  2.18276	  0.01	  1.9454e-05	  1.4029e-05	  0.000249021	  0.000220542	  8	  18	  4	  215576	  215576	  5503.53	  343.971	  0.01	  0.00264112	  0.00212219	  12	  4	  18	  18	  422	  145	  2.20417	  2.20417	  0	  0	  0	  0	  6317.10	  394.819	  0.00	  0.00	  0.000734735	  0.000667954	 
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	0.15	vpr	57.62 MiB	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	-1	782a17c	Release IPO VTR_ASSERT_LEVEL=3	GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64	2024-08-16T12:54:30	-1	-1	59004	1	4	28	32	2	10	9	4	4	16	clb	auto	19.2 MiB	0.00	20	27	15	8	4	57.6 MiB	0.00	0.00	2.44626	0	0	2.44626	0.01	6.1505e-05	5.4271e-05	0.000399345	0.000366854	8	12	5	72000	72000	5593.62	349.601	0.01	0.00469757	0.00398579	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.00	0.00	0.00	-1	-1	0.00	0.0018976	0.00177716	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	0.15	vpr	57.43 MiB	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	-1	782a17c	Release IPO VTR_ASSERT_LEVEL=3	GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64	2024-08-16T12:54:30	-1	-1	58804	1	4	28	32	2	10	9	4	4	16	clb	auto	19.1 MiB	0.00	20	27	15	8	4	57.4 MiB	0.00	0.00	2.44626	0	0	2.44626	0.01	3.5236e-05	2.9806e-05	0.000357366	0.000308936	8	12	5	72000	72000	5593.62	349.601	0.01	0.00440932	0.00372158	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.00	0.00	0.00	-1	-1	0.00	0.00185784	0.00175594	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	0.15	vpr	57.38 MiB	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	-1	782a17c	Release IPO VTR_ASSERT_LEVEL=3	GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64	2024-08-16T12:54:30	-1	-1	58756	1	4	28	32	2	10	9	4	4	16	clb	auto	19.0 MiB	0.00	20	27	15	8	4	57.4 MiB	0.00	0.00	2.44626	0	0	2.44626	0.01	3.5736e-05	3.0076e-05	0.000329113	0.000300139	8	12	5	72000	72000	5593.62	349.601	0.01	0.00439327	0.00372855	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.00	0.00	0.00	-1	-1	0.00	0.00183794	0.00172653	

From 8cab5024e76df0a63fec9634f5e70cfa8c4a7902 Mon Sep 17 00:00:00 2001
From: amin1377 <amin1377.mohaghegh@gmail.com>
Date: Fri, 16 Aug 2024 10:06:11 -0400
Subject: [PATCH 04/12] [test] update odin strong clock alias res

---
 .../strong_clock_aliases/config/golden_results.txt        | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
index 06d1734c750..eed3e3f19b2 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
@@ -1,4 +1,4 @@
- arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
- timing/k6_N10_40nm.xml	  clock_aliases.blif	  common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	  0.54	  vpr	  54.49 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  4	  1	  -1	  -1	  success	  v8.0.0-6793-gb52911b9f	  release IPO VTR_ASSERT_LEVEL=2	  GNU 7.5.0 on Linux-4.15.0-167-generic x86_64	  2022-11-27T15:52:14	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing	  55800	  1	  4	  28	  32	  2	  10	  9	  4	  4	  16	  clb	  auto	  15.8 MiB	  0.03	  20	  54.5 MiB	  0.00	  0.00	  2.18276	  0	  0	  2.18276	  0.02	  2.9141e-05	  2.1776e-05	  0.000384601	  0.00034525	  8	  18	  4	  215576	  215576	  5503.53	  343.971	  0.03	  0.00411474	  0.00340189	  12	  4	  18	  18	  422	  145	  2.20417	  2.20417	  0	  0	  0	  0	  6317.10	  394.819	  0.00	  0.00	  0.000888863	  0.000804989	 
- timing/k6_N10_40nm.xml	  clock_aliases.blif	  common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	  0.66	  vpr	  54.73 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  4	  1	  -1	  -1	  success	  v8.0.0-6793-gb52911b9f	  release IPO VTR_ASSERT_LEVEL=2	  GNU 7.5.0 on Linux-4.15.0-167-generic x86_64	  2022-11-27T15:52:14	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing	  56048	  1	  4	  28	  32	  2	  10	  9	  4	  4	  16	  clb	  auto	  15.9 MiB	  0.02	  20	  54.7 MiB	  0.03	  0.00	  2.18276	  0	  0	  2.18276	  0.02	  5.182e-05	  4.0804e-05	  0.000410032	  0.000361391	  8	  18	  4	  215576	  215576	  5503.53	  343.971	  0.06	  0.00413673	  0.00341089	  12	  4	  18	  18	  422	  145	  2.20417	  2.20417	  0	  0	  0	  0	  6317.10	  394.819	  0.00	  0.00	  0.000908048	  0.000820443	 
- timing/k6_N10_40nm.xml	  clock_aliases.blif	  common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	  0.57	  vpr	  54.77 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  4	  1	  -1	  -1	  success	  v8.0.0-6793-gb52911b9f	  release IPO VTR_ASSERT_LEVEL=2	  GNU 7.5.0 on Linux-4.15.0-167-generic x86_64	  2022-11-27T15:52:14	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing	  56080	  1	  4	  28	  32	  2	  10	  9	  4	  4	  16	  clb	  auto	  15.9 MiB	  0.01	  20	  54.8 MiB	  0.00	  0.00	  2.18276	  0	  0	  2.18276	  0.01	  2.5851e-05	  1.9164e-05	  0.000325142	  0.000288851	  8	  18	  4	  215576	  215576	  5503.53	  343.971	  0.03	  0.0040566	  0.00334035	  12	  4	  18	  18	  422	  145	  2.20417	  2.20417	  0	  0	  0	  0	  6317.10	  394.819	  0.01	  0.00	  0.00112307	  0.0010329	 
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	0.15	vpr	57.62 MiB	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	-1	782a17c	Release IPO VTR_ASSERT_LEVEL=3	GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64	2024-08-16T12:48:04	-1	-1	59008	1	4	28	32	2	10	9	4	4	16	clb	auto	19.2 MiB	0.00	20	27	15	8	4	57.6 MiB	0.00	0.00	2.44626	0	0	2.44626	0.01	3.6649e-05	3.0788e-05	0.000332461	0.000302474	8	12	5	72000	72000	5593.62	349.601	0.01	0.00463095	0.00390158	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.00	0.00	0.00	-1	-1	0.00	0.00184241	0.00173742	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	0.15	vpr	57.50 MiB	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	-1	782a17c	Release IPO VTR_ASSERT_LEVEL=3	GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64	2024-08-16T12:48:04	-1	-1	58880	1	4	28	32	2	10	9	4	4	16	clb	auto	19.1 MiB	0.00	20	27	15	8	4	57.5 MiB	0.00	0.00	2.44626	0	0	2.44626	0.01	3.6368e-05	3.0868e-05	0.000334423	0.000304918	8	12	5	72000	72000	5593.62	349.601	0.01	0.00434957	0.00368628	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.00	0.00	0.00	-1	-1	0.00	0.00187403	0.00175995	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	0.15	vpr	57.37 MiB	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	-1	782a17c	Release IPO VTR_ASSERT_LEVEL=3	GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64	2024-08-16T12:48:04	-1	-1	58748	1	4	28	32	2	10	9	4	4	16	clb	auto	19.1 MiB	0.00	20	27	15	8	4	57.4 MiB	0.00	0.00	2.44626	0	0	2.44626	0.01	3.6097e-05	3.0537e-05	0.000332419	0.000303054	8	12	5	72000	72000	5593.62	349.601	0.01	0.00433458	0.00365113	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.00	0.00	0.00	-1	-1	0.00	0.00181848	0.00171448	

From d18caa1c6c070df26a48426f913dbcf08872007d Mon Sep 17 00:00:00 2001
From: amin1377 <amin1377.mohaghegh@gmail.com>
Date: Thu, 22 Aug 2024 19:34:30 -0400
Subject: [PATCH 05/12] update nightly test1 golden

---
 .../config/golden_results.txt                 | 38 +++++++++----------
 .../config/golden_results.txt                 | 38 +++++++++----------
 2 files changed, 38 insertions(+), 38 deletions(-)

diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
index 8157d1a7724..4a1e9b67c4e 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
@@ -1,20 +1,20 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-k6_N10_40nm.xml	alu4.pre-vpr.blif	common	7.21	vpr	65.09 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	96	14	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:20	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	66652	14	8	926	934	0	478	118	12	12	144	clb	auto	27.6 MiB	0.39	4805	7921	1196	6264	461	65.1 MiB	0.16	0.00	4.7509	-33.2503	-4.7509	nan	0.36	0.00190138	0.00162009	0.0688365	0.0606739	74	6597	21	5.3894e+06	5.17382e+06	608941.	4228.75	4.36	0.724831	0.62564	14184	119952	-1	6717	44	4137	20437	842824	113986	4.58526	nan	-32.9374	-4.58526	0	0	758555.	5267.75	0.15	0.25	0.07	-1	-1	0.15	0.111914	0.0993596	
-k6_N10_40nm.xml	apex2.pre-vpr.blif	common	11.41	vpr	67.08 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	114	38	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:20	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	68692	39	3	1113	1117	0	655	156	13	13	169	clb	auto	29.4 MiB	0.52	7970	14402	2695	10284	1423	67.1 MiB	0.31	0.01	5.67046	-16.7656	-5.67046	nan	0.44	0.00272498	0.0023725	0.117567	0.10279	74	12212	25	6.52117e+06	6.14392e+06	728195.	4308.85	7.04	1.29022	1.10763	16710	144151	-1	12100	18	6056	29564	1238130	177195	5.46327	nan	-16.0252	-5.46327	0	0	906856.	5366.01	0.29	0.45	0.14	-1	-1	0.29	0.156952	0.142444	
-k6_N10_40nm.xml	apex4.pre-vpr.blif	common	7.42	vpr	65.21 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	95	9	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:20	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	66780	9	19	897	916	0	536	123	12	12	144	clb	auto	27.4 MiB	0.43	6343	9578	1685	7369	524	65.2 MiB	0.20	0.01	4.76124	-79.5577	-4.76124	nan	0.35	0.00213426	0.00181729	0.0770497	0.0677823	62	10552	34	5.3894e+06	5.11993e+06	523024.	3632.11	4.01	0.784997	0.679634	13040	101000	-1	9514	34	6114	31519	1235789	184059	5.08979	nan	-80.98	-5.08979	0	0	643745.	4470.45	0.22	0.52	0.10	-1	-1	0.22	0.192852	0.171041	
-k6_N10_40nm.xml	bigkey.pre-vpr.blif	common	8.34	vpr	66.71 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	94	229	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:20	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	68312	263	197	1372	1603	1	490	554	17	17	289	io	auto	28.7 MiB	0.31	4429	175652	50348	113731	11573	66.7 MiB	0.75	0.02	2.82334	-708.457	-2.82334	2.82334	0.85	0.00300682	0.00269253	0.247317	0.22094	34	7778	18	1.21262e+07	5.06604e+06	661981.	2290.59	3.56	0.96314	0.863927	21366	128092	-1	7371	18	2453	11694	676065	127375	3.03973	3.03973	-763.206	-3.03973	0	0	811075.	2806.49	0.32	0.31	0.12	-1	-1	0.32	0.139942	0.127415	
-k6_N10_40nm.xml	clma.pre-vpr.blif	common	36.92	vpr	100.13 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	380	62	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:20	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	102536	383	82	3674	4077	1	2327	845	22	22	484	clb	auto	53.8 MiB	1.83	30495	408131	149393	204426	54312	91.0 MiB	4.41	0.03	8.38463	-355.215	-8.38463	8.38463	1.59	0.00553376	0.00482363	1.10718	0.941379	86	48680	35	2.15576e+07	2.04797e+07	2.58188e+06	5334.46	19.54	3.95042	3.31869	52488	536144	-1	43642	27	20275	90858	4018144	545419	8.17711	8.17711	-353.933	-8.17711	0	0	3.23937e+06	6692.90	0.78	1.10	0.32	-1	-1	0.78	0.412432	0.36509	
-k6_N10_40nm.xml	des.pre-vpr.blif	common	7.33	vpr	64.82 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	99	256	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:20	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	66380	256	245	954	1199	0	610	600	18	18	324	io	auto	26.8 MiB	0.24	4908	149811	41746	100723	7342	64.8 MiB	0.56	0.01	3.98472	-745.824	-3.98472	nan	0.95	0.002533	0.00233963	0.161563	0.149504	32	8452	46	1.37969e+07	5.33551e+06	718733.	2218.31	2.56	0.640485	0.5926	23676	138656	-1	7309	16	2635	6179	382431	81452	4.25723	nan	-787.373	-4.25723	0	0	879796.	2715.42	0.36	0.21	0.13	-1	-1	0.36	0.106126	0.0991908	
-k6_N10_40nm.xml	diffeq.pre-vpr.blif	common	5.71	vpr	65.49 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	97	64	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:20	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	67064	64	39	1371	1410	1	553	200	12	12	144	clb	auto	27.6 MiB	0.34	3782	22392	4498	16716	1178	65.5 MiB	0.25	0.01	5.76255	-1080.02	-5.76255	5.76255	0.36	0.00236145	0.00203563	0.102983	0.0912687	46	5161	24	5.3894e+06	5.22772e+06	394751.	2741.33	1.69	0.633809	0.550745	11608	77537	-1	5089	24	3148	10672	380947	63653	5.40496	5.40496	-1070.98	-5.40496	0	0	505417.	3509.84	0.17	0.25	0.07	-1	-1	0.17	0.142657	0.127941	
-k6_N10_40nm.xml	dsip.pre-vpr.blif	common	9.03	vpr	66.61 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	95	229	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:20	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	68208	229	197	1370	1567	1	535	521	16	16	256	io	auto	28.7 MiB	0.32	4249	145076	42098	96002	6976	66.6 MiB	0.69	0.01	2.82038	-687.741	-2.82038	2.82038	0.71	0.00278869	0.00251961	0.222451	0.198857	34	7820	28	1.05632e+07	5.11993e+06	580208.	2266.44	4.63	0.965895	0.865428	18880	112045	-1	7420	18	2762	9849	588259	120916	2.94626	2.94626	-745.332	-2.94626	0	0	710900.	2776.95	0.27	0.28	0.10	-1	-1	0.27	0.137157	0.125437	
-k6_N10_40nm.xml	elliptic.pre-vpr.blif	common	25.44	vpr	78.20 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	230	131	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:20	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	80080	131	114	3421	3535	1	1217	475	18	18	324	clb	auto	41.1 MiB	0.96	11435	128263	36626	85751	5886	78.2 MiB	1.31	0.02	7.47596	-4443.09	-7.47596	7.47596	0.95	0.00614289	0.00546322	0.48079	0.413918	50	20115	48	1.37969e+07	1.23956e+07	1.02665e+06	3168.68	12.14	2.63609	2.25374	27232	203968	-1	16697	23	7740	32519	1480622	220162	7.27428	7.27428	-4524.79	-7.27428	0	0	1.31637e+06	4062.87	0.50	0.76	0.20	-1	-1	0.50	0.391654	0.347969	
-k6_N10_40nm.xml	ex1010.pre-vpr.blif	common	36.12	vpr	85.68 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	302	10	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:20	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	87736	10	10	2659	2669	0	1417	322	20	20	400	clb	auto	45.3 MiB	1.53	26735	58781	15782	41072	1927	82.0 MiB	1.36	0.02	6.79311	-65.8142	-6.79311	nan	1.26	0.00790626	0.00655989	0.45956	0.389002	98	46081	40	1.74617e+07	1.6276e+07	2.35420e+06	5885.50	26.21	3.66603	3.08292	46488	495728	-1	40094	26	13124	79778	4200582	472080	6.72249	nan	-64.7071	-6.72249	0	0	2.96690e+06	7417.26	0.70	0.97	0.30	-1	-1	0.70	0.301	0.268194	
-k6_N10_40nm.xml	ex5p.pre-vpr.blif	common	8.16	vpr	63.91 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	78	8	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:20	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	65440	8	63	761	824	0	443	149	11	11	121	clb	auto	26.1 MiB	0.33	4420	9999	1667	7706	626	63.9 MiB	0.15	0.00	4.13681	-180.38	-4.13681	nan	0.29	0.00162574	0.00140448	0.0573666	0.0510513	68	6844	29	4.36541e+06	4.20373e+06	471571.	3897.28	5.40	0.972863	0.839418	11382	90811	-1	6299	27	3950	17583	680545	104378	4.04861	nan	-185.982	-4.04861	0	0	579861.	4792.24	0.19	0.31	0.09	-1	-1	0.19	0.131733	0.118193	
-k6_N10_40nm.xml	frisc.pre-vpr.blif	common	27.72	vpr	78.53 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	240	20	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:20	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	80412	20	116	3175	3291	1	1254	376	18	18	324	clb	auto	41.2 MiB	0.96	14937	83092	21035	56910	5147	78.5 MiB	1.17	0.02	9.37137	-4836.23	-9.37137	9.37137	0.99	0.00592225	0.00528715	0.438554	0.382925	66	23239	30	1.37969e+07	1.29346e+07	1.36437e+06	4211.00	13.84	3.3299	2.8475	30784	270180	-1	20879	24	8723	36885	1817074	266114	9.12568	9.12568	-4847.74	-9.12568	0	0	1.68162e+06	5190.19	0.59	0.84	0.27	-1	-1	0.59	0.397344	0.351977	
-k6_N10_40nm.xml	misex3.pre-vpr.blif	common	7.60	vpr	64.73 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	87	14	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:20	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	66280	14	14	828	842	0	488	115	12	12	144	clb	auto	26.9 MiB	0.36	4941	5695	788	4522	385	64.7 MiB	0.13	0.00	4.69826	-60.2129	-4.69826	nan	0.36	0.00170664	0.00147133	0.0572936	0.0509496	54	8009	47	5.3894e+06	4.68878e+06	451357.	3134.42	4.30	0.924117	0.797498	12324	89954	-1	7171	21	4179	17710	662276	104535	4.54449	nan	-60.4911	-4.54449	0	0	586610.	4073.68	0.19	0.29	0.09	-1	-1	0.19	0.124236	0.112554	
-k6_N10_40nm.xml	pdc.pre-vpr.blif	common	29.89	vpr	82.92 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	307	16	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:20	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	84912	16	40	2839	2879	0	1501	363	20	20	400	clb	auto	46.4 MiB	1.31	24796	68945	17552	48401	2992	82.9 MiB	1.38	0.02	7.00232	-251.23	-7.00232	nan	1.21	0.00652942	0.00561975	0.453795	0.382384	80	44574	39	1.74617e+07	1.65455e+07	1.96642e+06	4916.06	16.16	3.20485	2.70123	41700	405380	-1	36503	18	12436	74071	3266555	428458	6.7432	nan	-249.933	-6.7432	0	0	2.46811e+06	6170.27	0.94	1.30	0.42	-1	-1	0.94	0.437431	0.392854	
-k6_N10_40nm.xml	s298.pre-vpr.blif	common	4.64	vpr	63.79 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	77	4	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:20	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	65316	4	6	726	732	1	378	87	11	11	121	clb	auto	26.1 MiB	0.30	3693	3735	430	3194	111	63.8 MiB	0.10	0.00	6.30858	-51.7143	-6.30858	6.30858	0.27	0.00174803	0.00148525	0.0451667	0.0404791	44	6200	32	4.36541e+06	4.14984e+06	309216.	2555.51	1.64	0.405195	0.352697	9582	61621	-1	5457	22	3588	18601	711043	111359	6.51519	6.51519	-54.7562	-6.51519	0	0	401578.	3318.83	0.12	0.26	0.06	-1	-1	0.12	0.106611	0.0963338	
-k6_N10_40nm.xml	s38584.1.pre-vpr.blif	common	31.21	vpr	87.25 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	368	38	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:20	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	89348	39	304	4677	4982	1	2229	711	22	22	484	clb	auto	50.4 MiB	1.17	15892	248127	72238	162853	13036	87.3 MiB	2.40	0.03	5.02641	-3215.78	-5.02641	5.02641	1.57	0.00844683	0.00754098	0.749422	0.648136	44	24233	33	2.15576e+07	1.9833e+07	1.41060e+06	2914.46	7.76	3.1785	2.75583	39444	288878	-1	21443	23	12112	33710	1370500	248738	5.15976	5.15976	-3289.71	-5.15976	0	0	1.82601e+06	3772.76	0.73	0.91	0.28	-1	-1	0.73	0.543496	0.483827	
-k6_N10_40nm.xml	seq.pre-vpr.blif	common	7.61	vpr	65.78 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	103	41	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:20	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	67356	41	35	1006	1041	0	588	179	13	13	169	clb	auto	28.2 MiB	0.47	6846	17819	3270	12655	1894	65.8 MiB	0.27	0.01	4.96104	-139.99	-4.96104	nan	0.43	0.00209503	0.00179479	0.0985096	0.0867435	56	12202	44	6.52117e+06	5.55108e+06	559864.	3312.80	3.70	0.750444	0.65127	14694	110679	-1	10652	23	5478	25529	1041333	159644	4.77402	nan	-140.731	-4.77402	0	0	714795.	4229.55	0.24	0.41	0.11	-1	-1	0.24	0.151125	0.136708	
-k6_N10_40nm.xml	spla.pre-vpr.blif	common	29.32	vpr	77.64 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	245	16	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:20	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	79508	16	46	2232	2278	0	1154	307	18	18	324	clb	auto	40.3 MiB	1.01	17066	52057	12539	36561	2957	77.6 MiB	0.98	0.02	6.1923	-216.925	-6.1923	nan	0.96	0.00511679	0.00441538	0.341779	0.291619	70	29237	30	1.37969e+07	1.3204e+07	1.42834e+06	4408.47	18.56	3.25549	2.73837	31752	286880	-1	25273	21	9773	55725	2341275	316396	6.1326	nan	-216.962	-6.1326	0	0	1.78317e+06	5503.60	0.64	1.01	0.30	-1	-1	0.64	0.364275	0.325415	
-k6_N10_40nm.xml	tseng.pre-vpr.blif	common	6.63	vpr	66.31 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	110	52	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:20	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	67900	52	122	1461	1583	1	509	284	13	13	169	clb	auto	28.5 MiB	0.29	3129	40403	8633	29315	2455	66.3 MiB	0.30	0.01	5.00636	-1311.79	-5.00636	5.00636	0.45	0.00228655	0.00204201	0.110733	0.0982164	32	5107	32	6.52117e+06	5.92834e+06	352895.	2088.14	2.83	0.847248	0.735343	12174	67024	-1	4717	29	2763	8262	352580	70758	4.58906	4.58906	-1300.62	-4.58906	0	0	431135.	2551.09	0.16	0.23	0.06	-1	-1	0.16	0.140174	0.124654	
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+k6_N10_40nm.xml	apex2.pre-vpr.blif	common	11.54	vpr	67.02 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	115	38	-1	-1	success	ee5eb02-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-16T14:20:57	gh-actions-runner-vtr-auto-spawned31	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	68632	39	3	1113	1117	0	675	157	13	13	169	clb	auto	29.5 MiB	0.52	7879	13693	2337	10136	1220	67.0 MiB	0.28	0.01	6.02154	-17.5859	-6.02154	nan	0.45	0.00275834	0.00233622	0.107502	0.0951802	62	13086	48	2.178e+06	2.07e+06	652532.	3861.14	7.21	1.37926	1.19039	15366	127615	-1	11563	30	6785	30387	1264252	174643	5.82632	nan	-17.1242	-5.82632	0	0	801739.	4744.02	0.26	0.57	0.12	-1	-1	0.26	0.221433	0.19916	
+k6_N10_40nm.xml	apex4.pre-vpr.blif	common	7.06	vpr	65.45 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	95	9	-1	-1	success	ee5eb02-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-16T14:20:57	gh-actions-runner-vtr-auto-spawned31	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	67016	9	19	897	916	0	569	123	12	12	144	clb	auto	27.7 MiB	0.44	6709	9578	1569	7337	672	65.4 MiB	0.22	0.01	5.16784	-84.6504	-5.16784	nan	0.36	0.00241558	0.0020605	0.0899188	0.0795928	62	10796	38	1.8e+06	1.71e+06	546237.	3793.31	3.62	0.755057	0.654516	13040	106280	-1	9528	24	5403	25371	1032193	149160	5.31039	nan	-84.6173	-5.31039	0	0	671089.	4660.34	0.22	0.44	0.10	-1	-1	0.22	0.163682	0.147834	
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+k6_N10_40nm.xml	des.pre-vpr.blif	common	9.79	vpr	64.66 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	101	256	-1	-1	success	ee5eb02-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-16T14:20:57	gh-actions-runner-vtr-auto-spawned31	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	66208	256	245	954	1199	0	613	602	18	18	324	io	auto	26.5 MiB	0.23	4828	140357	37125	96029	7203	64.7 MiB	0.54	0.01	4.31026	-789.244	-4.31026	nan	1.00	0.00288301	0.00272449	0.170722	0.158812	34	7705	26	4.608e+06	1.818e+06	779010.	2404.35	4.97	1.01926	0.945251	24000	152888	-1	7130	18	2525	6134	402061	81348	4.49788	nan	-806.729	-4.49788	0	0	956463.	2952.05	0.37	0.23	0.13	-1	-1	0.37	0.120003	0.112271	
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+k6_N10_40nm.xml	dsip.pre-vpr.blif	common	9.22	vpr	66.58 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	97	229	-1	-1	success	ee5eb02-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-16T14:20:57	gh-actions-runner-vtr-auto-spawned31	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	68180	229	197	1370	1567	1	538	523	16	16	256	io	auto	28.6 MiB	0.34	4639	156367	46237	102482	7648	66.6 MiB	0.78	0.01	3.20322	-726.151	-3.20322	3.20322	0.78	0.00314855	0.00281952	0.245995	0.219734	34	8368	47	3.528e+06	1.746e+06	604079.	2359.69	4.62	1.11544	1.00073	18880	118149	-1	7459	13	2689	9149	571229	113616	3.28489	3.28489	-779.779	-3.28489	0	0	742044.	2898.61	0.29	0.26	0.11	-1	-1	0.29	0.115099	0.106741	
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+k6_N10_40nm.xml	ex1010.pre-vpr.blif	common	38.22	vpr	82.20 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	299	10	-1	-1	success	ee5eb02-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-16T14:20:57	gh-actions-runner-vtr-auto-spawned31	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	84168	10	10	2659	2669	0	1414	319	20	20	400	clb	auto	45.7 MiB	1.52	26670	58036	15610	40440	1986	82.2 MiB	1.37	0.02	6.99148	-66.5608	-6.99148	nan	1.34	0.00734998	0.00639376	0.47292	0.399553	90	47190	31	5.832e+06	5.382e+06	2.27845e+06	5696.13	28.00	3.11918	2.60796	44092	472493	-1	40435	27	13453	81187	4495090	507770	6.68929	nan	-64.8044	-6.68929	0	0	2.84047e+06	7101.17	0.71	1.14	0.29	-1	-1	0.71	0.336474	0.299193	
+k6_N10_40nm.xml	ex5p.pre-vpr.blif	common	8.49	vpr	63.87 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	82	8	-1	-1	success	ee5eb02-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-16T14:20:57	gh-actions-runner-vtr-auto-spawned31	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	65400	8	63	761	824	0	451	153	12	12	144	clb	auto	26.1 MiB	0.31	4564	13650	2467	10070	1113	63.9 MiB	0.19	0.01	4.36001	-198.144	-4.36001	nan	0.36	0.00202315	0.00175635	0.0754293	0.0662608	46	8116	47	1.8e+06	1.476e+06	409728.	2845.33	5.59	1.04053	0.898087	11608	81817	-1	7004	30	4945	21003	896494	141905	4.47246	nan	-203.996	-4.47246	0	0	527971.	3666.47	0.17	0.37	0.07	-1	-1	0.17	0.142673	0.127129	
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+k6_N10_40nm.xml	misex3.pre-vpr.blif	common	7.52	vpr	64.44 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	86	14	-1	-1	success	ee5eb02-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-16T14:20:57	gh-actions-runner-vtr-auto-spawned31	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	65988	14	14	828	842	0	506	114	12	12	144	clb	auto	26.8 MiB	0.36	4946	8118	1259	6320	539	64.4 MiB	0.18	0.00	4.99427	-64.5608	-4.99427	nan	0.38	0.00202505	0.0017544	0.076652	0.0683471	50	7449	35	1.8e+06	1.548e+06	439064.	3049.06	4.16	0.859461	0.745897	11896	86528	-1	6915	25	4736	20579	777903	117189	4.85973	nan	-63.5848	-4.85973	0	0	562980.	3909.58	0.18	0.32	0.08	-1	-1	0.18	0.128932	0.1166	
+k6_N10_40nm.xml	pdc.pre-vpr.blif	common	31.39	vpr	83.04 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	311	16	-1	-1	success	ee5eb02-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-16T14:20:57	gh-actions-runner-vtr-auto-spawned31	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	85032	16	40	2839	2879	0	1521	367	20	20	400	clb	auto	46.5 MiB	1.32	24941	68643	17504	47903	3236	83.0 MiB	1.50	0.03	7.11101	-257.274	-7.11101	nan	1.32	0.00814889	0.00674352	0.494696	0.420888	78	41725	45	5.832e+06	5.598e+06	2.00674e+06	5016.85	17.98	3.39922	2.87425	41300	418538	-1	35794	21	11768	65698	3038822	387442	7.18904	nan	-255.486	-7.18904	0	0	2.53133e+06	6328.34	0.99	1.44	0.44	-1	-1	0.99	0.539876	0.484595	
+k6_N10_40nm.xml	s298.pre-vpr.blif	common	5.07	vpr	63.72 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	77	4	-1	-1	success	ee5eb02-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-16T14:20:57	gh-actions-runner-vtr-auto-spawned31	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	65248	4	6	726	732	1	405	87	11	11	121	clb	auto	26.1 MiB	0.31	3932	4503	604	3722	177	63.7 MiB	0.12	0.00	7.20975	-57.1746	-7.20975	7.20975	0.29	0.00160903	0.00138311	0.0565681	0.0504102	44	6222	32	1.458e+06	1.386e+06	324964.	2685.65	2.03	0.544024	0.472793	9582	65203	-1	5554	23	3368	16222	637492	96172	6.94914	6.94914	-58.3727	-6.94914	0	0	420935.	3478.80	0.13	0.28	0.05	-1	-1	0.13	0.123093	0.110761	
+k6_N10_40nm.xml	s38584.1.pre-vpr.blif	common	37.83	vpr	87.75 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	376	38	-1	-1	success	ee5eb02-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-16T14:20:57	gh-actions-runner-vtr-auto-spawned31	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	89856	39	304	4677	4982	1	2202	719	22	22	484	clb	auto	50.4 MiB	1.17	15134	255020	73345	166893	14782	87.8 MiB	2.42	0.03	5.66276	-3253.04	-5.66276	5.66276	1.70	0.00802743	0.00713342	0.736128	0.638028	40	23370	39	7.2e+06	6.768e+06	1.34575e+06	2780.48	12.71	4.12792	3.53956	37996	272632	-1	21030	29	11717	32882	1453579	252466	5.64983	5.64983	-3333.79	-5.64983	0	0	1.68761e+06	3486.79	0.69	1.00	0.26	-1	-1	0.69	0.594158	0.523275	
+k6_N10_40nm.xml	seq.pre-vpr.blif	common	10.51	vpr	66.10 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	101	41	-1	-1	success	ee5eb02-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-16T14:20:57	gh-actions-runner-vtr-auto-spawned31	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	67684	41	35	1006	1041	0	615	177	13	13	169	clb	auto	28.5 MiB	0.48	6961	16049	2946	11365	1738	66.1 MiB	0.28	0.01	5.03195	-143.664	-5.03195	nan	0.44	0.0026392	0.0023032	0.104441	0.0926794	60	12020	38	2.178e+06	1.818e+06	630658.	3731.70	6.55	1.20996	1.04611	15198	124941	-1	10354	24	5139	23293	962130	137023	5.06992	nan	-144.115	-5.06992	0	0	788291.	4664.44	0.26	0.42	0.12	-1	-1	0.26	0.167051	0.150709	
+k6_N10_40nm.xml	spla.pre-vpr.blif	common	20.31	vpr	77.93 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	241	16	-1	-1	success	ee5eb02-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-16T14:20:57	gh-actions-runner-vtr-auto-spawned31	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	79800	16	46	2232	2278	0	1201	303	18	18	324	clb	auto	40.5 MiB	1.02	17032	51153	12014	36600	2539	77.9 MiB	1.10	0.02	6.29481	-217.773	-6.29481	nan	1.01	0.00692542	0.00584914	0.405951	0.347549	70	30122	46	4.608e+06	4.338e+06	1.48298e+06	4577.10	9.27	2.30812	1.96597	31752	300704	-1	25154	21	9819	54210	2459519	309528	6.20862	nan	-218.942	-6.20862	0	0	1.85205e+06	5716.21	0.68	1.04	0.30	-1	-1	0.68	0.377258	0.335776	
+k6_N10_40nm.xml	tseng.pre-vpr.blif	common	6.73	vpr	66.39 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	105	52	-1	-1	success	ee5eb02-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-16T14:20:57	gh-actions-runner-vtr-auto-spawned31	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	67984	52	122	1461	1583	1	525	279	13	13	169	clb	auto	28.5 MiB	0.30	3192	45829	11147	32251	2431	66.4 MiB	0.38	0.01	5.68935	-1256.78	-5.68935	5.68935	0.45	0.00301241	0.00265536	0.153193	0.135734	30	5287	29	2.178e+06	1.89e+06	350324.	2072.92	2.78	0.871199	0.757648	12006	67531	-1	4334	25	2585	6950	258089	51105	5.34065	5.34065	-1250.43	-5.34065	0	0	430798.	2549.10	0.16	0.21	0.06	-1	-1	0.16	0.136378	0.121702	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt
index 7d481319553..d627c7d0b85 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt
@@ -1,20 +1,20 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-k6_N10_40nm.xml	alu4.pre-vpr.blif	common	9.29	vpr	65.08 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	96	14	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:13	gh-actions-runner-vtr-auto-spawned84	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	66644	14	8	926	934	0	478	118	12	12	144	clb	auto	27.6 MiB	0.41	4805	7921	1196	6264	461	65.1 MiB	0.18	0.01	4.7509	-33.2503	-4.7509	nan	0.36	0.00245534	0.00218398	0.0861248	0.0762105	74	6597	21	5.3894e+06	5.17382e+06	608941.	4228.75	6.03	1.1052	0.963163	14184	119952	-1	6717	44	4137	20437	842824	113986	4.58526	nan	-32.9374	-4.58526	0	0	758555.	5267.75	0.22	0.28	0.12	-1	-1	0.22	0.124145	0.110592	
-k6_N10_40nm.xml	apex2.pre-vpr.blif	common	8.94	vpr	67.36 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	114	38	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:13	gh-actions-runner-vtr-auto-spawned84	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	68972	39	3	1113	1117	0	655	156	13	13	169	clb	auto	29.7 MiB	0.53	7970	14402	2695	10284	1423	67.4 MiB	0.30	0.01	5.67046	-16.7656	-5.67046	nan	0.44	0.00249151	0.00212297	0.115197	0.101904	74	12212	25	6.52117e+06	6.14392e+06	728195.	4308.85	5.41	0.941858	0.815146	16710	144151	-1	12100	18	6056	29564	1238130	177195	5.46327	nan	-16.0252	-5.46327	0	0	906856.	5366.01	0.19	0.29	0.08	-1	-1	0.19	0.0956231	0.0877335	
-k6_N10_40nm.xml	apex4.pre-vpr.blif	common	7.93	vpr	65.52 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	95	9	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:13	gh-actions-runner-vtr-auto-spawned84	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	67096	9	19	897	916	0	536	123	12	12	144	clb	auto	27.8 MiB	0.45	6343	9578	1685	7369	524	65.5 MiB	0.23	0.01	4.76124	-79.5577	-4.76124	nan	0.36	0.00226599	0.00196452	0.0943993	0.0837185	62	10552	34	5.3894e+06	5.11993e+06	523024.	3632.11	4.35	0.89265	0.774996	13040	101000	-1	9514	34	6114	31519	1235789	184059	5.08979	nan	-80.98	-5.08979	0	0	643745.	4470.45	0.21	0.57	0.10	-1	-1	0.21	0.212584	0.188789	
-k6_N10_40nm.xml	bigkey.pre-vpr.blif	common	8.57	vpr	66.60 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	94	229	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:13	gh-actions-runner-vtr-auto-spawned84	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	68196	263	197	1372	1603	1	490	554	17	17	289	io	auto	28.6 MiB	0.32	4429	175652	50348	113731	11573	66.6 MiB	0.78	0.02	2.82334	-708.457	-2.82334	2.82334	0.89	0.00309848	0.00277799	0.251899	0.224174	34	7778	18	1.21262e+07	5.06604e+06	661981.	2290.59	3.59	0.946112	0.847675	21366	128092	-1	7371	18	2453	11694	676065	127375	3.03973	3.03973	-763.206	-3.03973	0	0	811075.	2806.49	0.31	0.31	0.12	-1	-1	0.31	0.133578	0.12208	
-k6_N10_40nm.xml	clma.pre-vpr.blif	common	42.14	vpr	100.22 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	380	62	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:13	gh-actions-runner-vtr-auto-spawned84	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	102628	383	82	3674	4077	1	2327	845	22	22	484	clb	auto	53.9 MiB	1.73	30495	408131	149393	204426	54312	91.1 MiB	4.72	0.05	8.38463	-355.215	-8.38463	8.38463	1.71	0.0104313	0.00935194	1.25162	1.04414	86	48680	35	2.15576e+07	2.04797e+07	2.58188e+06	5334.46	24.07	5.1352	4.28764	52488	536144	-1	43642	27	20275	90858	4018144	545419	8.17711	8.17711	-353.933	-8.17711	0	0	3.23937e+06	6692.90	0.85	1.18	0.33	-1	-1	0.85	0.436135	0.383384	
-k6_N10_40nm.xml	des.pre-vpr.blif	common	7.63	vpr	64.74 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	99	256	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:13	gh-actions-runner-vtr-auto-spawned84	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	66292	256	245	954	1199	0	610	600	18	18	324	io	auto	26.8 MiB	0.25	4908	149811	41746	100723	7342	64.7 MiB	0.59	0.01	3.98472	-745.824	-3.98472	nan	1.02	0.00279852	0.00260384	0.181571	0.168921	32	8452	46	1.37969e+07	5.33551e+06	718733.	2218.31	2.72	0.697381	0.647433	23676	138656	-1	7309	16	2635	6179	382431	81452	4.25723	nan	-787.373	-4.25723	0	0	879796.	2715.42	0.35	0.22	0.12	-1	-1	0.35	0.11147	0.104644	
-k6_N10_40nm.xml	diffeq.pre-vpr.blif	common	5.96	vpr	65.98 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	97	64	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:13	gh-actions-runner-vtr-auto-spawned84	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	67564	64	39	1371	1410	1	553	200	12	12	144	clb	auto	28.1 MiB	0.33	3782	22392	4498	16716	1178	66.0 MiB	0.28	0.01	5.76255	-1080.02	-5.76255	5.76255	0.39	0.00268109	0.00242071	0.122136	0.108269	46	5161	24	5.3894e+06	5.22772e+06	394751.	2741.33	1.80	0.696206	0.60919	11608	77537	-1	5089	24	3148	10672	380947	63653	5.40496	5.40496	-1070.98	-5.40496	0	0	505417.	3509.84	0.17	0.25	0.08	-1	-1	0.17	0.143015	0.128603	
-k6_N10_40nm.xml	dsip.pre-vpr.blif	common	9.46	vpr	66.47 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	95	229	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:13	gh-actions-runner-vtr-auto-spawned84	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	68068	229	197	1370	1567	1	535	521	16	16	256	io	auto	28.5 MiB	0.33	4249	145076	42098	96002	6976	66.5 MiB	0.71	0.01	2.82038	-687.741	-2.82038	2.82038	0.74	0.00305502	0.00278554	0.230386	0.204932	34	7820	28	1.05632e+07	5.11993e+06	580208.	2266.44	4.88	1.03291	0.925929	18880	112045	-1	7420	18	2762	9849	588259	120916	2.94626	2.94626	-745.332	-2.94626	0	0	710900.	2776.95	0.30	0.34	0.10	-1	-1	0.30	0.158768	0.144045	
-k6_N10_40nm.xml	elliptic.pre-vpr.blif	common	26.78	vpr	78.45 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	230	131	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:13	gh-actions-runner-vtr-auto-spawned84	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	80328	131	114	3421	3535	1	1217	475	18	18	324	clb	auto	41.3 MiB	0.99	11435	128263	36626	85751	5886	78.4 MiB	1.41	0.02	7.47596	-4443.09	-7.47596	7.47596	1.05	0.00689155	0.00617445	0.553306	0.477884	50	20115	48	1.37969e+07	1.23956e+07	1.02665e+06	3168.68	13.47	3.20144	2.75548	27232	203968	-1	16697	23	7740	32519	1480622	220162	7.27428	7.27428	-4524.79	-7.27428	0	0	1.31637e+06	4062.87	0.50	0.75	0.18	-1	-1	0.50	0.386104	0.344498	
-k6_N10_40nm.xml	ex1010.pre-vpr.blif	common	46.88	vpr	85.48 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	302	10	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:13	gh-actions-runner-vtr-auto-spawned84	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	87536	10	10	2659	2669	0	1417	322	20	20	400	clb	auto	45.6 MiB	1.55	26735	58781	15782	41072	1927	82.1 MiB	1.51	0.03	6.79311	-65.8142	-6.79311	nan	1.35	0.0085124	0.00699839	0.554051	0.464812	98	46081	40	1.74617e+07	1.6276e+07	2.35420e+06	5885.50	33.93	5.65722	4.78731	46488	495728	-1	40094	26	13124	79778	4200582	472080	6.72249	nan	-64.7071	-6.72249	0	0	2.96690e+06	7417.26	1.14	1.68	0.56	-1	-1	1.14	0.520613	0.459683	
-k6_N10_40nm.xml	ex5p.pre-vpr.blif	common	8.38	vpr	63.84 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	78	8	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:13	gh-actions-runner-vtr-auto-spawned84	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	65376	8	63	761	824	0	443	149	11	11	121	clb	auto	26.0 MiB	0.34	4420	9999	1667	7706	626	63.8 MiB	0.17	0.01	4.13681	-180.38	-4.13681	nan	0.29	0.00211285	0.00182583	0.0720785	0.0644836	68	6844	29	4.36541e+06	4.20373e+06	471571.	3897.28	5.57	1.06761	0.928764	11382	90811	-1	6299	27	3950	17583	680545	104378	4.04861	nan	-185.982	-4.04861	0	0	579861.	4792.24	0.19	0.34	0.09	-1	-1	0.19	0.141177	0.126817	
-k6_N10_40nm.xml	frisc.pre-vpr.blif	common	30.81	vpr	78.66 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	240	20	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:13	gh-actions-runner-vtr-auto-spawned84	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	80548	20	116	3175	3291	1	1254	376	18	18	324	clb	auto	41.3 MiB	1.01	14937	83092	21035	56910	5147	78.7 MiB	1.24	0.02	9.37137	-4836.23	-9.37137	9.37137	1.06	0.00697286	0.00631498	0.487542	0.424923	66	23239	30	1.37969e+07	1.29346e+07	1.36437e+06	4211.00	15.48	4.05596	3.47527	30784	270180	-1	20879	24	8723	36885	1817074	266114	9.12568	9.12568	-4847.74	-9.12568	0	0	1.68162e+06	5190.19	0.68	0.96	0.27	-1	-1	0.68	0.464555	0.409006	
-k6_N10_40nm.xml	misex3.pre-vpr.blif	common	8.14	vpr	64.57 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	87	14	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:13	gh-actions-runner-vtr-auto-spawned84	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	66124	14	14	828	842	0	488	115	12	12	144	clb	auto	26.8 MiB	0.37	4941	5695	788	4522	385	64.6 MiB	0.13	0.01	4.69826	-60.2129	-4.69826	nan	0.36	0.00194998	0.00170438	0.0577851	0.0517467	54	8009	47	5.3894e+06	4.68878e+06	451357.	3134.42	4.78	1.0707	0.928432	12324	89954	-1	7171	21	4179	17710	662276	104535	4.54449	nan	-60.4911	-4.54449	0	0	586610.	4073.68	0.20	0.33	0.09	-1	-1	0.20	0.137883	0.125264	
-k6_N10_40nm.xml	pdc.pre-vpr.blif	common	32.65	vpr	82.86 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	307	16	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:13	gh-actions-runner-vtr-auto-spawned84	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	84852	16	40	2839	2879	0	1501	363	20	20	400	clb	auto	46.3 MiB	1.35	24796	68945	17552	48401	2992	82.9 MiB	1.52	0.02	7.00232	-251.23	-7.00232	nan	1.36	0.00825615	0.00726621	0.537715	0.450301	80	44574	39	1.74617e+07	1.65455e+07	1.96642e+06	4916.06	17.86	3.70284	3.07411	41700	405380	-1	36503	18	12436	74071	3266555	428458	6.7432	nan	-249.933	-6.7432	0	0	2.46811e+06	6170.27	1.06	1.45	0.44	-1	-1	1.06	0.492521	0.439734	
-k6_N10_40nm.xml	s298.pre-vpr.blif	common	5.16	vpr	63.29 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	77	4	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:13	gh-actions-runner-vtr-auto-spawned84	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	64812	4	6	726	732	1	378	87	11	11	121	clb	auto	25.6 MiB	0.33	3693	3735	430	3194	111	63.3 MiB	0.12	0.00	6.30858	-51.7143	-6.30858	6.30858	0.29	0.00206524	0.0018247	0.0575937	0.0523635	44	6200	32	4.36541e+06	4.14984e+06	309216.	2555.51	1.92	0.492503	0.432481	9582	61621	-1	5457	22	3588	18601	711043	111359	6.51519	6.51519	-54.7562	-6.51519	0	0	401578.	3318.83	0.13	0.30	0.06	-1	-1	0.13	0.11595	0.105363	
-k6_N10_40nm.xml	s38584.1.pre-vpr.blif	common	37.82	vpr	87.45 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	368	38	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:13	gh-actions-runner-vtr-auto-spawned84	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	89548	39	304	4677	4982	1	2229	711	22	22	484	clb	auto	50.6 MiB	1.27	15892	248127	72238	162853	13036	87.4 MiB	2.76	0.04	5.02641	-3215.78	-5.02641	5.02641	1.86	0.00946056	0.0084162	0.850041	0.726935	44	24233	33	2.15576e+07	1.9833e+07	1.41060e+06	2914.46	9.06	3.67401	3.14581	39444	288878	-1	21443	23	12112	33710	1370500	248738	5.15976	5.15976	-3289.71	-5.15976	0	0	1.82601e+06	3772.76	0.88	1.06	0.28	-1	-1	0.88	0.611244	0.534232	
-k6_N10_40nm.xml	seq.pre-vpr.blif	common	8.06	vpr	65.75 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	103	41	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:13	gh-actions-runner-vtr-auto-spawned84	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	67332	41	35	1006	1041	0	588	179	13	13	169	clb	auto	28.2 MiB	0.48	6846	17819	3270	12655	1894	65.8 MiB	0.31	0.01	4.96104	-139.99	-4.96104	nan	0.44	0.00266866	0.00225678	0.118497	0.104761	56	12202	44	6.52117e+06	5.55108e+06	559864.	3312.80	4.05	0.848326	0.735081	14694	110679	-1	10652	23	5478	25529	1041333	159644	4.77402	nan	-140.731	-4.77402	0	0	714795.	4229.55	0.23	0.47	0.11	-1	-1	0.23	0.169854	0.153167	
-k6_N10_40nm.xml	spla.pre-vpr.blif	common	32.64	vpr	77.38 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	245	16	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:13	gh-actions-runner-vtr-auto-spawned84	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	79240	16	46	2232	2278	0	1154	307	18	18	324	clb	auto	40.0 MiB	1.04	17066	52057	12539	36561	2957	77.4 MiB	1.10	0.02	6.1923	-216.925	-6.1923	nan	1.04	0.00646966	0.00573086	0.413673	0.351269	70	29237	30	1.37969e+07	1.3204e+07	1.42834e+06	4408.47	21.13	4.16608	3.52139	31752	286880	-1	25273	21	9773	55725	2341275	316396	6.1326	nan	-216.962	-6.1326	0	0	1.78317e+06	5503.60	0.72	1.16	0.29	-1	-1	0.72	0.428936	0.383431	
-k6_N10_40nm.xml	tseng.pre-vpr.blif	common	7.00	vpr	65.94 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	110	52	-1	-1	success	8f82416-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-02T00:48:13	gh-actions-runner-vtr-auto-spawned84	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	67524	52	122	1461	1583	1	509	284	13	13	169	clb	auto	28.1 MiB	0.30	3129	40403	8633	29315	2455	65.9 MiB	0.32	0.01	5.00636	-1311.79	-5.00636	5.00636	0.44	0.00242755	0.00214846	0.127974	0.114495	32	5107	32	6.52117e+06	5.92834e+06	352895.	2088.14	3.01	0.951342	0.834771	12174	67024	-1	4717	29	2763	8262	352580	70758	4.58906	4.58906	-1300.62	-4.58906	0	0	431135.	2551.09	0.16	0.27	0.06	-1	-1	0.16	0.167609	0.149371	
+k6_N10_40nm.xml	alu4.pre-vpr.blif	common	8.71	vpr	65.38 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	97	14	-1	-1	success	ee5eb02-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-16T14:20:50	gh-actions-runner-vtr-auto-spawned135	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	66944	14	8	926	934	0	517	119	12	12	144	clb	auto	27.6 MiB	0.40	4978	9171	1462	7157	552	65.4 MiB	0.21	0.01	4.85854	-36.6925	-4.85854	nan	0.38	0.00226244	0.001991	0.0945504	0.082642	52	6841	26	1.8e+06	1.746e+06	452692.	3143.70	5.22	1.22756	1.05858	12180	91053	-1	6642	23	3992	14975	576861	90555	4.88853	nan	-35.9466	-4.88853	0	0	594734.	4130.10	0.19	0.31	0.08	-1	-1	0.19	0.150949	0.136693	
+k6_N10_40nm.xml	apex2.pre-vpr.blif	common	9.58	vpr	67.03 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	115	38	-1	-1	success	ee5eb02-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-16T14:20:50	gh-actions-runner-vtr-auto-spawned135	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	68636	39	3	1113	1117	0	675	157	13	13	169	clb	auto	29.5 MiB	0.53	7879	13693	2337	10136	1220	67.0 MiB	0.30	0.01	6.02154	-17.5859	-6.02154	nan	0.45	0.0028102	0.00246118	0.117499	0.103818	62	13086	48	2.178e+06	2.07e+06	652532.	3861.14	6.02	1.0391	0.894937	15366	127615	-1	11563	30	6785	30387	1264252	174643	5.82632	nan	-17.1242	-5.82632	0	0	801739.	4744.02	0.17	0.37	0.07	-1	-1	0.17	0.134439	0.121141	
+k6_N10_40nm.xml	apex4.pre-vpr.blif	common	7.04	vpr	65.39 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	95	9	-1	-1	success	ee5eb02-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-16T14:20:50	gh-actions-runner-vtr-auto-spawned135	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	66960	9	19	897	916	0	569	123	12	12	144	clb	auto	27.6 MiB	0.47	6709	9578	1569	7337	672	65.4 MiB	0.22	0.01	5.16784	-84.6504	-5.16784	nan	0.37	0.00236091	0.00202291	0.0896899	0.0795875	62	10796	38	1.8e+06	1.71e+06	546237.	3793.31	3.57	0.718352	0.625054	13040	106280	-1	9528	24	5403	25371	1032193	149160	5.31039	nan	-84.6173	-5.31039	0	0	671089.	4660.34	0.21	0.41	0.10	-1	-1	0.21	0.148545	0.133948	
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From ff6bfc648b1fdf9df0bcd70798291537ef4ac19f Mon Sep 17 00:00:00 2001
From: amin1377 <amin1377.mohaghegh@gmail.com>
Date: Sun, 25 Aug 2024 16:27:34 -0400
Subject: [PATCH 06/12] [test][strong] update strong_clock* golden

---
 .../config/golden_results.txt                  |  6 +++---
 .../config/golden_results.txt                  |  4 ++--
 .../config/golden_results.txt                  | 18 +++++++++---------
 3 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt
index a5ac81a2c65..90d9f177c7c 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt
@@ -1,4 +1,4 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	0.15	vpr	57.62 MiB	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	-1	782a17c	Release IPO VTR_ASSERT_LEVEL=3	GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64	2024-08-16T12:54:30	-1	-1	59004	1	4	28	32	2	10	9	4	4	16	clb	auto	19.2 MiB	0.00	20	27	15	8	4	57.6 MiB	0.00	0.00	2.44626	0	0	2.44626	0.01	6.1505e-05	5.4271e-05	0.000399345	0.000366854	8	12	5	72000	72000	5593.62	349.601	0.01	0.00469757	0.00398579	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.00	0.00	0.00	-1	-1	0.00	0.0018976	0.00177716	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	0.15	vpr	57.43 MiB	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	-1	782a17c	Release IPO VTR_ASSERT_LEVEL=3	GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64	2024-08-16T12:54:30	-1	-1	58804	1	4	28	32	2	10	9	4	4	16	clb	auto	19.1 MiB	0.00	20	27	15	8	4	57.4 MiB	0.00	0.00	2.44626	0	0	2.44626	0.01	3.5236e-05	2.9806e-05	0.000357366	0.000308936	8	12	5	72000	72000	5593.62	349.601	0.01	0.00440932	0.00372158	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.00	0.00	0.00	-1	-1	0.00	0.00185784	0.00175594	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	0.15	vpr	57.38 MiB	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	-1	782a17c	Release IPO VTR_ASSERT_LEVEL=3	GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64	2024-08-16T12:54:30	-1	-1	58756	1	4	28	32	2	10	9	4	4	16	clb	auto	19.0 MiB	0.00	20	27	15	8	4	57.4 MiB	0.00	0.00	2.44626	0	0	2.44626	0.01	3.5736e-05	3.0076e-05	0.000329113	0.000300139	8	12	5	72000	72000	5593.62	349.601	0.01	0.00439327	0.00372855	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.00	0.00	0.00	-1	-1	0.00	0.00183794	0.00172653	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	0.33	vpr	57.89 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	59280	1	4	28	32	2	10	9	4	4	16	clb	auto	19.6 MiB	0.01	20	27	15	8	4	57.9 MiB	0.00	0.00	2.44626	0	0	2.44626	0.02	6.522e-05	5.8807e-05	0.000520276	0.000480282	8	12	5	72000	72000	5593.62	349.601	0.03	0.00762819	0.00638476	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.00	0.00	0.00	-1	-1	0.00	0.00235121	0.00216168	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	0.32	vpr	57.76 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	59144	1	4	28	32	2	10	9	4	4	16	clb	auto	19.5 MiB	0.01	20	27	15	8	4	57.8 MiB	0.00	0.00	2.44626	0	0	2.44626	0.01	7.6909e-05	6.9134e-05	0.000530933	0.000491554	8	12	5	72000	72000	5593.62	349.601	0.03	0.00769087	0.00644081	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.00	0.00	0.00	-1	-1	0.00	0.00237431	0.00218377	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	0.32	vpr	57.91 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	59304	1	4	28	32	2	10	9	4	4	16	clb	auto	19.6 MiB	0.01	20	27	15	8	4	57.9 MiB	0.00	0.00	2.44626	0	0	2.44626	0.01	5.6889e-05	5.0331e-05	0.000476198	0.000438042	8	12	5	72000	72000	5593.62	349.601	0.03	0.00727055	0.00604445	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.00	0.00	0.00	-1	-1	0.00	0.00234916	0.00215934	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt
index f2cadd4e550..e34e4d38d17 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt
@@ -1,2 +1,2 @@
- arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
- timing/k6_N10_40nm.xml	  clock_set_delay_aliases.blif	  common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc	  0.21	  vpr	  56.37 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  2	  2	  -1	  -1	  success	  v8.0.0-6989-g4a9293e1e-dirty	  release IPO VTR_ASSERT_LEVEL=3	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-02-04T01:37:29	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  57720	  2	  2	  22	  24	  2	  4	  6	  4	  4	  16	  clb	  auto	  18.1 MiB	  0.00	  4	  56.4 MiB	  0.00	  0.00	  1.293	  0	  0	  1.293	  0.01	  1.7316e-05	  1.2051e-05	  0.000172483	  0.000143849	  6	  6	  1	  215576	  107788	  3924.73	  245.296	  0.00	  0.000640147	  0.000558617	  9	  3	  5	  5	  233	  128	  1.293	  1.293	  0	  0	  0	  0	  5503.53	  343.971	  0.00	  0.00	  0.000444617	  0.000393194	 
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
+timing/k6_N10_40nm.xml	clock_set_delay_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc	0.30	vpr	57.82 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	2	2	-1	-1	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	59208	2	2	22	24	2	4	6	4	4	16	clb	auto	19.5 MiB	0.01	4	15	2	10	3	57.8 MiB	0.00	0.00	1.297	0	0	1.297	0.01	4.3769e-05	3.8064e-05	0.000324999	0.000293005	4	6	2	72000	36000	2827.54	176.721	0.01	0.00228834	0.0020767	644	852	-1	6	2	4	4	138	80	1.297	1.297	0	0	0	0	4025.56	251.598	0.00	0.00	0.00	-1	-1	0.00	0.00162095	0.00152882	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt
index 0a89c3b897f..e7a944100ab 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt
@@ -1,9 +1,9 @@
- arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	  num_global_nets	  num_routed_nets	 
- timing/k6_N10_40nm.xml	  microbenchmarks/d_flip_flop.v	  common_--clock_modeling_ideal_--route_chan_width_60	  0.28	  vpr	  56.10 MiB	  	  -1	  -1	  0.05	  20076	  1	  0.00	  -1	  -1	  32876	  -1	  -1	  1	  2	  -1	  -1	  success	  v8.0.0-6989-g4a9293e1e-dirty	  release IPO VTR_ASSERT_LEVEL=3	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-02-04T01:37:29	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  57444	  2	  1	  3	  4	  1	  3	  4	  3	  3	  9	  -1	  auto	  17.5 MiB	  0.00	  4	  56.1 MiB	  0.00	  0.00	  0.571526	  -0.946421	  -0.571526	  0.571526	  0.00	  7.472e-06	  4.444e-06	  5.2255e-05	  3.5357e-05	  -1	  2	  2	  53894	  53894	  12370.0	  1374.45	  0.00	  0.000150639	  0.000101445	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  1	  2	 
- timing/k6_N10_40nm.xml	  microbenchmarks/d_flip_flop.v	  common_--clock_modeling_route_--route_chan_width_60	  0.26	  vpr	  56.07 MiB	  	  -1	  -1	  0.05	  20348	  1	  0.00	  -1	  -1	  33116	  -1	  -1	  1	  2	  -1	  -1	  success	  v8.0.0-6989-g4a9293e1e-dirty	  release IPO VTR_ASSERT_LEVEL=3	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-02-04T01:37:29	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  57412	  2	  1	  3	  4	  1	  3	  4	  3	  3	  9	  -1	  auto	  17.5 MiB	  0.00	  6	  56.1 MiB	  0.00	  0.00	  0.526189	  -0.94819	  -0.526189	  0.526189	  0.00	  7.373e-06	  4.228e-06	  5.4128e-05	  3.6541e-05	  -1	  8	  3	  53894	  53894	  14028.3	  1558.70	  0.00	  0.000159415	  0.000108151	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  0	  3	 
- timing/k6_N10_40nm.xml	  verilog/mkPktMerge.v	  common_--clock_modeling_ideal_--route_chan_width_60	  20.62	  yosys	  204.34 MiB	  	  -1	  -1	  16.70	  209240	  2	  1.15	  -1	  -1	  59832	  -1	  -1	  155	  5	  -1	  -1	  success	  v8.0.0-6989-g4a9293e1e-dirty	  release IPO VTR_ASSERT_LEVEL=3	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-02-04T01:37:29	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  59280	  5	  156	  191	  347	  1	  163	  316	  15	  15	  225	  clb	  auto	  19.6 MiB	  0.02	  22	  57.9 MiB	  0.07	  0.00	  1.10153	  -11.3996	  -1.10153	  1.10153	  0.01	  0.000146864	  0.000131212	  0.011265	  0.0101019	  -1	  38	  5	  9.10809e+06	  8.35357e+06	  828754.	  3683.35	  0.00	  0.0144781	  0.0131086	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  154	  9	 
- timing/k6_N10_40nm.xml	  verilog/mkPktMerge.v	  common_--clock_modeling_route_--route_chan_width_60	  20.82	  yosys	  204.26 MiB	  	  -1	  -1	  16.55	  209160	  2	  1.15	  -1	  -1	  59996	  -1	  -1	  155	  5	  -1	  -1	  success	  v8.0.0-6989-g4a9293e1e-dirty	  release IPO VTR_ASSERT_LEVEL=3	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-02-04T01:37:29	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  59440	  5	  156	  191	  347	  1	  163	  316	  15	  15	  225	  clb	  auto	  19.8 MiB	  0.02	  25	  58.0 MiB	  0.08	  0.00	  1.12309	  -11.8205	  -1.12309	  1.12309	  0.01	  0.000159954	  0.000141912	  0.0122901	  0.011012	  -1	  48	  4	  9.10809e+06	  8.35357e+06	  858153.	  3814.01	  0.00	  0.0153796	  0.0139115	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  153	  10	 
- timing/k6_N10_mem32K_40nm.xml	  microbenchmarks/d_flip_flop.v	  common_--clock_modeling_ideal_--route_chan_width_60	  0.34	  vpr	  60.93 MiB	  	  -1	  -1	  0.06	  20324	  1	  0.00	  -1	  -1	  33212	  -1	  -1	  1	  2	  0	  0	  success	  v8.0.0-6989-g4a9293e1e-dirty	  release IPO VTR_ASSERT_LEVEL=3	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-02-04T01:37:29	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  62388	  2	  1	  3	  4	  1	  3	  4	  3	  3	  9	  -1	  auto	  22.2 MiB	  0.00	  4	  60.9 MiB	  0.01	  0.00	  0.571526	  -0.946421	  -0.571526	  0.571526	  0.00	  2.0228e-05	  1.4173e-05	  7.1706e-05	  4.9857e-05	  -1	  2	  2	  53894	  53894	  12370.0	  1374.45	  0.00	  0.000190797	  0.00013594	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  1	  2	 
- timing/k6_N10_mem32K_40nm.xml	  microbenchmarks/d_flip_flop.v	  common_--clock_modeling_route_--route_chan_width_60	  0.27	  vpr	  61.09 MiB	  	  -1	  -1	  0.06	  20372	  1	  0.01	  -1	  -1	  33044	  -1	  -1	  1	  2	  0	  0	  success	  v8.0.0-6989-g4a9293e1e-dirty	  release IPO VTR_ASSERT_LEVEL=3	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-02-04T01:37:29	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  62556	  2	  1	  3	  4	  1	  3	  4	  3	  3	  9	  -1	  auto	  22.4 MiB	  0.00	  6	  61.1 MiB	  0.00	  0.00	  0.526189	  -0.94819	  -0.526189	  0.526189	  0.00	  7.855e-06	  4.642e-06	  5.7063e-05	  3.8267e-05	  -1	  8	  3	  53894	  53894	  14028.3	  1558.70	  0.00	  0.000173245	  0.000119981	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  0	  3	 
- timing/k6_N10_mem32K_40nm.xml	  verilog/mkPktMerge.v	  common_--clock_modeling_ideal_--route_chan_width_60	  5.31	  vpr	  69.03 MiB	  	  -1	  -1	  0.84	  29148	  2	  0.11	  -1	  -1	  37560	  -1	  -1	  32	  311	  15	  0	  success	  v8.0.0-6989-g4a9293e1e-dirty	  release IPO VTR_ASSERT_LEVEL=3	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-02-04T01:37:29	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  70688	  311	  156	  972	  1128	  1	  953	  514	  28	  28	  784	  memory	  auto	  30.9 MiB	  0.40	  8912	  69.0 MiB	  0.82	  0.02	  4.4435	  -4133.58	  -4.4435	  4.4435	  0.14	  0.00289443	  0.00248922	  0.296854	  0.253031	  -1	  13294	  11	  4.25198e+07	  9.94461e+06	  2.96205e+06	  3778.13	  1.02	  0.4114	  0.359724	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  15	  938	 
- timing/k6_N10_mem32K_40nm.xml	  verilog/mkPktMerge.v	  common_--clock_modeling_route_--route_chan_width_60	  5.65	  vpr	  69.32 MiB	  	  -1	  -1	  0.83	  29208	  2	  0.10	  -1	  -1	  37556	  -1	  -1	  32	  311	  15	  0	  success	  v8.0.0-6989-g4a9293e1e-dirty	  release IPO VTR_ASSERT_LEVEL=3	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-02-04T01:37:29	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  70980	  311	  156	  972	  1128	  1	  953	  514	  28	  28	  784	  memory	  auto	  31.2 MiB	  0.39	  9335	  69.3 MiB	  0.87	  0.03	  4.01406	  -3152.9	  -4.01406	  4.01406	  0.18	  0.00283395	  0.00242386	  0.302074	  0.260062	  -1	  14070	  16	  4.25198e+07	  9.94461e+06	  3.02951e+06	  3864.17	  1.19	  0.45079	  0.397878	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  14	  939	 
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	num_global_nets	num_routed_nets	
+timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_--clock_modeling_ideal_--route_chan_width_60	0.30	vpr	57.61 MiB		-1	-1	0.06	19388	1	0.02	-1	-1	33516	-1	-1	1	2	-1	-1	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	58988	2	1	3	4	1	3	4	3	3	9	-1	auto	19.1 MiB	0.00	4	9	6	3	0	57.6 MiB	0.00	0.00	0.55447	-0.91031	-0.55447	0.55447	0.00	1.4209e-05	1.0635e-05	0.000112608	8.885e-05	-1	2	1	18000	18000	14049.7	1561.07	0.00	0.00111531	0.00103596	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
+timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_--clock_modeling_route_--route_chan_width_60	0.30	vpr	57.69 MiB		-1	-1	0.06	19244	1	0.02	-1	-1	33536	-1	-1	1	2	-1	-1	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	59076	2	1	3	4	1	3	4	3	3	9	-1	auto	19.2 MiB	0.00	6	9	5	2	2	57.7 MiB	0.00	0.00	0.48631	-0.91031	-0.48631	0.48631	0.00	1.4475e-05	1.0195e-05	0.000102982	7.9111e-05	-1	4	1	18000	18000	15707.9	1745.32	0.00	0.00110914	0.00104203	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
+timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_--clock_modeling_ideal_--route_chan_width_60	26.57	parmys	203.92 MiB		-1	-1	21.33	208816	2	1.49	-1	-1	61188	-1	-1	155	5	-1	-1	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	61088	5	156	191	347	1	163	316	15	15	225	clb	auto	21.3 MiB	0.03	22	75566	54444	2848	18274	59.7 MiB	0.07	0.00	1.49664	-15.129	-1.49664	1.49664	0.00	0.000225009	0.000209684	0.0166386	0.0154931	-1	38	6	3.042e+06	2.79e+06	863192.	3836.41	0.01	0.0221087	0.0205962	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	154	9	
+timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_--clock_modeling_route_--route_chan_width_60	26.99	parmys	204.15 MiB		-1	-1	21.52	209052	2	1.49	-1	-1	60656	-1	-1	155	5	-1	-1	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	60972	5	156	191	347	1	163	316	15	15	225	clb	auto	21.3 MiB	0.03	25	77716	55619	3345	18752	59.5 MiB	0.13	0.00	1.47823	-14.9031	-1.47823	1.47823	0.00	0.000388878	0.000358886	0.0289108	0.0266306	-1	38	3	3.042e+06	2.79e+06	892591.	3967.07	0.01	0.0351201	0.0324031	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	153	10	
+timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_--clock_modeling_ideal_--route_chan_width_60	0.35	vpr	63.08 MiB		-1	-1	0.08	19324	1	0.02	-1	-1	33472	-1	-1	1	2	0	0	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	64592	2	1	3	4	1	3	4	3	3	9	-1	auto	24.5 MiB	0.00	4	9	6	2	1	63.1 MiB	0.00	0.00	0.55247	-0.90831	-0.55247	0.55247	0.00	1.3129e-05	9.703e-06	0.000103951	8.1123e-05	-1	2	2	53894	53894	12370.0	1374.45	0.00	0.00116445	0.00109439	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
+timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_--clock_modeling_route_--route_chan_width_60	0.35	vpr	62.96 MiB		-1	-1	0.08	19876	1	0.02	-1	-1	33484	-1	-1	1	2	0	0	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	64468	2	1	3	4	1	3	4	3	3	9	-1	auto	24.3 MiB	0.00	6	9	5	2	2	63.0 MiB	0.00	0.00	0.48631	-0.90831	-0.48631	0.48631	0.00	1.5477e-05	1.1104e-05	0.000110622	8.6576e-05	-1	8	1	53894	53894	14028.3	1558.70	0.00	0.00113491	0.00106717	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
+timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_--clock_modeling_ideal_--route_chan_width_60	6.10	vpr	71.24 MiB		-1	-1	1.09	28164	2	0.15	-1	-1	37372	-1	-1	32	311	15	0	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	72952	311	156	972	1128	1	953	514	28	28	784	memory	auto	33.0 MiB	0.48	8979	193966	70726	114124	9116	71.2 MiB	1.31	0.03	4.11528	-4394.91	-4.11528	4.11528	0.00	0.00488787	0.00418834	0.465058	0.395185	-1	13380	12	4.25198e+07	9.94461e+06	2.96205e+06	3778.13	0.38	0.643724	0.557601	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	15	938	
+timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_--clock_modeling_route_--route_chan_width_60	6.26	vpr	71.41 MiB		-1	-1	1.06	28216	2	0.15	-1	-1	37564	-1	-1	32	311	15	0	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	73128	311	156	972	1128	1	953	514	28	28	784	memory	auto	33.2 MiB	0.48	8125	208372	75006	121666	11700	71.4 MiB	1.39	0.02	4.69946	-3846.5	-4.69946	4.69946	0.00	0.00473553	0.0040387	0.491963	0.415743	-1	12865	15	4.25198e+07	9.94461e+06	3.02951e+06	3864.17	0.41	0.692219	0.598424	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	14	939	

From fe7252ab36a409cde63d0370254ced8346785588 Mon Sep 17 00:00:00 2001
From: amin1377 <amin1377.mohaghegh@gmail.com>
Date: Sun, 25 Aug 2024 16:35:02 -0400
Subject: [PATCH 07/12] [test][strong_odin]

---
 .../config/golden_results.txt                  |  6 +++---
 .../config/golden_results.txt                  |  4 ++--
 .../config/golden_results.txt                  | 18 +++++++++---------
 3 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
index eed3e3f19b2..ecdb2d74099 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
@@ -1,4 +1,4 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	0.15	vpr	57.62 MiB	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	-1	782a17c	Release IPO VTR_ASSERT_LEVEL=3	GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64	2024-08-16T12:48:04	-1	-1	59008	1	4	28	32	2	10	9	4	4	16	clb	auto	19.2 MiB	0.00	20	27	15	8	4	57.6 MiB	0.00	0.00	2.44626	0	0	2.44626	0.01	3.6649e-05	3.0788e-05	0.000332461	0.000302474	8	12	5	72000	72000	5593.62	349.601	0.01	0.00463095	0.00390158	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.00	0.00	0.00	-1	-1	0.00	0.00184241	0.00173742	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	0.15	vpr	57.50 MiB	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	-1	782a17c	Release IPO VTR_ASSERT_LEVEL=3	GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64	2024-08-16T12:48:04	-1	-1	58880	1	4	28	32	2	10	9	4	4	16	clb	auto	19.1 MiB	0.00	20	27	15	8	4	57.5 MiB	0.00	0.00	2.44626	0	0	2.44626	0.01	3.6368e-05	3.0868e-05	0.000334423	0.000304918	8	12	5	72000	72000	5593.62	349.601	0.01	0.00434957	0.00368628	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.00	0.00	0.00	-1	-1	0.00	0.00187403	0.00175995	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	0.15	vpr	57.37 MiB	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	-1	782a17c	Release IPO VTR_ASSERT_LEVEL=3	GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64	2024-08-16T12:48:04	-1	-1	58748	1	4	28	32	2	10	9	4	4	16	clb	auto	19.1 MiB	0.00	20	27	15	8	4	57.4 MiB	0.00	0.00	2.44626	0	0	2.44626	0.01	3.6097e-05	3.0537e-05	0.000332419	0.000303054	8	12	5	72000	72000	5593.62	349.601	0.01	0.00433458	0.00365113	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.00	0.00	0.00	-1	-1	0.00	0.00181848	0.00171448	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	4.13	vpr	202.88 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	207748	1	4	28	32	2	10	9	4	4	16	clb	auto	51.9 MiB	0.14	20	27	15	8	4	193.9 MiB	0.03	0.00	2.44626	0	0	2.44626	0.51	0.000583271	0.000535066	0.00308541	0.00258587	8	12	5	72000	72000	5593.62	349.601	0.86	0.0614891	0.0547303	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.010886	0.00952369	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	4.18	vpr	203.46 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	208344	1	4	28	32	2	10	9	4	4	16	clb	auto	52.0 MiB	0.14	20	27	15	8	4	194.0 MiB	0.03	0.00	2.44626	0	0	2.44626	0.51	0.000579833	0.000533235	0.00309464	0.0025854	8	12	5	72000	72000	5593.62	349.601	0.86	0.0608434	0.0541405	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0108096	0.00946964	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	4.13	vpr	202.64 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	207504	1	4	28	32	2	10	9	4	4	16	clb	auto	51.4 MiB	0.14	20	27	15	8	4	193.1 MiB	0.03	0.00	2.44626	0	0	2.44626	0.51	0.000572304	0.000525073	0.00310109	0.00259353	8	12	5	72000	72000	5593.62	349.601	0.86	0.0611009	0.054383	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0108444	0.00950833	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt
index 716bd84b5d9..e08e6fdcd68 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt
@@ -1,2 +1,2 @@
- arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
- timing/k6_N10_40nm.xml	  clock_set_delay_aliases.blif	  common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc	  0.70	  vpr	  54.43 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  2	  2	  -1	  -1	  success	  v8.0.0-6793-gb52911b9f	  release IPO VTR_ASSERT_LEVEL=2	  GNU 7.5.0 on Linux-4.15.0-167-generic x86_64	  2022-11-27T15:52:14	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing	  55736	  2	  2	  22	  24	  2	  4	  6	  4	  4	  16	  clb	  auto	  16.0 MiB	  0.00	  4	  54.4 MiB	  0.00	  0.00	  1.293	  0	  0	  1.293	  0.02	  3.0248e-05	  2.3255e-05	  0.00029412	  0.000252171	  6	  6	  1	  215576	  107788	  3924.73	  245.296	  0.09	  0.0011793	  0.00104221	  9	  3	  5	  5	  233	  128	  1.293	  1.293	  0	  0	  0	  0	  5503.53	  343.971	  0.00	  0.06	  0.000728173	  0.000642893	 
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
+timing/k6_N10_40nm.xml	clock_set_delay_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc	3.91	vpr	202.38 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	2	2	-1	-1	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	207240	2	2	22	24	2	4	6	4	4	16	clb	auto	51.8 MiB	0.10	4	15	2	10	3	193.1 MiB	0.02	0.00	1.297	0	0	1.297	0.50	0.000500888	0.000459494	0.00266891	0.00218049	4	6	2	72000	36000	2827.54	176.721	0.84	0.0129763	0.0108607	644	852	-1	6	2	4	4	138	80	1.297	1.297	0	0	0	0	4025.56	251.598	0.01	0.02	0.16	-1	-1	0.01	0.00609768	0.00517486	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt
index b8c6939d726..d15e3368469 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt
@@ -1,9 +1,9 @@
-arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	crit_path_total_internal_heap_pushes	crit_path_total_internal_heap_pops	crit_path_total_external_heap_pushes	crit_path_total_external_heap_pops	crit_path_total_external_SOURCE_pushes	crit_path_total_external_SOURCE_pops	crit_path_total_internal_SOURCE_pushes	crit_path_total_internal_SOURCE_pops	crit_path_total_external_SINK_pushes	crit_path_total_external_SINK_pops	crit_path_total_internal_SINK_pushes	crit_path_total_internal_SINK_pops	crit_path_total_external_IPIN_pushes	crit_path_total_external_IPIN_pops	crit_path_total_internal_IPIN_pushes	crit_path_total_internal_IPIN_pops	crit_path_total_external_OPIN_pushes	crit_path_total_external_OPIN_pops	crit_path_total_internal_OPIN_pushes	crit_path_total_internal_OPIN_pops	crit_path_total_external_CHANX_pushes	crit_path_total_external_CHANX_pops	crit_path_total_internal_CHANX_pushes	crit_path_total_internal_CHANX_pops	crit_path_total_external_CHANY_pushes	crit_path_total_external_CHANY_pops	crit_path_total_internal_CHANY_pushes	crit_path_total_internal_CHANY_pops	crit_path_rt_node_SOURCE_pushes	crit_path_rt_node_SINK_pushes	crit_path_rt_node_IPIN_pushes	crit_path_rt_node_OPIN_pushes	crit_path_rt_node_CHANX_pushes	crit_path_rt_node_CHANY_pushes	crit_path_adding_all_rt	crit_path_adding_high_fanout_rt	crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	num_global_nets	num_routed_nets	
-timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	0.24	vpr	55.66 MiB		0.00	5216	-1	-1	1	0.00	-1	-1	32328	-1	-1	1	2	-1	-1	success	v8.0.0-7649-g3eb9a4e-dirty	Release IPO VTR_ASSERT_LEVEL=3	GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64	2023-04-20T17:52:50	agent-1	/home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks	56996	2	1	3	4	1	3	4	3	3	9	-1	auto	16.5 MiB	0.00	4	55.7 MiB	0.00	0.00	0.571526	-0.946421	-0.571526	0.571526	0.00	7.621e-06	5.224e-06	6.7874e-05	5.0802e-05	-1	2	2	53894	53894	12370.0	1374.45	0.00	0.000205736	0.000155947	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
-timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	0.23	vpr	55.70 MiB		0.00	5212	-1	-1	1	0.01	-1	-1	32344	-1	-1	1	2	-1	-1	success	v8.0.0-7649-g3eb9a4e-dirty	Release IPO VTR_ASSERT_LEVEL=3	GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64	2023-04-20T17:52:50	agent-1	/home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks	57032	2	1	3	4	1	3	4	3	3	9	-1	auto	16.6 MiB	0.00	6	55.7 MiB	0.00	0.00	0.526189	-0.94819	-0.526189	0.526189	0.00	7.761e-06	5.265e-06	6.7961e-05	5.0472e-05	-1	4	1	53894	53894	14028.3	1558.70	0.00	0.000187922	0.00014281	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
-timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	4.64	vpr	58.30 MiB		0.36	58984	-1	-1	2	1.50	-1	-1	48756	-1	-1	155	5	-1	-1	success	v8.0.0-7649-g3eb9a4e-dirty	Release IPO VTR_ASSERT_LEVEL=3	GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64	2023-04-20T17:52:50	agent-1	/home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks	59700	5	156	191	347	1	163	316	15	15	225	clb	auto	19.7 MiB	0.05	22	58.3 MiB	0.20	0.00	1.10064	-11.4028	-1.10064	1.10064	0.02	0.000207655	0.000184614	0.0172662	0.0153484	-1	34	4	9.10809e+06	8.35357e+06	828754.	3683.35	0.01	0.0215404	0.0193498	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	154	9	
-timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	4.63	vpr	57.95 MiB		0.36	59028	-1	-1	2	1.45	-1	-1	48796	-1	-1	155	5	-1	-1	success	v8.0.0-7649-g3eb9a4e-dirty	Release IPO VTR_ASSERT_LEVEL=3	GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64	2023-04-20T17:52:50	agent-1	/home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks	59344	5	156	191	347	1	163	316	15	15	225	clb	auto	19.5 MiB	0.05	25	58.0 MiB	0.20	0.00	1.08173	-11.7171	-1.08173	1.08173	0.02	0.000210434	0.000187171	0.0177434	0.0157333	-1	56	4	9.10809e+06	8.35357e+06	858153.	3814.01	0.01	0.0220048	0.0197235	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	153	10	
-timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	0.30	vpr	60.97 MiB		0.03	5868	-1	-1	1	0.00	-1	-1	32324	-1	-1	1	2	0	0	success	v8.0.0-7649-g3eb9a4e-dirty	Release IPO VTR_ASSERT_LEVEL=3	GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64	2023-04-20T17:52:50	agent-1	/home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks	62436	2	1	3	4	1	3	4	3	3	9	-1	auto	22.2 MiB	0.00	4	61.0 MiB	0.00	0.00	0.571526	-0.946421	-0.571526	0.571526	0.00	7.366e-06	4.962e-06	6.4942e-05	4.834e-05	-1	2	2	53894	53894	12370.0	1374.45	0.00	0.000199931	0.000152012	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
-timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	0.29	vpr	61.36 MiB		0.02	5840	-1	-1	1	0.01	-1	-1	32312	-1	-1	1	2	0	0	success	v8.0.0-7649-g3eb9a4e-dirty	Release IPO VTR_ASSERT_LEVEL=3	GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64	2023-04-20T17:52:50	agent-1	/home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks	62828	2	1	3	4	1	3	4	3	3	9	-1	auto	22.4 MiB	0.00	6	61.4 MiB	0.00	0.00	0.526189	-0.94819	-0.526189	0.526189	0.00	7.761e-06	5.205e-06	6.9109e-05	5.2607e-05	-1	4	1	53894	53894	14028.3	1558.70	0.00	0.000190744	0.000146909	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
-timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	6.17	vpr	69.56 MiB		0.21	16208	-1	-1	2	0.15	-1	-1	37780	-1	-1	32	311	15	0	success	v8.0.0-7649-g3eb9a4e-dirty	Release IPO VTR_ASSERT_LEVEL=3	GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64	2023-04-20T17:52:50	agent-1	/home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks	71228	311	156	972	1128	1	953	514	28	28	784	memory	auto	31.1 MiB	0.57	8510	69.6 MiB	1.42	0.02	3.82722	-4064.49	-3.82722	3.82722	0.26	0.00342284	0.00289929	0.387553	0.329277	-1	13023	14	4.25198e+07	9.94461e+06	2.96205e+06	3778.13	1.10	0.5346	0.464391	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	15	938	
-timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	6.41	vpr	69.44 MiB		0.18	16292	-1	-1	2	0.13	-1	-1	37668	-1	-1	32	311	15	0	success	v8.0.0-7649-g3eb9a4e-dirty	Release IPO VTR_ASSERT_LEVEL=3	GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64	2023-04-20T17:52:50	agent-1	/home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks	71104	311	156	972	1128	1	953	514	28	28	784	memory	auto	30.9 MiB	0.58	8543	69.4 MiB	1.40	0.02	4.32962	-3179.64	-4.32962	4.32962	0.21	0.00343224	0.00290294	0.37301	0.318522	-1	13270	16	4.25198e+07	9.94461e+06	3.02951e+06	3864.17	1.34	0.531097	0.463938	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	14	939	
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	num_global_nets	num_routed_nets	
+timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	1.26	vpr	188.86 MiB		0.14	21040	-1	-1	1	0.02	-1	-1	33188	-1	-1	1	2	-1	-1	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	193388	2	1	3	4	1	3	4	3	3	9	-1	auto	49.5 MiB	0.02	4	9	3	5	1	184.5 MiB	0.01	0.00	0.55447	-0.91031	-0.55447	0.55447	0.00	0.000183823	0.000174194	0.00100836	0.000790661	-1	2	4	18000	18000	14049.7	1561.07	0.01	0.00460219	0.00375757	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
+timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	1.27	vpr	188.60 MiB		0.14	20628	-1	-1	1	0.02	-1	-1	33332	-1	-1	1	2	-1	-1	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	193124	2	1	3	4	1	3	4	3	3	9	-1	auto	49.3 MiB	0.02	6	9	3	3	3	184.3 MiB	0.01	0.00	0.48631	-0.91031	-0.48631	0.48631	0.00	0.000177321	0.000167639	0.00103736	0.000764866	-1	4	3	18000	18000	15707.9	1745.32	0.01	0.00431966	0.00346039	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
+timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	38.48	odin	761.48 MiB		14.71	779760	-1	-1	2	1.40	-1	-1	54260	-1	-1	155	5	-1	-1	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	335884	5	156	191	347	1	163	316	15	15	225	clb	auto	72.4 MiB	1.22	22	86316	62090	3287	20939	314.6 MiB	8.40	0.11	1.49664	-15.129	-1.49664	1.49664	0.00	0.00426561	0.0040116	0.354616	0.332804	-1	30	6	3.042e+06	2.79e+06	863192.	3836.41	0.18	0.428316	0.401633	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	154	9	
+timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	38.42	odin	761.69 MiB		14.65	779972	-1	-1	2	1.39	-1	-1	54048	-1	-1	155	5	-1	-1	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	336664	5	156	191	347	1	163	316	15	15	225	clb	auto	72.6 MiB	1.21	25	86316	61881	3554	20881	315.7 MiB	8.36	0.10	1.47767	-14.8876	-1.47767	1.47767	0.00	0.00425682	0.00401442	0.358109	0.335378	-1	53	7	3.042e+06	2.79e+06	892591.	3967.07	0.20	0.440276	0.412199	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	153	10	
+timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	6.86	vpr	218.88 MiB		2.30	38132	-1	-1	1	0.02	-1	-1	33428	-1	-1	1	2	0	0	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	224132	2	1	3	4	1	3	4	3	3	9	-1	auto	76.7 MiB	0.03	4	9	3	5	1	213.6 MiB	0.01	0.00	0.55247	-0.90831	-0.55247	0.55247	0.00	0.000178865	0.000169268	0.000984461	0.000772611	-1	2	3	53894	53894	12370.0	1374.45	0.01	0.00430389	0.00350335	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
+timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	6.87	vpr	218.13 MiB		2.29	38336	-1	-1	1	0.02	-1	-1	33336	-1	-1	1	2	0	0	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	223364	2	1	3	4	1	3	4	3	3	9	-1	auto	76.9 MiB	0.03	6	9	3	3	3	213.9 MiB	0.01	0.00	0.48631	-0.90831	-0.48631	0.48631	0.00	0.000188486	0.000177671	0.00107327	0.000808747	-1	4	2	53894	53894	14028.3	1558.70	0.01	0.00421058	0.00337424	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
+timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	109.20	odin	592.18 MiB		9.76	606396	-1	-1	2	0.16	-1	-1	37412	-1	-1	32	311	15	0	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	550636	311	156	972	1128	1	953	514	28	28	784	memory	auto	195.3 MiB	10.16	8852	208372	78139	120196	10037	514.6 MiB	40.87	0.47	4.11307	-4320.89	-4.11307	4.11307	0.02	0.1118	0.105538	11.7033	11.043	-1	13295	15	4.25198e+07	9.94461e+06	2.96205e+06	3778.13	6.89	15.5574	14.7523	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	15	938	
+timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	111.94	odin	592.37 MiB		9.78	606588	-1	-1	2	0.16	-1	-1	37320	-1	-1	32	311	15	0	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	553664	311	156	972	1128	1	953	514	28	28	784	memory	auto	195.3 MiB	10.22	8741	214546	82147	122429	9970	513.9 MiB	42.14	0.46	4.83167	-3665.82	-4.83167	4.83167	0.02	0.112871	0.106525	12.0865	11.4105	-1	13585	17	4.25198e+07	9.94461e+06	3.02951e+06	3864.17	7.65	16.4571	15.6143	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	14	939	

From 5ecd36fb7692aa4c8842a37ea977c73c0dabb6ed Mon Sep 17 00:00:00 2001
From: amin1377 <amin1377.mohaghegh@gmail.com>
Date: Mon, 26 Aug 2024 18:40:05 -0400
Subject: [PATCH 08/12] [test] update strong odin golden

---
 .../config/golden_results.txt                    |  6 +++---
 .../config/golden_results.txt                    |  2 +-
 .../config/golden_results.txt                    | 16 ++++++++--------
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
index ecdb2d74099..5e9d390bcb8 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
@@ -1,4 +1,4 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	4.13	vpr	202.88 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	207748	1	4	28	32	2	10	9	4	4	16	clb	auto	51.9 MiB	0.14	20	27	15	8	4	193.9 MiB	0.03	0.00	2.44626	0	0	2.44626	0.51	0.000583271	0.000535066	0.00308541	0.00258587	8	12	5	72000	72000	5593.62	349.601	0.86	0.0614891	0.0547303	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.010886	0.00952369	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	4.18	vpr	203.46 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	208344	1	4	28	32	2	10	9	4	4	16	clb	auto	52.0 MiB	0.14	20	27	15	8	4	194.0 MiB	0.03	0.00	2.44626	0	0	2.44626	0.51	0.000579833	0.000533235	0.00309464	0.0025854	8	12	5	72000	72000	5593.62	349.601	0.86	0.0608434	0.0541405	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0108096	0.00946964	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	4.13	vpr	202.64 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	207504	1	4	28	32	2	10	9	4	4	16	clb	auto	51.4 MiB	0.14	20	27	15	8	4	193.1 MiB	0.03	0.00	2.44626	0	0	2.44626	0.51	0.000572304	0.000525073	0.00310109	0.00259353	8	12	5	72000	72000	5593.62	349.601	0.86	0.0611009	0.054383	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0108444	0.00950833	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	4.34	vpr	203.48 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	208364	1	4	28	32	2	10	9	4	4	16	clb	auto	51.8 MiB	0.15	20	27	15	8	4	194.0 MiB	0.03	0.00	2.44626	0	0	2.44626	0.52	0.000590751	0.000540821	0.00316208	0.00264441	8	12	5	72000	72000	5593.62	349.601	0.90	0.0650926	0.0576217	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0118781	0.0104259	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	4.30	vpr	203.96 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	208860	1	4	28	32	2	10	9	4	4	16	clb	auto	52.0 MiB	0.15	20	27	15	8	4	194.0 MiB	0.03	0.00	2.44626	0	0	2.44626	0.53	0.000590039	0.000540401	0.00316168	0.00264575	8	12	5	72000	72000	5593.62	349.601	0.91	0.0661082	0.058795	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.011084	0.00968987	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	4.36	vpr	202.70 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	207564	1	4	28	32	2	10	9	4	4	16	clb	auto	51.6 MiB	0.15	20	27	15	8	4	193.4 MiB	0.03	0.00	2.44626	0	0	2.44626	0.52	0.000584676	0.000538033	0.00319424	0.00261523	8	12	5	72000	72000	5593.62	349.601	0.91	0.0673054	0.0593848	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.18	-1	-1	0.01	0.0112706	0.00986656	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt
index e08e6fdcd68..a76acda88a1 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt
@@ -1,2 +1,2 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-timing/k6_N10_40nm.xml	clock_set_delay_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc	3.91	vpr	202.38 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	2	2	-1	-1	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	207240	2	2	22	24	2	4	6	4	4	16	clb	auto	51.8 MiB	0.10	4	15	2	10	3	193.1 MiB	0.02	0.00	1.297	0	0	1.297	0.50	0.000500888	0.000459494	0.00266891	0.00218049	4	6	2	72000	36000	2827.54	176.721	0.84	0.0129763	0.0108607	644	852	-1	6	2	4	4	138	80	1.297	1.297	0	0	0	0	4025.56	251.598	0.01	0.02	0.16	-1	-1	0.01	0.00609768	0.00517486	
+timing/k6_N10_40nm.xml	clock_set_delay_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc	3.91	vpr	201.04 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	2	2	-1	-1	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	205860	2	2	22	24	2	4	6	4	4	16	clb	auto	51.6 MiB	0.11	4	15	2	10	3	193.0 MiB	0.02	0.00	1.297	0	0	1.297	0.53	0.000520067	0.000476752	0.00285601	0.00232812	4	6	2	72000	36000	2827.54	176.721	0.63	0.0112241	0.0092358	644	852	-1	6	2	4	4	138	80	1.297	1.297	0	0	0	0	4025.56	251.598	0.01	0.03	0.17	-1	-1	0.01	0.00632552	0.00538297	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt
index d15e3368469..9441871386b 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt
@@ -1,9 +1,9 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	num_global_nets	num_routed_nets	
-timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	1.26	vpr	188.86 MiB		0.14	21040	-1	-1	1	0.02	-1	-1	33188	-1	-1	1	2	-1	-1	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	193388	2	1	3	4	1	3	4	3	3	9	-1	auto	49.5 MiB	0.02	4	9	3	5	1	184.5 MiB	0.01	0.00	0.55447	-0.91031	-0.55447	0.55447	0.00	0.000183823	0.000174194	0.00100836	0.000790661	-1	2	4	18000	18000	14049.7	1561.07	0.01	0.00460219	0.00375757	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
-timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	1.27	vpr	188.60 MiB		0.14	20628	-1	-1	1	0.02	-1	-1	33332	-1	-1	1	2	-1	-1	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	193124	2	1	3	4	1	3	4	3	3	9	-1	auto	49.3 MiB	0.02	6	9	3	3	3	184.3 MiB	0.01	0.00	0.48631	-0.91031	-0.48631	0.48631	0.00	0.000177321	0.000167639	0.00103736	0.000764866	-1	4	3	18000	18000	15707.9	1745.32	0.01	0.00431966	0.00346039	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
-timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	38.48	odin	761.48 MiB		14.71	779760	-1	-1	2	1.40	-1	-1	54260	-1	-1	155	5	-1	-1	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	335884	5	156	191	347	1	163	316	15	15	225	clb	auto	72.4 MiB	1.22	22	86316	62090	3287	20939	314.6 MiB	8.40	0.11	1.49664	-15.129	-1.49664	1.49664	0.00	0.00426561	0.0040116	0.354616	0.332804	-1	30	6	3.042e+06	2.79e+06	863192.	3836.41	0.18	0.428316	0.401633	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	154	9	
-timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	38.42	odin	761.69 MiB		14.65	779972	-1	-1	2	1.39	-1	-1	54048	-1	-1	155	5	-1	-1	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	336664	5	156	191	347	1	163	316	15	15	225	clb	auto	72.6 MiB	1.21	25	86316	61881	3554	20881	315.7 MiB	8.36	0.10	1.47767	-14.8876	-1.47767	1.47767	0.00	0.00425682	0.00401442	0.358109	0.335378	-1	53	7	3.042e+06	2.79e+06	892591.	3967.07	0.20	0.440276	0.412199	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	153	10	
-timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	6.86	vpr	218.88 MiB		2.30	38132	-1	-1	1	0.02	-1	-1	33428	-1	-1	1	2	0	0	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	224132	2	1	3	4	1	3	4	3	3	9	-1	auto	76.7 MiB	0.03	4	9	3	5	1	213.6 MiB	0.01	0.00	0.55247	-0.90831	-0.55247	0.55247	0.00	0.000178865	0.000169268	0.000984461	0.000772611	-1	2	3	53894	53894	12370.0	1374.45	0.01	0.00430389	0.00350335	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
-timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	6.87	vpr	218.13 MiB		2.29	38336	-1	-1	1	0.02	-1	-1	33336	-1	-1	1	2	0	0	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	223364	2	1	3	4	1	3	4	3	3	9	-1	auto	76.9 MiB	0.03	6	9	3	3	3	213.9 MiB	0.01	0.00	0.48631	-0.90831	-0.48631	0.48631	0.00	0.000188486	0.000177671	0.00107327	0.000808747	-1	4	2	53894	53894	14028.3	1558.70	0.01	0.00421058	0.00337424	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
-timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	109.20	odin	592.18 MiB		9.76	606396	-1	-1	2	0.16	-1	-1	37412	-1	-1	32	311	15	0	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	550636	311	156	972	1128	1	953	514	28	28	784	memory	auto	195.3 MiB	10.16	8852	208372	78139	120196	10037	514.6 MiB	40.87	0.47	4.11307	-4320.89	-4.11307	4.11307	0.02	0.1118	0.105538	11.7033	11.043	-1	13295	15	4.25198e+07	9.94461e+06	2.96205e+06	3778.13	6.89	15.5574	14.7523	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	15	938	
-timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	111.94	odin	592.37 MiB		9.78	606588	-1	-1	2	0.16	-1	-1	37320	-1	-1	32	311	15	0	success	84e0337-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:44:22	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	553664	311	156	972	1128	1	953	514	28	28	784	memory	auto	195.3 MiB	10.22	8741	214546	82147	122429	9970	513.9 MiB	42.14	0.46	4.83167	-3665.82	-4.83167	4.83167	0.02	0.112871	0.106525	12.0865	11.4105	-1	13585	17	4.25198e+07	9.94461e+06	3.02951e+06	3864.17	7.65	16.4571	15.6143	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	14	939	
+timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	1.32	vpr	188.94 MiB		0.15	20836	-1	-1	1	0.02	-1	-1	33556	-1	-1	1	2	-1	-1	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	193476	2	1	3	4	1	3	4	3	3	9	-1	auto	49.4 MiB	0.02	4	9	3	5	1	184.4 MiB	0.01	0.00	0.55447	-0.91031	-0.55447	0.55447	0.00	0.000193623	0.000183054	0.00103055	0.000810022	-1	2	4	18000	18000	14049.7	1561.07	0.01	0.0048381	0.00395026	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
+timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	3.24	vpr	389.26 MiB		0.15	20660	-1	-1	1	0.02	-1	-1	33500	-1	-1	1	2	-1	-1	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	398600	2	1	3	4	1	3	4	3	3	9	-1	auto	49.7 MiB	0.02	6	9	3	3	3	185.0 MiB	0.01	0.00	0.48631	-0.91031	-0.48631	0.48631	0.00	0.000181957	0.000170609	0.00112245	0.000838041	-1	4	3	18000	18000	15707.9	1745.32	0.01	0.00480652	0.00384951	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
+timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	40.21	odin	761.48 MiB		15.23	779752	-1	-1	2	1.56	-1	-1	54136	-1	-1	155	5	-1	-1	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	335364	5	156	191	347	1	163	316	15	15	225	clb	auto	72.2 MiB	1.25	22	86316	62090	3287	20939	314.2 MiB	8.84	0.11	1.49664	-15.129	-1.49664	1.49664	0.00	0.00431013	0.00404742	0.372331	0.349617	-1	30	6	3.042e+06	2.79e+06	863192.	3836.41	0.20	0.451961	0.423884	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	154	9	
+timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	39.93	odin	761.83 MiB		15.17	780116	-1	-1	2	1.53	-1	-1	54700	-1	-1	155	5	-1	-1	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	336768	5	156	191	347	1	163	316	15	15	225	clb	auto	72.3 MiB	1.26	25	86316	61881	3554	20881	315.4 MiB	8.76	0.11	1.47767	-14.8876	-1.47767	1.47767	0.00	0.0044121	0.00414772	0.368517	0.344531	-1	53	7	3.042e+06	2.79e+06	892591.	3967.07	0.20	0.453918	0.424453	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	153	10	
+timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	7.14	vpr	218.73 MiB		2.38	38404	-1	-1	1	0.02	-1	-1	33284	-1	-1	1	2	0	0	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	223976	2	1	3	4	1	3	4	3	3	9	-1	auto	76.7 MiB	0.03	4	9	3	5	1	213.7 MiB	0.01	0.00	0.55247	-0.90831	-0.55247	0.55247	0.00	0.000178118	0.000166931	0.00103229	0.000812039	-1	2	3	53894	53894	12370.0	1374.45	0.01	0.00477196	0.0038942	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
+timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	7.15	vpr	218.62 MiB		2.33	38548	-1	-1	1	0.02	-1	-1	33516	-1	-1	1	2	0	0	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	223864	2	1	3	4	1	3	4	3	3	9	-1	auto	76.6 MiB	0.03	6	9	3	3	3	213.5 MiB	0.01	0.00	0.48631	-0.90831	-0.48631	0.48631	0.00	0.000177024	0.000166252	0.00108735	0.000812692	-1	4	2	53894	53894	14028.3	1558.70	0.01	0.00458707	0.00366792	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
+timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	114.37	odin	592.19 MiB		10.19	606404	-1	-1	2	0.17	-1	-1	37520	-1	-1	32	311	15	0	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	550036	311	156	972	1128	1	953	514	28	28	784	memory	auto	194.9 MiB	10.54	8852	208372	78139	120196	10037	513.9 MiB	43.26	0.49	4.11307	-4320.89	-4.11307	4.11307	0.02	0.114756	0.108193	12.2516	11.5561	-1	13295	15	4.25198e+07	9.94461e+06	2.96205e+06	3778.13	7.31	16.3344	15.4821	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	15	938	
+timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	118.43	odin	592.16 MiB		10.13	606368	-1	-1	2	0.17	-1	-1	37528	-1	-1	32	311	15	0	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	553884	311	156	972	1128	1	953	514	28	28	784	memory	auto	195.5 MiB	10.77	8741	214546	82147	122429	9970	513.9 MiB	45.11	0.49	4.83167	-3665.82	-4.83167	4.83167	0.02	0.117476	0.111037	12.6577	11.9566	-1	13585	17	4.25198e+07	9.94461e+06	3.02951e+06	3864.17	8.13	17.291	16.417	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	14	939	

From 4d775c61c62ca18597aa79af1bf321731a9503c4 Mon Sep 17 00:00:00 2001
From: amin1377 <amin1377.mohaghegh@gmail.com>
Date: Tue, 27 Aug 2024 17:59:45 -0400
Subject: [PATCH 09/12] [test] update reg strong/odin

---
 .../config/golden_results.txt                    |  4 ++--
 .../config/golden_results.txt                    |  6 +++---
 .../config/golden_results.txt                    |  2 +-
 .../config/golden_results.txt                    | 16 ++++++++--------
 .../config/golden_results.txt                    |  4 ++--
 5 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt
index aeff2922e33..65afefc1140 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt
@@ -1,3 +1,3 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-k6_N10_40nm.xml	stereovision0.v	common	140.15	vpr	272.04 MiB		-1	-1	12.85	119508	5	37.98	-1	-1	65828	-1	-1	1307	169	-1	-1	success	v8.0.0-10642-gf11aaea3f	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	2024-07-18T10:51:58	betzgrp-wintermute.eecg.utoronto.ca	/home/mahmo494/Desktop/inc_dec_wires/vtr-verilog-to-routing/vtr_flow/tasks	278564	169	197	21166	21363	1	7566	1673	39	39	1521	clb	auto	140.8 MiB	3.95	53142	974519	347458	607168	19893	272.0 MiB	10.23	0.10	3.63366	-15348.4	-3.63366	3.63366	9.71	0.0315035	0.026913	3.45179	2.89228	44	69063	46	7.37824e+07	7.04408e+07	4.68145e+06	3077.88	43.27	19.1637	16.0718	125110	968779	-1	63965	24	33902	65662	2813140	489196	3.57565	3.57565	-16119.5	-3.57565	0	0	6.05227e+06	3979.14	1.97	2.96	0.84	-1	-1	1.97	2.09287	1.80452	
-k6_N10_40nm_diff_switch_for_inc_dec_wires.xml	stereovision0.v	common	138.68	vpr	271.91 MiB		-1	-1	12.57	119440	5	36.46	-1	-1	65388	-1	-1	1307	169	-1	-1	success	v8.0.0-10642-gf11aaea3f	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	2024-07-18T10:51:58	betzgrp-wintermute.eecg.utoronto.ca	/home/mahmo494/Desktop/inc_dec_wires/vtr-verilog-to-routing/vtr_flow/tasks	278432	169	197	21166	21363	1	7566	1673	39	39	1521	clb	auto	140.7 MiB	3.96	53142	974519	347458	607168	19893	271.9 MiB	11.12	0.11	3.63366	-15348.4	-3.63366	3.63366	9.48	0.037164	0.0323029	4.04546	3.42407	44	69063	46	7.37824e+07	7.04408e+07	4.68145e+06	3077.88	43.94	19.9593	16.7643	125110	968779	-1	63965	24	33902	65662	2813140	489196	3.57565	3.57565	-16119.5	-3.57565	0	0	6.05227e+06	3979.14	2.02	2.80	0.83	-1	-1	2.02	1.87812	1.62699	
+k6_N10_40nm.xml	stereovision0.v	common	122.65	vpr	276.58 MiB		-1	-1	16.00	124916	5	53.73	-1	-1	69176	-1	-1	1305	169	-1	-1	success	28100b1	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:45:19	gh-actions-runner-vtr-auto-spawned39	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	283220	169	197	21117	21314	1	7688	1671	39	39	1521	clb	auto	143.1 MiB	2.85	53732	982959	351248	609845	21866	276.6 MiB	9.99	0.10	3.76204	-15507.8	-3.76204	3.76204	9.44	0.0159737	0.0133362	1.80765	1.48264	42	70545	48	2.4642e+07	2.349e+07	4.65856e+06	3062.82	15.47	6.76385	5.69	122070	947469	-1	65863	22	34742	65762	3361891	541264	4.0937	4.0937	-16235.4	-4.0937	0	0	5.79504e+06	3810.02	1.92	1.71	0.57	-1	-1	1.92	1.12349	0.992148	
+k6_N10_40nm_diff_switch_for_inc_dec_wires.xml	stereovision0.v	common	134.93	vpr	274.07 MiB		-1	-1	16.21	125172	5	55.27	-1	-1	68860	-1	-1	1305	169	-1	-1	success	28100b1	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:45:19	gh-actions-runner-vtr-auto-spawned39	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	280648	169	197	21117	21314	1	7523	1671	39	39	1521	clb	auto	143.0 MiB	2.85	51811	1022607	376856	616274	29477	274.1 MiB	10.32	0.10	3.69006	-14773.1	-3.69006	3.69006	9.39	0.0156983	0.0130538	1.86259	1.52838	38	69466	48	7.37824e+07	7.0333e+07	4.16760e+06	2740.04	25.94	8.42194	7.05848	119030	845795	-1	62788	23	35878	68950	2803037	507578	3.5696	3.5696	-16170.3	-3.5696	0	0	5.22668e+06	3436.35	1.75	1.68	0.49	-1	-1	1.75	1.12315	0.986398	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
index 5e9d390bcb8..1c0aa04d923 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
@@ -1,4 +1,4 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	4.34	vpr	203.48 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	208364	1	4	28	32	2	10	9	4	4	16	clb	auto	51.8 MiB	0.15	20	27	15	8	4	194.0 MiB	0.03	0.00	2.44626	0	0	2.44626	0.52	0.000590751	0.000540821	0.00316208	0.00264441	8	12	5	72000	72000	5593.62	349.601	0.90	0.0650926	0.0576217	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0118781	0.0104259	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	4.30	vpr	203.96 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	208860	1	4	28	32	2	10	9	4	4	16	clb	auto	52.0 MiB	0.15	20	27	15	8	4	194.0 MiB	0.03	0.00	2.44626	0	0	2.44626	0.53	0.000590039	0.000540401	0.00316168	0.00264575	8	12	5	72000	72000	5593.62	349.601	0.91	0.0661082	0.058795	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.011084	0.00968987	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	4.36	vpr	202.70 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	207564	1	4	28	32	2	10	9	4	4	16	clb	auto	51.6 MiB	0.15	20	27	15	8	4	193.4 MiB	0.03	0.00	2.44626	0	0	2.44626	0.52	0.000584676	0.000538033	0.00319424	0.00261523	8	12	5	72000	72000	5593.62	349.601	0.91	0.0673054	0.0593848	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.18	-1	-1	0.01	0.0112706	0.00986656	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	4.07	vpr	203.36 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	208244	1	4	28	32	2	10	9	4	4	16	clb	auto	52.2 MiB	0.14	20	27	15	8	4	193.9 MiB	0.03	0.00	2.44626	0	0	2.44626	0.50	0.000571891	0.000524572	0.00307425	0.00256774	8	12	5	72000	72000	5593.62	349.601	0.85	0.0613454	0.0545823	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.010792	0.00942798	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	4.11	vpr	203.34 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	208224	1	4	28	32	2	10	9	4	4	16	clb	auto	51.7 MiB	0.14	20	27	15	8	4	193.4 MiB	0.03	0.00	2.44626	0	0	2.44626	0.50	0.00058752	0.000534007	0.00311595	0.0026124	8	12	5	72000	72000	5593.62	349.601	0.83	0.0566783	0.0504183	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0110182	0.00964784	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	5.95	vpr	203.75 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	208644	1	4	28	32	2	10	9	4	4	16	clb	auto	52.1 MiB	0.14	20	27	15	8	4	193.9 MiB	0.03	0.00	2.44626	0	0	2.44626	0.48	0.000574077	0.000526413	0.00309971	0.00259288	8	12	5	72000	72000	5593.62	349.601	0.85	0.061428	0.0545572	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0109867	0.00962922	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt
index a76acda88a1..55149fd5d45 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt
@@ -1,2 +1,2 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-timing/k6_N10_40nm.xml	clock_set_delay_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc	3.91	vpr	201.04 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	2	2	-1	-1	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	205860	2	2	22	24	2	4	6	4	4	16	clb	auto	51.6 MiB	0.11	4	15	2	10	3	193.0 MiB	0.02	0.00	1.297	0	0	1.297	0.53	0.000520067	0.000476752	0.00285601	0.00232812	4	6	2	72000	36000	2827.54	176.721	0.63	0.0112241	0.0092358	644	852	-1	6	2	4	4	138	80	1.297	1.297	0	0	0	0	4025.56	251.598	0.01	0.03	0.17	-1	-1	0.01	0.00632552	0.00538297	
+timing/k6_N10_40nm.xml	clock_set_delay_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc	3.64	vpr	201.25 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	2	2	-1	-1	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	206076	2	2	22	24	2	4	6	4	4	16	clb	auto	51.9 MiB	0.10	4	15	2	10	3	193.2 MiB	0.02	0.00	1.297	0	0	1.297	0.50	0.00047801	0.000438708	0.00256566	0.00209288	4	6	2	72000	36000	2827.54	176.721	0.59	0.0102637	0.00844197	644	852	-1	6	2	4	4	138	80	1.297	1.297	0	0	0	0	4025.56	251.598	0.01	0.02	0.16	-1	-1	0.01	0.00594057	0.00506721	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt
index 9441871386b..f66c440549a 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt
@@ -1,9 +1,9 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	num_global_nets	num_routed_nets	
-timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	1.32	vpr	188.94 MiB		0.15	20836	-1	-1	1	0.02	-1	-1	33556	-1	-1	1	2	-1	-1	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	193476	2	1	3	4	1	3	4	3	3	9	-1	auto	49.4 MiB	0.02	4	9	3	5	1	184.4 MiB	0.01	0.00	0.55447	-0.91031	-0.55447	0.55447	0.00	0.000193623	0.000183054	0.00103055	0.000810022	-1	2	4	18000	18000	14049.7	1561.07	0.01	0.0048381	0.00395026	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
-timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	3.24	vpr	389.26 MiB		0.15	20660	-1	-1	1	0.02	-1	-1	33500	-1	-1	1	2	-1	-1	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	398600	2	1	3	4	1	3	4	3	3	9	-1	auto	49.7 MiB	0.02	6	9	3	3	3	185.0 MiB	0.01	0.00	0.48631	-0.91031	-0.48631	0.48631	0.00	0.000181957	0.000170609	0.00112245	0.000838041	-1	4	3	18000	18000	15707.9	1745.32	0.01	0.00480652	0.00384951	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
-timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	40.21	odin	761.48 MiB		15.23	779752	-1	-1	2	1.56	-1	-1	54136	-1	-1	155	5	-1	-1	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	335364	5	156	191	347	1	163	316	15	15	225	clb	auto	72.2 MiB	1.25	22	86316	62090	3287	20939	314.2 MiB	8.84	0.11	1.49664	-15.129	-1.49664	1.49664	0.00	0.00431013	0.00404742	0.372331	0.349617	-1	30	6	3.042e+06	2.79e+06	863192.	3836.41	0.20	0.451961	0.423884	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	154	9	
-timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	39.93	odin	761.83 MiB		15.17	780116	-1	-1	2	1.53	-1	-1	54700	-1	-1	155	5	-1	-1	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	336768	5	156	191	347	1	163	316	15	15	225	clb	auto	72.3 MiB	1.26	25	86316	61881	3554	20881	315.4 MiB	8.76	0.11	1.47767	-14.8876	-1.47767	1.47767	0.00	0.0044121	0.00414772	0.368517	0.344531	-1	53	7	3.042e+06	2.79e+06	892591.	3967.07	0.20	0.453918	0.424453	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	153	10	
-timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	7.14	vpr	218.73 MiB		2.38	38404	-1	-1	1	0.02	-1	-1	33284	-1	-1	1	2	0	0	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	223976	2	1	3	4	1	3	4	3	3	9	-1	auto	76.7 MiB	0.03	4	9	3	5	1	213.7 MiB	0.01	0.00	0.55247	-0.90831	-0.55247	0.55247	0.00	0.000178118	0.000166931	0.00103229	0.000812039	-1	2	3	53894	53894	12370.0	1374.45	0.01	0.00477196	0.0038942	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
-timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	7.15	vpr	218.62 MiB		2.33	38548	-1	-1	1	0.02	-1	-1	33516	-1	-1	1	2	0	0	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	223864	2	1	3	4	1	3	4	3	3	9	-1	auto	76.6 MiB	0.03	6	9	3	3	3	213.5 MiB	0.01	0.00	0.48631	-0.90831	-0.48631	0.48631	0.00	0.000177024	0.000166252	0.00108735	0.000812692	-1	4	2	53894	53894	14028.3	1558.70	0.01	0.00458707	0.00366792	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
-timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	114.37	odin	592.19 MiB		10.19	606404	-1	-1	2	0.17	-1	-1	37520	-1	-1	32	311	15	0	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	550036	311	156	972	1128	1	953	514	28	28	784	memory	auto	194.9 MiB	10.54	8852	208372	78139	120196	10037	513.9 MiB	43.26	0.49	4.11307	-4320.89	-4.11307	4.11307	0.02	0.114756	0.108193	12.2516	11.5561	-1	13295	15	4.25198e+07	9.94461e+06	2.96205e+06	3778.13	7.31	16.3344	15.4821	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	15	938	
-timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	118.43	odin	592.16 MiB		10.13	606368	-1	-1	2	0.17	-1	-1	37528	-1	-1	32	311	15	0	success	884dcc8-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-25T20:48:27	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	553884	311	156	972	1128	1	953	514	28	28	784	memory	auto	195.5 MiB	10.77	8741	214546	82147	122429	9970	513.9 MiB	45.11	0.49	4.83167	-3665.82	-4.83167	4.83167	0.02	0.117476	0.111037	12.6577	11.9566	-1	13585	17	4.25198e+07	9.94461e+06	3.02951e+06	3864.17	8.13	17.291	16.417	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	14	939	
+timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	1.24	vpr	188.77 MiB		0.14	20652	-1	-1	1	0.02	-1	-1	33340	-1	-1	1	2	-1	-1	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	193300	2	1	3	4	1	3	4	3	3	9	-1	auto	49.7 MiB	0.02	4	9	3	5	1	184.5 MiB	0.01	0.00	0.55447	-0.91031	-0.55447	0.55447	0.00	0.000172585	0.000163824	0.000970606	0.000762723	-1	2	4	18000	18000	14049.7	1561.07	0.01	0.00445731	0.00365507	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
+timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	1.28	vpr	188.76 MiB		0.14	20616	-1	-1	1	0.02	-1	-1	33520	-1	-1	1	2	-1	-1	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	193288	2	1	3	4	1	3	4	3	3	9	-1	auto	49.4 MiB	0.02	6	9	3	3	3	184.3 MiB	0.01	0.00	0.48631	-0.91031	-0.48631	0.48631	0.00	0.000174933	0.000164528	0.001039	0.000771883	-1	4	3	18000	18000	15707.9	1745.32	0.01	0.00430835	0.00346477	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
+timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	37.61	odin	761.60 MiB		14.38	779876	-1	-1	2	1.41	-1	-1	54528	-1	-1	155	5	-1	-1	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	335744	5	156	191	347	1	163	316	15	15	225	clb	auto	72.1 MiB	1.19	22	86316	62090	3287	20939	314.2 MiB	8.06	0.11	1.49664	-15.129	-1.49664	1.49664	0.00	0.00419551	0.0039364	0.344907	0.323331	-1	30	6	3.042e+06	2.79e+06	863192.	3836.41	0.18	0.418275	0.391804	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	154	9	
+timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	37.67	odin	761.58 MiB		14.28	779856	-1	-1	2	1.37	-1	-1	54264	-1	-1	155	5	-1	-1	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	337116	5	156	191	347	1	163	316	15	15	225	clb	auto	72.7 MiB	1.18	25	86316	61881	3554	20881	315.5 MiB	8.17	0.10	1.47767	-14.8876	-1.47767	1.47767	0.00	0.00422007	0.00396367	0.349813	0.326796	-1	53	7	3.042e+06	2.79e+06	892591.	3967.07	0.19	0.430322	0.402063	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	153	10	
+timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	6.73	vpr	217.91 MiB		2.23	38372	-1	-1	1	0.02	-1	-1	33500	-1	-1	1	2	0	0	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	223136	2	1	3	4	1	3	4	3	3	9	-1	auto	76.6 MiB	0.03	4	9	3	5	1	212.9 MiB	0.01	0.00	0.55247	-0.90831	-0.55247	0.55247	0.00	0.000172148	0.000163075	0.000979512	0.000772784	-1	2	3	53894	53894	12370.0	1374.45	0.01	0.00428296	0.00349453	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
+timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	6.75	vpr	218.53 MiB		2.23	38108	-1	-1	1	0.02	-1	-1	33428	-1	-1	1	2	0	0	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	223772	2	1	3	4	1	3	4	3	3	9	-1	auto	76.8 MiB	0.03	6	9	3	3	3	213.7 MiB	0.01	0.00	0.48631	-0.90831	-0.48631	0.48631	0.00	0.00017534	0.000165209	0.00105029	0.000783127	-1	4	2	53894	53894	14028.3	1558.70	0.01	0.00415274	0.00331925	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
+timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	108.57	odin	592.08 MiB		9.60	606288	-1	-1	2	0.16	-1	-1	37608	-1	-1	32	311	15	0	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	550592	311	156	972	1128	1	953	514	28	28	784	memory	auto	195.5 MiB	10.08	8852	208372	78139	120196	10037	514.7 MiB	40.55	0.47	4.11307	-4320.89	-4.11307	4.11307	0.02	0.111322	0.104853	11.6537	10.9748	-1	13295	15	4.25198e+07	9.94461e+06	2.96205e+06	3778.13	7.00	15.5787	14.7468	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	15	938	
+timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	110.53	odin	592.16 MiB		9.55	606368	-1	-1	2	0.16	-1	-1	37464	-1	-1	32	311	15	0	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	553708	311	156	972	1128	1	953	514	28	28	784	memory	auto	195.6 MiB	10.10	8741	214546	82147	122429	9970	514.2 MiB	41.52	0.45	4.83167	-3665.82	-4.83167	4.83167	0.02	0.110642	0.104324	11.9239	11.2422	-1	13585	17	4.25198e+07	9.94461e+06	3.02951e+06	3864.17	7.48	16.2268	15.3775	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	14	939	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt
index 873a4df06d4..f34151c1528 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt
@@ -1,3 +1,3 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-k6_N10_40nm.xml	stereovision0.v	common	170.85	vpr	277.04 MiB		2.40	125884	-1	-1	5	83.06	-1	-1	75508	-1	-1	1297	157	-1	-1	success	v8.0.0-10644-gbada3f40f	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	2024-07-18T12:52:25	betzgrp-wintermute.eecg.utoronto.ca	/home/mahmo494/Desktop/inc_dec_wires/vtr-verilog-to-routing/vtr_flow/tasks	283692	157	197	21024	21221	1	7547	1651	39	39	1521	clb	auto	144.7 MiB	3.96	51912	967297	355681	587577	24039	277.0 MiB	10.10	0.10	3.27987	-14557.4	-3.27987	3.27987	9.63	0.0317477	0.0266474	3.48443	2.90114	46	64729	31	7.37824e+07	6.99019e+07	4.88195e+06	3209.70	35.95	15.7549	13.2195	126630	998267	-1	62442	28	35421	67860	2863040	490307	3.17524	3.17524	-15310.6	-3.17524	0	0	6.27360e+06	4124.65	1.97	3.27	0.83	-1	-1	1.97	2.34241	2.01697	
-k6_N10_40nm_diff_switch_for_inc_dec_wires.xml	stereovision0.v	common	170.38	vpr	277.10 MiB		2.43	126080	-1	-1	5	82.80	-1	-1	75404	-1	-1	1297	157	-1	-1	success	v8.0.0-10644-gbada3f40f	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	2024-07-18T12:52:25	betzgrp-wintermute.eecg.utoronto.ca	/home/mahmo494/Desktop/inc_dec_wires/vtr-verilog-to-routing/vtr_flow/tasks	283748	157	197	21024	21221	1	7547	1651	39	39	1521	clb	auto	144.6 MiB	4.05	51912	967297	355681	587577	24039	277.1 MiB	10.27	0.10	3.27987	-14557.4	-3.27987	3.27987	9.61	0.0323462	0.0271905	3.52052	2.92391	46	64729	31	7.37824e+07	6.99019e+07	4.88195e+06	3209.70	34.80	15.1519	12.6486	126630	998267	-1	62442	28	35421	67860	2863040	490307	3.17524	3.17524	-15310.6	-3.17524	0	0	6.27360e+06	4124.65	1.87	3.85	0.81	-1	-1	1.87	2.71824	2.34292	
+k6_N10_40nm.xml	stereovision0.v	common	1424.21	odin	1.76 GiB		98.01	1840532	-1	-1	5	86.92	-1	-1	79188	-1	-1	1290	157	-1	-1	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	1127628	157	197	21024	21221	1	7745	1644	38	38	1444	clb	auto	784.9 MiB	142.70	54476	961845	345093	595347	21405	1018.4 MiB	226.12	2.31	4.1021	-15015.6	-4.1021	4.1021	127.72	0.391313	0.346271	40.1408	35.4135	46	66086	26	2.3328e+07	2.322e+07	4.77644e+06	3307.78	407.25	137.599	124.407	120184	989140	-1	64416	19	33992	65277	2895642	459795	3.87727	3.87727	-15760.1	-3.87727	0	0	6.15323e+06	4261.24	6.62	24.31	15.33	-1	-1	6.62	8.59946	7.93086	
+k6_N10_40nm_diff_switch_for_inc_dec_wires.xml	stereovision0.v	common	1461.05	odin	1.76 GiB		97.93	1840552	-1	-1	5	86.85	-1	-1	79520	-1	-1	1297	157	-1	-1	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	1134244	157	197	21024	21221	1	7547	1651	39	39	1521	clb	auto	793.5 MiB	146.87	51912	967297	355681	587577	24039	1015.9 MiB	226.98	2.33	3.27987	-14557.4	-3.27987	3.27987	134.65	0.393187	0.344536	40.3549	35.4133	46	64729	31	7.37824e+07	6.99019e+07	4.88195e+06	3209.70	433.25	142.554	128.65	126630	998267	-1	62442	28	35421	67860	2863040	490307	3.17524	3.17524	-15310.6	-3.17524	0	0	6.27360e+06	4124.65	6.93	28.63	16.02	-1	-1	6.93	11.9796	11.034	

From 84624ac365008078df186b1812aaedf5f25dedbe Mon Sep 17 00:00:00 2001
From: amin1377 <amin1377.mohaghegh@gmail.com>
Date: Tue, 27 Aug 2024 18:51:08 -0400
Subject: [PATCH 10/12] update strong odin

---
 .../config/golden_results.txt                    |  6 +++---
 .../config/golden_results.txt                    |  2 +-
 .../config/golden_results.txt                    | 16 ++++++++--------
 .../config/golden_results.txt                    |  4 ++--
 4 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
index 1c0aa04d923..0e6dc420714 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
@@ -1,4 +1,4 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	4.07	vpr	203.36 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	208244	1	4	28	32	2	10	9	4	4	16	clb	auto	52.2 MiB	0.14	20	27	15	8	4	193.9 MiB	0.03	0.00	2.44626	0	0	2.44626	0.50	0.000571891	0.000524572	0.00307425	0.00256774	8	12	5	72000	72000	5593.62	349.601	0.85	0.0613454	0.0545823	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.010792	0.00942798	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	4.11	vpr	203.34 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	208224	1	4	28	32	2	10	9	4	4	16	clb	auto	51.7 MiB	0.14	20	27	15	8	4	193.4 MiB	0.03	0.00	2.44626	0	0	2.44626	0.50	0.00058752	0.000534007	0.00311595	0.0026124	8	12	5	72000	72000	5593.62	349.601	0.83	0.0566783	0.0504183	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0110182	0.00964784	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	5.95	vpr	203.75 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	208644	1	4	28	32	2	10	9	4	4	16	clb	auto	52.1 MiB	0.14	20	27	15	8	4	193.9 MiB	0.03	0.00	2.44626	0	0	2.44626	0.48	0.000574077	0.000526413	0.00309971	0.00259288	8	12	5	72000	72000	5593.62	349.601	0.85	0.061428	0.0545572	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0109867	0.00962922	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt
index 55149fd5d45..64742271fed 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt
@@ -1,2 +1,2 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-timing/k6_N10_40nm.xml	clock_set_delay_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc	3.64	vpr	201.25 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	2	2	-1	-1	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	206076	2	2	22	24	2	4	6	4	4	16	clb	auto	51.9 MiB	0.10	4	15	2	10	3	193.2 MiB	0.02	0.00	1.297	0	0	1.297	0.50	0.00047801	0.000438708	0.00256566	0.00209288	4	6	2	72000	36000	2827.54	176.721	0.59	0.0102637	0.00844197	644	852	-1	6	2	4	4	138	80	1.297	1.297	0	0	0	0	4025.56	251.598	0.01	0.02	0.16	-1	-1	0.01	0.00594057	0.00506721	
+timing/k6_N10_40nm.xml	clock_set_delay_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt
index f66c440549a..425790ca8b7 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt
@@ -1,9 +1,9 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	num_global_nets	num_routed_nets	
-timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	1.24	vpr	188.77 MiB		0.14	20652	-1	-1	1	0.02	-1	-1	33340	-1	-1	1	2	-1	-1	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	193300	2	1	3	4	1	3	4	3	3	9	-1	auto	49.7 MiB	0.02	4	9	3	5	1	184.5 MiB	0.01	0.00	0.55447	-0.91031	-0.55447	0.55447	0.00	0.000172585	0.000163824	0.000970606	0.000762723	-1	2	4	18000	18000	14049.7	1561.07	0.01	0.00445731	0.00365507	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
-timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	1.28	vpr	188.76 MiB		0.14	20616	-1	-1	1	0.02	-1	-1	33520	-1	-1	1	2	-1	-1	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	193288	2	1	3	4	1	3	4	3	3	9	-1	auto	49.4 MiB	0.02	6	9	3	3	3	184.3 MiB	0.01	0.00	0.48631	-0.91031	-0.48631	0.48631	0.00	0.000174933	0.000164528	0.001039	0.000771883	-1	4	3	18000	18000	15707.9	1745.32	0.01	0.00430835	0.00346477	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
-timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	37.61	odin	761.60 MiB		14.38	779876	-1	-1	2	1.41	-1	-1	54528	-1	-1	155	5	-1	-1	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	335744	5	156	191	347	1	163	316	15	15	225	clb	auto	72.1 MiB	1.19	22	86316	62090	3287	20939	314.2 MiB	8.06	0.11	1.49664	-15.129	-1.49664	1.49664	0.00	0.00419551	0.0039364	0.344907	0.323331	-1	30	6	3.042e+06	2.79e+06	863192.	3836.41	0.18	0.418275	0.391804	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	154	9	
-timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	37.67	odin	761.58 MiB		14.28	779856	-1	-1	2	1.37	-1	-1	54264	-1	-1	155	5	-1	-1	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	337116	5	156	191	347	1	163	316	15	15	225	clb	auto	72.7 MiB	1.18	25	86316	61881	3554	20881	315.5 MiB	8.17	0.10	1.47767	-14.8876	-1.47767	1.47767	0.00	0.00422007	0.00396367	0.349813	0.326796	-1	53	7	3.042e+06	2.79e+06	892591.	3967.07	0.19	0.430322	0.402063	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	153	10	
-timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	6.73	vpr	217.91 MiB		2.23	38372	-1	-1	1	0.02	-1	-1	33500	-1	-1	1	2	0	0	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	223136	2	1	3	4	1	3	4	3	3	9	-1	auto	76.6 MiB	0.03	4	9	3	5	1	212.9 MiB	0.01	0.00	0.55247	-0.90831	-0.55247	0.55247	0.00	0.000172148	0.000163075	0.000979512	0.000772784	-1	2	3	53894	53894	12370.0	1374.45	0.01	0.00428296	0.00349453	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
-timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	6.75	vpr	218.53 MiB		2.23	38108	-1	-1	1	0.02	-1	-1	33428	-1	-1	1	2	0	0	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	223772	2	1	3	4	1	3	4	3	3	9	-1	auto	76.8 MiB	0.03	6	9	3	3	3	213.7 MiB	0.01	0.00	0.48631	-0.90831	-0.48631	0.48631	0.00	0.00017534	0.000165209	0.00105029	0.000783127	-1	4	2	53894	53894	14028.3	1558.70	0.01	0.00415274	0.00331925	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
-timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	108.57	odin	592.08 MiB		9.60	606288	-1	-1	2	0.16	-1	-1	37608	-1	-1	32	311	15	0	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	550592	311	156	972	1128	1	953	514	28	28	784	memory	auto	195.5 MiB	10.08	8852	208372	78139	120196	10037	514.7 MiB	40.55	0.47	4.11307	-4320.89	-4.11307	4.11307	0.02	0.111322	0.104853	11.6537	10.9748	-1	13295	15	4.25198e+07	9.94461e+06	2.96205e+06	3778.13	7.00	15.5787	14.7468	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	15	938	
-timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	110.53	odin	592.16 MiB		9.55	606368	-1	-1	2	0.16	-1	-1	37464	-1	-1	32	311	15	0	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	553708	311	156	972	1128	1	953	514	28	28	784	memory	auto	195.6 MiB	10.10	8741	214546	82147	122429	9970	514.2 MiB	41.52	0.45	4.83167	-3665.82	-4.83167	4.83167	0.02	0.110642	0.104324	11.9239	11.2422	-1	13585	17	4.25198e+07	9.94461e+06	3.02951e+06	3864.17	7.48	16.2268	15.3775	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	14	939	
+timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt
index f34151c1528..6198ac5edde 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt
@@ -1,3 +1,3 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-k6_N10_40nm.xml	stereovision0.v	common	1424.21	odin	1.76 GiB		98.01	1840532	-1	-1	5	86.92	-1	-1	79188	-1	-1	1290	157	-1	-1	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	1127628	157	197	21024	21221	1	7745	1644	38	38	1444	clb	auto	784.9 MiB	142.70	54476	961845	345093	595347	21405	1018.4 MiB	226.12	2.31	4.1021	-15015.6	-4.1021	4.1021	127.72	0.391313	0.346271	40.1408	35.4135	46	66086	26	2.3328e+07	2.322e+07	4.77644e+06	3307.78	407.25	137.599	124.407	120184	989140	-1	64416	19	33992	65277	2895642	459795	3.87727	3.87727	-15760.1	-3.87727	0	0	6.15323e+06	4261.24	6.62	24.31	15.33	-1	-1	6.62	8.59946	7.93086	
-k6_N10_40nm_diff_switch_for_inc_dec_wires.xml	stereovision0.v	common	1461.05	odin	1.76 GiB		97.93	1840552	-1	-1	5	86.85	-1	-1	79520	-1	-1	1297	157	-1	-1	success	28100b1-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-26T22:49:29	gh-actions-runner-vtr-auto-spawned147	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	1134244	157	197	21024	21221	1	7547	1651	39	39	1521	clb	auto	793.5 MiB	146.87	51912	967297	355681	587577	24039	1015.9 MiB	226.98	2.33	3.27987	-14557.4	-3.27987	3.27987	134.65	0.393187	0.344536	40.3549	35.4133	46	64729	31	7.37824e+07	6.99019e+07	4.88195e+06	3209.70	433.25	142.554	128.65	126630	998267	-1	62442	28	35421	67860	2863040	490307	3.17524	3.17524	-15310.6	-3.17524	0	0	6.27360e+06	4124.65	6.93	28.63	16.02	-1	-1	6.93	11.9796	11.034	
+k6_N10_40nm.xml	stereovision0.v	common	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+k6_N10_40nm_diff_switch_for_inc_dec_wires.xml	stereovision0.v	common	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	

From 6ba8eb71c16fe0e0932b9eb18efe53a9174057e0 Mon Sep 17 00:00:00 2001
From: amin1377 <amin1377.mohaghegh@gmail.com>
Date: Wed, 28 Aug 2024 08:22:50 -0400
Subject: [PATCH 11/12] updage strong odin golden result

---
 .../config/golden_results.txt                    |  6 +++---
 .../config/golden_results.txt                    |  2 +-
 .../config/golden_results.txt                    | 16 ++++++++--------
 .../config/golden_results.txt                    |  4 ++--
 4 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
index 0e6dc420714..37bd51c747e 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
@@ -1,4 +1,4 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	5.41	vpr	210.32 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	215372	1	4	28	32	2	10	9	4	4	16	clb	auto	51.6 MiB	0.14	20	27	15	8	4	193.4 MiB	0.03	0.00	2.44626	0	0	2.44626	0.51	0.000583141	0.000535113	0.00311475	0.00261673	8	12	5	72000	72000	5593.62	349.601	2.10	0.0862302	0.0767113	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0109455	0.00960207	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	7.10	vpr	394.45 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	403912	1	4	28	32	2	10	9	4	4	16	clb	auto	51.6 MiB	0.14	20	27	15	8	4	193.6 MiB	0.03	0.00	2.44626	0	0	2.44626	0.51	0.000585834	0.000538181	0.00313704	0.0026163	8	12	5	72000	72000	5593.62	349.601	2.10	0.0854666	0.0759832	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0110022	0.00964644	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	5.33	vpr	210.00 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	215036	1	4	28	32	2	10	9	4	4	16	clb	auto	51.7 MiB	0.14	20	27	15	8	4	193.7 MiB	0.03	0.00	2.44626	0	0	2.44626	0.50	0.000588315	0.000539577	0.00308844	0.0026033	8	12	5	72000	72000	5593.62	349.601	2.09	0.0840539	0.0747826	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0100088	0.0087372	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt
index 64742271fed..728e10cd85e 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt
@@ -1,2 +1,2 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-timing/k6_N10_40nm.xml	clock_set_delay_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+timing/k6_N10_40nm.xml	clock_set_delay_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc	4.81	vpr	207.77 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	2	2	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	212752	2	2	22	24	2	4	6	4	4	16	clb	auto	51.5 MiB	0.10	4	15	2	10	3	192.8 MiB	0.02	0.00	1.297	0	0	1.297	0.49	0.000472548	0.000433891	0.00258794	0.00211333	4	6	2	72000	36000	2827.54	176.721	1.75	0.0226752	0.0196524	644	852	-1	6	2	4	4	138	80	1.297	1.297	0	0	0	0	4025.56	251.598	0.01	0.02	0.16	-1	-1	0.01	0.00604643	0.0051332	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt
index 425790ca8b7..6b6e64d50b7 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt
@@ -1,9 +1,9 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	num_global_nets	num_routed_nets	
-timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
-timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
-timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
-timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
-timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
-timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
-timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
-timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	2.93	vpr	373.06 MiB		0.14	20488	-1	-1	1	0.02	-1	-1	33464	-1	-1	1	2	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	382012	2	1	3	4	1	3	4	3	3	9	-1	auto	49.4 MiB	0.02	4	9	3	5	1	184.5 MiB	0.01	0.00	0.55447	-0.91031	-0.55447	0.55447	0.00	0.000175279	0.000165491	0.000976401	0.000767979	-1	2	4	18000	18000	14049.7	1561.07	0.01	0.00449048	0.00368003	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
+timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	1.28	vpr	188.73 MiB		0.14	20620	-1	-1	1	0.02	-1	-1	33596	-1	-1	1	2	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	193264	2	1	3	4	1	3	4	3	3	9	-1	auto	49.8 MiB	0.02	6	9	3	3	3	184.7 MiB	0.01	0.00	0.48631	-0.91031	-0.48631	0.48631	0.00	0.000179683	0.000169331	0.00104574	0.000777636	-1	4	3	18000	18000	15707.9	1745.32	0.01	0.00434022	0.00346833	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
+timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	37.69	odin	761.83 MiB		14.13	780112	-1	-1	2	1.41	-1	-1	54088	-1	-1	155	5	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	335516	5	156	191	347	1	163	316	15	15	225	clb	auto	72.2 MiB	1.21	22	86316	62090	3287	20939	314.4 MiB	8.27	0.11	1.49664	-15.129	-1.49664	1.49664	0.00	0.00426637	0.00401077	0.352304	0.330517	-1	30	6	3.042e+06	2.79e+06	863192.	3836.41	0.18	0.426089	0.399481	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	154	9	
+timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	37.85	odin	761.64 MiB		14.27	779924	-1	-1	2	1.37	-1	-1	54552	-1	-1	155	5	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	336112	5	156	191	347	1	163	316	15	15	225	clb	auto	71.9 MiB	1.14	25	86316	61881	3554	20881	315.0 MiB	8.35	0.10	1.47767	-14.8876	-1.47767	1.47767	0.00	0.00427632	0.00401248	0.356421	0.332972	-1	53	7	3.042e+06	2.79e+06	892591.	3967.07	0.20	0.438475	0.409721	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	153	10	
+timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	6.72	vpr	218.05 MiB		2.19	38292	-1	-1	1	0.02	-1	-1	33576	-1	-1	1	2	0	0	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	223280	2	1	3	4	1	3	4	3	3	9	-1	auto	76.3 MiB	0.03	4	9	3	5	1	213.1 MiB	0.01	0.00	0.55247	-0.90831	-0.55247	0.55247	0.00	0.000167702	0.000158607	0.000975812	0.00076565	-1	2	3	53894	53894	12370.0	1374.45	0.01	0.00428013	0.00347708	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
+timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	6.85	vpr	218.27 MiB		2.22	38424	-1	-1	1	0.02	-1	-1	33516	-1	-1	1	2	0	0	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	223504	2	1	3	4	1	3	4	3	3	9	-1	auto	76.6 MiB	0.03	6	9	3	3	3	213.5 MiB	0.01	0.00	0.48631	-0.90831	-0.48631	0.48631	0.00	0.000179672	0.000169578	0.00106215	0.000790093	-1	4	2	53894	53894	14028.3	1558.70	0.01	0.00420473	0.00335158	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
+timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	109.92	odin	592.27 MiB		9.47	606488	-1	-1	2	0.15	-1	-1	37288	-1	-1	32	311	15	0	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	550084	311	156	972	1128	1	953	514	28	28	784	memory	auto	194.9 MiB	10.51	8852	208372	78139	120196	10037	513.9 MiB	41.04	0.47	4.11307	-4320.89	-4.11307	4.11307	0.02	0.112519	0.10601	11.801	11.1176	-1	13295	15	4.25198e+07	9.94461e+06	2.96205e+06	3778.13	7.09	15.7544	14.9174	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	15	938	
+timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	111.57	odin	592.08 MiB		9.49	606288	-1	-1	2	0.16	-1	-1	37464	-1	-1	32	311	15	0	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	553212	311	156	972	1128	1	953	514	28	28	784	memory	auto	195.1 MiB	10.54	8741	214546	82147	122429	9970	513.6 MiB	42.17	0.47	4.83167	-3665.82	-4.83167	4.83167	0.02	0.112604	0.106159	12.0753	11.3955	-1	13585	17	4.25198e+07	9.94461e+06	3.02951e+06	3864.17	7.66	16.4333	15.5853	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	14	939	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt
index 6198ac5edde..d69900ba925 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt
@@ -1,3 +1,3 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-k6_N10_40nm.xml	stereovision0.v	common	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
-k6_N10_40nm_diff_switch_for_inc_dec_wires.xml	stereovision0.v	common	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	unknown	unknown	unknown	unknown	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+k6_N10_40nm.xml	stereovision0.v	common	1549.26	odin	1.76 GiB		98.39	1840428	-1	-1	5	90.37	-1	-1	79020	-1	-1	1290	157	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	1154524	157	197	21024	21221	1	7745	1644	38	38	1444	clb	auto	783.3 MiB	148.56	54476	961845	345093	595347	21405	1014.1 MiB	232.41	2.34	4.1021	-15015.6	-4.1021	4.1021	129.29	0.389902	0.346585	40.7176	35.9264	46	66086	26	2.3328e+07	2.322e+07	4.77644e+06	3307.78	532.12	144.943	131.243	120184	989140	-1	64416	19	33992	65277	2895642	459795	3.87727	3.87727	-15760.1	-3.87727	0	0	6.15323e+06	4261.24	6.84	24.73	15.59	-1	-1	6.84	8.80011	8.1096	
+k6_N10_40nm_diff_switch_for_inc_dec_wires.xml	stereovision0.v	common	1603.48	odin	1.76 GiB		98.56	1840680	-1	-1	5	90.29	-1	-1	79364	-1	-1	1297	157	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	1174048	157	197	21024	21221	1	7547	1651	39	39	1521	clb	auto	790.0 MiB	154.00	51912	967297	355681	587577	24039	1018.2 MiB	231.75	2.35	3.27987	-14557.4	-3.27987	3.27987	136.16	0.388182	0.340036	40.7003	35.6992	46	64729	31	7.37824e+07	6.99019e+07	4.88195e+06	3209.70	568.33	147.381	133.258	126630	998267	-1	62442	28	35421	67860	2863040	490307	3.17524	3.17524	-15310.6	-3.17524	0	0	6.27360e+06	4124.65	7.18	29.21	16.28	-1	-1	7.18	12.2122	11.2365	

From fe82c327fb9f125c663de1ee2d8d05f506c78043 Mon Sep 17 00:00:00 2001
From: amin1377 <amin1377.mohaghegh@gmail.com>
Date: Wed, 28 Aug 2024 09:30:11 -0400
Subject: [PATCH 12/12] mannual updating of strong odin results update

---
 .../config/golden_results.txt                    |  6 +++---
 .../config/golden_results.txt                    |  2 +-
 .../config/golden_results.txt                    | 16 ++++++++--------
 .../config/golden_results.txt                    |  4 ++--
 4 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
index 37bd51c747e..39d7267adf0 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt
@@ -1,4 +1,4 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	5.41	vpr	210.32 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	215372	1	4	28	32	2	10	9	4	4	16	clb	auto	51.6 MiB	0.14	20	27	15	8	4	193.4 MiB	0.03	0.00	2.44626	0	0	2.44626	0.51	0.000583141	0.000535113	0.00311475	0.00261673	8	12	5	72000	72000	5593.62	349.601	2.10	0.0862302	0.0767113	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0109455	0.00960207	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	7.10	vpr	394.45 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	403912	1	4	28	32	2	10	9	4	4	16	clb	auto	51.6 MiB	0.14	20	27	15	8	4	193.6 MiB	0.03	0.00	2.44626	0	0	2.44626	0.51	0.000585834	0.000538181	0.00313704	0.0026163	8	12	5	72000	72000	5593.62	349.601	2.10	0.0854666	0.0759832	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0110022	0.00964644	
-timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	5.33	vpr	210.00 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	215036	1	4	28	32	2	10	9	4	4	16	clb	auto	51.7 MiB	0.14	20	27	15	8	4	193.7 MiB	0.03	0.00	2.44626	0	0	2.44626	0.50	0.000588315	0.000539577	0.00308844	0.0026033	8	12	5	72000	72000	5593.62	349.601	2.09	0.0840539	0.0747826	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0100088	0.0087372	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk.sdc	5.41	vpr	210.32 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	64611	1	4	28	32	2	10	9	4	4	16	clb	auto	51.6 MiB	0.14	20	27	15	8	4	193.4 MiB	0.03	0.00	2.44626	0	0	2.44626	0.51	0.000583141	0.000535113	0.00311475	0.00261673	8	12	5	72000	72000	5593.62	349.601	2.10	0.0862302	0.0767113	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0109455	0.00960207	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc	7.10	vpr	394.45 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	80782	1	4	28	32	2	10	9	4	4	16	clb	auto	51.6 MiB	0.14	20	27	15	8	4	193.6 MiB	0.03	0.00	2.44626	0	0	2.44626	0.51	0.000585834	0.000538181	0.00313704	0.0026163	8	12	5	72000	72000	5593.62	349.601	2.10	0.0854666	0.0759832	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0110022	0.00964644	
+timing/k6_N10_40nm.xml	clock_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc	5.33	vpr	210.00 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	4	1	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	64510	1	4	28	32	2	10	9	4	4	16	clb	auto	51.7 MiB	0.14	20	27	15	8	4	193.7 MiB	0.03	0.00	2.44626	0	0	2.44626	0.50	0.000588315	0.000539577	0.00308844	0.0026033	8	12	5	72000	72000	5593.62	349.601	2.09	0.0840539	0.0747826	672	1128	-1	12	6	24	24	485	152	2.38921	2.38921	0	0	0	0	6492.02	405.751	0.01	0.04	0.17	-1	-1	0.01	0.0100088	0.0087372	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt
index 728e10cd85e..67438b42e30 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt
@@ -1,2 +1,2 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-timing/k6_N10_40nm.xml	clock_set_delay_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc	4.81	vpr	207.77 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	2	2	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	212752	2	2	22	24	2	4	6	4	4	16	clb	auto	51.5 MiB	0.10	4	15	2	10	3	192.8 MiB	0.02	0.00	1.297	0	0	1.297	0.49	0.000472548	0.000433891	0.00258794	0.00211333	4	6	2	72000	36000	2827.54	176.721	1.75	0.0226752	0.0196524	644	852	-1	6	2	4	4	138	80	1.297	1.297	0	0	0	0	4025.56	251.598	0.01	0.02	0.16	-1	-1	0.01	0.00604643	0.0051332	
+timing/k6_N10_40nm.xml	clock_set_delay_aliases.blif	common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc	4.81	vpr	207.77 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	2	2	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	63825	2	2	22	24	2	4	6	4	4	16	clb	auto	51.5 MiB	0.10	4	15	2	10	3	192.8 MiB	0.02	0.00	1.297	0	0	1.297	0.49	0.000472548	0.000433891	0.00258794	0.00211333	4	6	2	72000	36000	2827.54	176.721	1.75	0.0226752	0.0196524	644	852	-1	6	2	4	4	138	80	1.297	1.297	0	0	0	0	4025.56	251.598	0.01	0.02	0.16	-1	-1	0.01	0.00604643	0.0051332	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt
index 6b6e64d50b7..ffbc6a68d97 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt
@@ -1,9 +1,9 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	num_global_nets	num_routed_nets	
-timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	2.93	vpr	373.06 MiB		0.14	20488	-1	-1	1	0.02	-1	-1	33464	-1	-1	1	2	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	382012	2	1	3	4	1	3	4	3	3	9	-1	auto	49.4 MiB	0.02	4	9	3	5	1	184.5 MiB	0.01	0.00	0.55447	-0.91031	-0.55447	0.55447	0.00	0.000175279	0.000165491	0.000976401	0.000767979	-1	2	4	18000	18000	14049.7	1561.07	0.01	0.00449048	0.00368003	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
-timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	1.28	vpr	188.73 MiB		0.14	20620	-1	-1	1	0.02	-1	-1	33596	-1	-1	1	2	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	193264	2	1	3	4	1	3	4	3	3	9	-1	auto	49.8 MiB	0.02	6	9	3	3	3	184.7 MiB	0.01	0.00	0.48631	-0.91031	-0.48631	0.48631	0.00	0.000179683	0.000169331	0.00104574	0.000777636	-1	4	3	18000	18000	15707.9	1745.32	0.01	0.00434022	0.00346833	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
-timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	37.69	odin	761.83 MiB		14.13	780112	-1	-1	2	1.41	-1	-1	54088	-1	-1	155	5	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	335516	5	156	191	347	1	163	316	15	15	225	clb	auto	72.2 MiB	1.21	22	86316	62090	3287	20939	314.4 MiB	8.27	0.11	1.49664	-15.129	-1.49664	1.49664	0.00	0.00426637	0.00401077	0.352304	0.330517	-1	30	6	3.042e+06	2.79e+06	863192.	3836.41	0.18	0.426089	0.399481	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	154	9	
-timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	37.85	odin	761.64 MiB		14.27	779924	-1	-1	2	1.37	-1	-1	54552	-1	-1	155	5	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	336112	5	156	191	347	1	163	316	15	15	225	clb	auto	71.9 MiB	1.14	25	86316	61881	3554	20881	315.0 MiB	8.35	0.10	1.47767	-14.8876	-1.47767	1.47767	0.00	0.00427632	0.00401248	0.356421	0.332972	-1	53	7	3.042e+06	2.79e+06	892591.	3967.07	0.20	0.438475	0.409721	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	153	10	
-timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	6.72	vpr	218.05 MiB		2.19	38292	-1	-1	1	0.02	-1	-1	33576	-1	-1	1	2	0	0	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	223280	2	1	3	4	1	3	4	3	3	9	-1	auto	76.3 MiB	0.03	4	9	3	5	1	213.1 MiB	0.01	0.00	0.55247	-0.90831	-0.55247	0.55247	0.00	0.000167702	0.000158607	0.000975812	0.00076565	-1	2	3	53894	53894	12370.0	1374.45	0.01	0.00428013	0.00347708	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
-timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	6.85	vpr	218.27 MiB		2.22	38424	-1	-1	1	0.02	-1	-1	33516	-1	-1	1	2	0	0	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	223504	2	1	3	4	1	3	4	3	3	9	-1	auto	76.6 MiB	0.03	6	9	3	3	3	213.5 MiB	0.01	0.00	0.48631	-0.90831	-0.48631	0.48631	0.00	0.000179672	0.000169578	0.00106215	0.000790093	-1	4	2	53894	53894	14028.3	1558.70	0.01	0.00420473	0.00335158	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
-timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	109.92	odin	592.27 MiB		9.47	606488	-1	-1	2	0.15	-1	-1	37288	-1	-1	32	311	15	0	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	550084	311	156	972	1128	1	953	514	28	28	784	memory	auto	194.9 MiB	10.51	8852	208372	78139	120196	10037	513.9 MiB	41.04	0.47	4.11307	-4320.89	-4.11307	4.11307	0.02	0.112519	0.10601	11.801	11.1176	-1	13295	15	4.25198e+07	9.94461e+06	2.96205e+06	3778.13	7.09	15.7544	14.9174	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	15	938	
-timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	111.57	odin	592.08 MiB		9.49	606288	-1	-1	2	0.16	-1	-1	37464	-1	-1	32	311	15	0	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	553212	311	156	972	1128	1	953	514	28	28	784	memory	auto	195.1 MiB	10.54	8741	214546	82147	122429	9970	513.6 MiB	42.17	0.47	4.83167	-3665.82	-4.83167	4.83167	0.02	0.112604	0.106159	12.0753	11.3955	-1	13585	17	4.25198e+07	9.94461e+06	3.02951e+06	3864.17	7.66	16.4333	15.5853	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	14	939	
+timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	2.93	vpr	373.06 MiB		0.14	20488	-1	-1	1	0.02	-1	-1	33464	-1	-1	1	2	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	76402	2	1	3	4	1	3	4	3	3	9	-1	auto	49.4 MiB	0.02	4	9	3	5	1	184.5 MiB	0.01	0.00	0.55447	-0.91031	-0.55447	0.55447	0.00	0.000175279	0.000165491	0.000976401	0.000767979	-1	2	4	18000	18000	14049.7	1561.07	0.01	0.00449048	0.00368003	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
+timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	1.28	vpr	188.73 MiB		0.14	20620	-1	-1	1	0.02	-1	-1	33596	-1	-1	1	2	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	77305	2	1	3	4	1	3	4	3	3	9	-1	auto	49.8 MiB	0.02	6	9	3	3	3	184.7 MiB	0.01	0.00	0.48631	-0.91031	-0.48631	0.48631	0.00	0.000179683	0.000169331	0.00104574	0.000777636	-1	4	3	18000	18000	15707.9	1745.32	0.01	0.00434022	0.00346833	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
+timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	37.69	odin	761.83 MiB		14.13	780112	-1	-1	2	1.41	-1	-1	54088	-1	-1	155	5	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	67103	5	156	191	347	1	163	316	15	15	225	clb	auto	72.2 MiB	1.21	22	86316	62090	3287	20939	314.4 MiB	0.1654	0.11	1.49664	-15.129	-1.49664	1.49664	0.00	0.00426637	0.00401077	0.352304	0.330517	-1	30	6	3.042e+06	2.79e+06	863192.	3836.41	0.18	0.426089	0.399481	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	154	9	
+timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	37.85	odin	761.64 MiB		14.27	779924	-1	-1	2	1.37	-1	-1	54552	-1	-1	155	5	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	67222	5	156	191	347	1	163	316	15	15	225	clb	auto	71.9 MiB	1.14	25	86316	61881	3554	20881	315.0 MiB	0.167	0.10	1.47767	-14.8876	-1.47767	1.47767	0.00	0.00427632	0.00401248	0.356421	0.332972	-1	53	7	3.042e+06	2.79e+06	892591.	3967.07	0.20	0.438475	0.409721	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	153	10	
+timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	6.72	vpr	218.05 MiB		2.19	38292	-1	-1	1	0.02	-1	-1	33576	-1	-1	1	2	0	0	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	66984	2	1	3	4	1	3	4	3	3	9	-1	auto	76.3 MiB	0.03	4	9	3	5	1	213.1 MiB	0.01	0.00	0.55247	-0.90831	-0.55247	0.55247	0.00	0.000167702	0.000158607	0.000975812	0.00076565	-1	2	3	53894	53894	12370.0	1374.45	0.01	0.00428013	0.00347708	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
+timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	6.85	vpr	218.27 MiB		2.22	38424	-1	-1	1	0.02	-1	-1	33516	-1	-1	1	2	0	0	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	67051	2	1	3	4	1	3	4	3	3	9	-1	auto	76.6 MiB	0.03	6	9	3	3	3	213.5 MiB	0.01	0.00	0.48631	-0.90831	-0.48631	0.48631	0.00	0.000179672	0.000169578	0.00106215	0.000790093	-1	4	2	53894	53894	14028.3	1558.70	0.01	0.00420473	0.00335158	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
+timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_ideal_--route_chan_width_60	109.92	odin	592.27 MiB		9.47	606488	-1	-1	2	0.15	-1	-1	37288	-1	-1	32	311	15	0	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	110016	311	156	972	1128	1	953	514	28	28	784	memory	auto	194.9 MiB	0.5255	8852	208372	78139	120196	10037	513.9 MiB	2.052	0.47	4.11307	-4320.89	-4.11307	4.11307	0.02	0.112519	0.10601	11.801	11.1176	-1	13295	15	4.25198e+07	9.94461e+06	2.96205e+06	3778.13	0.496	15.7544	14.9174	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	15	938	
+timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_-start_odin_--clock_modeling_route_--route_chan_width_60	111.57	odin	592.08 MiB		9.49	606288	-1	-1	2	0.16	-1	-1	37464	-1	-1	32	311	15	0	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	110642	311	156	972	1128	1	953	514	28	28	784	memory	auto	195.1 MiB	0.527	8741	214546	82147	122429	9970	513.6 MiB	2.10	0.47	4.83167	-3665.82	-4.83167	4.83167	0.02	0.112604	0.106159	12.0753	11.3955	-1	13585	17	4.25198e+07	9.94461e+06	3.02951e+06	3864.17	0.536	16.4333	15.5853	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	14	939	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt
index d69900ba925..8e8f487bfc9 100644
--- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt
+++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt
@@ -1,3 +1,3 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-k6_N10_40nm.xml	stereovision0.v	common	1549.26	odin	1.76 GiB		98.39	1840428	-1	-1	5	90.37	-1	-1	79020	-1	-1	1290	157	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	1154524	157	197	21024	21221	1	7745	1644	38	38	1444	clb	auto	783.3 MiB	148.56	54476	961845	345093	595347	21405	1014.1 MiB	232.41	2.34	4.1021	-15015.6	-4.1021	4.1021	129.29	0.389902	0.346585	40.7176	35.9264	46	66086	26	2.3328e+07	2.322e+07	4.77644e+06	3307.78	532.12	144.943	131.243	120184	989140	-1	64416	19	33992	65277	2895642	459795	3.87727	3.87727	-15760.1	-3.87727	0	0	6.15323e+06	4261.24	6.84	24.73	15.59	-1	-1	6.84	8.80011	8.1096	
-k6_N10_40nm_diff_switch_for_inc_dec_wires.xml	stereovision0.v	common	1603.48	odin	1.76 GiB		98.56	1840680	-1	-1	5	90.29	-1	-1	79364	-1	-1	1297	157	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	1174048	157	197	21024	21221	1	7547	1651	39	39	1521	clb	auto	790.0 MiB	154.00	51912	967297	355681	587577	24039	1018.2 MiB	231.75	2.35	3.27987	-14557.4	-3.27987	3.27987	136.16	0.388182	0.340036	40.7003	35.6992	46	64729	31	7.37824e+07	6.99019e+07	4.88195e+06	3209.70	568.33	147.381	133.258	126630	998267	-1	62442	28	35421	67860	2863040	490307	3.17524	3.17524	-15310.6	-3.17524	0	0	6.27360e+06	4124.65	7.18	29.21	16.28	-1	-1	7.18	12.2122	11.2365	
+k6_N10_40nm.xml	stereovision0.v	common	1549.26	odin	1.76 GiB		98.39	1840428	-1	-1	5	90.37	-1	-1	79020	-1	-1	1290	157	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	346357.2	157	197	21024	21221	1	7745	1644	38	38	1444	clb	auto	783.3 MiB	4.4568	54476	961845	345093	595347	21405	1014.1 MiB	13.94	2.34	4.1021	-15015.6	-4.1021	4.1021	129.29	0.389902	0.346585	40.7176	35.9264	46	66086	26	2.3328e+07	2.322e+07	4.77644e+06	3307.78	21.28	144.943	131.243	120184	989140	-1	64416	19	33992	65277	2895642	459795	3.87727	3.87727	-15760.1	-3.87727	0	0	6.15323e+06	4261.24	6.84	1.731	15.59	-1	-1	6.84	8.80011	8.1096	
+k6_N10_40nm_diff_switch_for_inc_dec_wires.xml	stereovision0.v	common	1603.48	odin	1.76 GiB		98.56	1840680	-1	-1	5	90.29	-1	-1	79364	-1	-1	1297	157	-1	-1	success	5941692-dirty	release IPO VTR_ASSERT_LEVEL=3 sanitizers	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-27T23:00:35	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	352214	157	197	21024	21221	1	7547	1651	39	39	1521	clb	auto	790.0 MiB	4.62	51912	967297	355681	587577	24039	1018.2 MiB	13.905	2.35	3.27987	-14557.4	-3.27987	3.27987	136.16	0.388182	0.340036	40.7003	35.6992	46	64729	31	7.37824e+07	6.99019e+07	4.88195e+06	3209.70	22.73	147.381	133.258	126630	998267	-1	62442	28	35421	67860	2863040	490307	3.17524	3.17524	-15310.6	-3.17524	0	0	6.27360e+06	4124.65	7.18	2.33	16.28	-1	-1	7.18	12.2122	11.2365