From 5118c979fef00fbbe8c43a3fedc93f14b2eaced5 Mon Sep 17 00:00:00 2001
From: soheilshahrouz <soheilqs@gmail.com>
Date: Sat, 7 Sep 2024 14:15:17 -0400
Subject: [PATCH] Update NoC link bandwidth in the architecture files used for
 MLP benchmarks

---
 ...atixiv_arch.timing_with_a_embedded_4x4_mesh_noc_topology.xml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/vtr_flow/arch/noc/mesh_noc_topology/mlp_benchmarks.stratixiv_arch.timing_with_a_embedded_4x4_mesh_noc_topology.xml b/vtr_flow/arch/noc/mesh_noc_topology/mlp_benchmarks.stratixiv_arch.timing_with_a_embedded_4x4_mesh_noc_topology.xml
index 456404fe457..80b185e17cb 100644
--- a/vtr_flow/arch/noc/mesh_noc_topology/mlp_benchmarks.stratixiv_arch.timing_with_a_embedded_4x4_mesh_noc_topology.xml
+++ b/vtr_flow/arch/noc/mesh_noc_topology/mlp_benchmarks.stratixiv_arch.timing_with_a_embedded_4x4_mesh_noc_topology.xml
@@ -48449,7 +48449,7 @@
     </switchblock>
   </switchblocklist>
   <!-- The NoC routers were added to the FPGA device in the fixed layout section-->
-  <noc link_bandwidth="1e6" router_latency="1e-9" link_latency="1e-9" noc_router_tile_name="noc_router_adapter">
+  <noc link_bandwidth="1.28e11" router_latency="1e-9" link_latency="1e-9" noc_router_tile_name="noc_router_adapter">
 	  <mesh startx="0" starty="0" endx="340" endy="270" size="4"/>
   </noc>
 </architecture>