From 77537dffbbad24933e239ea79f28cf66adfc8bc0 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 13 Dec 2023 14:45:30 -0500 Subject: [PATCH 1/5] increase ci run-time limit to 420 minutes --- .github/workflows/test.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 2db85a272ef..60529709e40 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -18,6 +18,8 @@ jobs: # Prevents from running on forks where no custom runners are available if: ${{ github.repository_owner == 'verilog-to-routing' }} + timeout-minutes: 420 + container: ubuntu:jammy runs-on: [self-hosted, Linux, X64] From 78d98fe3074de3a5db4b15ba374c1bcd45654f39 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 13 Dec 2023 19:48:52 -0500 Subject: [PATCH 2/5] vpr: test ci test run time --- .../config/config.txt | 70 +++++++++++++++++++ .../config/golden_results.txt | 23 ++++++ 2 files changed, 93 insertions(+) create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat/config/config.txt new file mode 100644 index 00000000000..7d2230b9a64 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat/config/config.txt @@ -0,0 +1,70 @@ +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/titan_blif/titan23/stratixiv + +# Path to directory of SDCs to use +sdc_dir=benchmarks/titan_blif/titan23/stratixiv + +# Path to directory of architectures to use +archs_dir=arch/titan + +# Add circuits to list to sweep +# Note that the circuits are roughly sorted so that some small +# circuits run first (to detect early failures), followed by larger +# circuits (so they do not start last) + +#To keep turn-around time reasonable (approx. <12 hrs) we exclude some +#of the slowest benchmarks + +#Largest benchmarks, excluded +#circuit_list_add=gaussianblur_stratixiv_arch_timing.blif + +#Mixed order of large and small +circuit_list_add=gsm_switch_stratixiv_arch_timing.blif +circuit_list_add=mes_noc_stratixiv_arch_timing.blif +circuit_list_add=dart_stratixiv_arch_timing.blif +circuit_list_add=denoise_stratixiv_arch_timing.blif +circuit_list_add=sparcT2_core_stratixiv_arch_timing.blif +circuit_list_add=cholesky_bdti_stratixiv_arch_timing.blif +circuit_list_add=minres_stratixiv_arch_timing.blif +circuit_list_add=stap_qrd_stratixiv_arch_timing.blif +circuit_list_add=openCV_stratixiv_arch_timing.blif +circuit_list_add=bitonic_mesh_stratixiv_arch_timing.blif +circuit_list_add=segmentation_stratixiv_arch_timing.blif +circuit_list_add=SLAM_spheric_stratixiv_arch_timing.blif +circuit_list_add=des90_stratixiv_arch_timing.blif + +#Small benchmarks +circuit_list_add=neuron_stratixiv_arch_timing.blif +circuit_list_add=sparcT1_core_stratixiv_arch_timing.blif +circuit_list_add=stereo_vision_stratixiv_arch_timing.blif +circuit_list_add=cholesky_mc_stratixiv_arch_timing.blif + +#Large benchmarks +circuit_list_add=directrf_stratixiv_arch_timing.blif +circuit_list_add=bitcoin_miner_stratixiv_arch_timing.blif +circuit_list_add=LU230_stratixiv_arch_timing.blif +circuit_list_add=sparcT1_chip2_stratixiv_arch_timing.blif +circuit_list_add=LU_Network_stratixiv_arch_timing.blif + +# Add architectures to list to sweep +arch_list_add=stratixiv_arch.timing.xml + +# Parse info and how to parse +parse_file=vpr_titan.txt + +# How to parse QoR info +qor_parse_file=qor_vpr_titan.txt +#qor_parse_file=qor_large.txt + +# Pass requirements +pass_requirements_file=pass_requirements_vpr_titan.txt + +#The Titan benchmarks are run at a fixed channel width of 300 to simulate a Stratix IV-like routing architecture +#A large number of routing iterations is set to ensure the router doesn't give up to easily on the larger benchmarks +#To be more run-time comparable to commercial tools like Quartus, we run with higher placer effort (inner_num=2) and lower astar_fac (1.0) +#Set a 24hr timeout so they don't run forever +script_params=-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map -timeout 86400 --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5 --seed 3 --flat_routing on diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat/config/golden_results.txt new file mode 100644 index 00000000000..aeab7fe3797 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat/config/golden_results.txt @@ -0,0 +1,23 @@ +arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes 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1087537 2 848902 34220 225 167 37575 LAB auto 800.01 -1 8905.24 34.75 8.79365 -825548 -7.79365 8.79365 142.25 1.97467 1.46614 404.675 290.131 10667459 2667357 3983335 3475083060 437778344 0 0 6.95909e+08 18520.5 221 13.7216 13.7216 -1.26214e+06 -12.7216 0 0 1592.57 1348.11 1039.94 533.31 +stratixiv_arch.timing.xml LU230_stratixiv_arch_timing.blif common 9437.46 373 16571 116 5040 16 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 18756984 178 195 663067 568001 2 413013 22116 430 319 137170 M9K auto 1116.15 -1 3180.91 12.00 22.8182 -3.14594e+06 -21.8182 7.83218 755.18 1.81031 1.31598 435.301 309.645 17977564 1024239 1942686 3346505372 605233804 0 0 2.57820e+09 18795.7 28 23.0087 9.77401 -5.72551e+06 -22.0087 0 0 898.40 569.516 420.296 2890.28 +stratixiv_arch.timing.xml sparcT1_chip2_stratixiv_arch_timing.blif common 9296.08 1891 33629 3 506 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 12985200 815 1076 764693 760412 1423 416439 36029 280 207 57960 io auto 1621.50 -1 5111.77 25.16 15.6661 -3.78262e+06 -14.6661 4.89313 350.69 1.92453 1.34688 361.645 249.477 7726080 1115595 3632800 1983755594 192008211 0 0 1.07375e+09 18525.7 57 16.6384 5.21373 -4.62443e+06 -15.6384 0 0 491.65 599.9 438.336 1286.93 +stratixiv_arch.timing.xml LU_Network_stratixiv_arch_timing.blif common 6921.18 399 31006 112 1175 0 2 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 11533096 85 185 721554 630079 28 403716 32694 220 163 35860 LAB auto 882.59 -1 4693.25 30.21 8.36036 -542473 -7.36036 5.25441 159.88 2.20091 1.50729 457.23 324.706 5827891 815904 1701202 1435542337 195550222 0 0 6.64235e+08 18523.0 28 9.38323 5.663 -836677 -8.38323 0 0 358.54 645.807 476.117 488.15 From 342ebc09b02533d477bfdf6c3716eb4048da09fa Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 13 Dec 2023 19:50:34 -0500 Subject: [PATCH 3/5] vpr: add ci run-time test to task file --- .../tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt index 085feec3117..992b7145ccb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt @@ -4,3 +4,4 @@ regression_tests/vtr_reg_nightly_test7/titan_other_run_flat #regression_tests/vtr_reg_nightly_test7/verify_router_lookahead_run_flat regression_tests/vtr_reg_nightly_test7/verify_rr_graph_run_flat regression_tests/vtr_reg_nightly_test7/3d_titan_other +regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat From fce3ad74f8b4ba42fc10ce5655f2e73cf9912b4f Mon Sep 17 00:00:00 2001 From: amin1377 Date: Thu, 14 Dec 2023 10:27:42 -0500 Subject: [PATCH 4/5] vpr: add gausian blur to check ci run-time limit --- .../titan_quick_qor_run_flat/config/config.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat/config/config.txt index 7d2230b9a64..c88ac04a187 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat/config/config.txt @@ -20,7 +20,7 @@ archs_dir=arch/titan #of the slowest benchmarks #Largest benchmarks, excluded -#circuit_list_add=gaussianblur_stratixiv_arch_timing.blif +circuit_list_add=gaussianblur_stratixiv_arch_timing.blif #Mixed order of large and small circuit_list_add=gsm_switch_stratixiv_arch_timing.blif From 635edb3d77ea853ad56ef78af77801262cc73109 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Fri, 15 Dec 2023 09:43:43 -0500 Subject: [PATCH 5/5] vpr: remove titan_quick_qor_run_flat --- .../vtr_reg_nightly_test7/task_list.txt | 1 - .../config/config.txt | 70 ------------------- .../config/golden_results.txt | 23 ------ 3 files changed, 94 deletions(-) delete mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat/config/config.txt delete mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt index 992b7145ccb..085feec3117 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt @@ -4,4 +4,3 @@ regression_tests/vtr_reg_nightly_test7/titan_other_run_flat #regression_tests/vtr_reg_nightly_test7/verify_router_lookahead_run_flat regression_tests/vtr_reg_nightly_test7/verify_rr_graph_run_flat regression_tests/vtr_reg_nightly_test7/3d_titan_other -regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat/config/config.txt deleted file mode 100644 index c88ac04a187..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat/config/config.txt +++ /dev/null @@ -1,70 +0,0 @@ -############################################ -# Configuration file for running experiments -############################################## - -# Path to directory of circuits to use -circuits_dir=benchmarks/titan_blif/titan23/stratixiv - -# Path to directory of SDCs to use -sdc_dir=benchmarks/titan_blif/titan23/stratixiv - -# Path to directory of architectures to use -archs_dir=arch/titan - -# Add circuits to list to sweep -# Note that the circuits are roughly sorted so that some small -# circuits run first (to detect early failures), followed by larger -# circuits (so they do not start last) - -#To keep turn-around time reasonable (approx. <12 hrs) we exclude some -#of the slowest benchmarks - -#Largest benchmarks, excluded -circuit_list_add=gaussianblur_stratixiv_arch_timing.blif - -#Mixed order of large and small -circuit_list_add=gsm_switch_stratixiv_arch_timing.blif -circuit_list_add=mes_noc_stratixiv_arch_timing.blif -circuit_list_add=dart_stratixiv_arch_timing.blif -circuit_list_add=denoise_stratixiv_arch_timing.blif -circuit_list_add=sparcT2_core_stratixiv_arch_timing.blif -circuit_list_add=cholesky_bdti_stratixiv_arch_timing.blif -circuit_list_add=minres_stratixiv_arch_timing.blif -circuit_list_add=stap_qrd_stratixiv_arch_timing.blif -circuit_list_add=openCV_stratixiv_arch_timing.blif -circuit_list_add=bitonic_mesh_stratixiv_arch_timing.blif -circuit_list_add=segmentation_stratixiv_arch_timing.blif -circuit_list_add=SLAM_spheric_stratixiv_arch_timing.blif -circuit_list_add=des90_stratixiv_arch_timing.blif - -#Small benchmarks -circuit_list_add=neuron_stratixiv_arch_timing.blif -circuit_list_add=sparcT1_core_stratixiv_arch_timing.blif -circuit_list_add=stereo_vision_stratixiv_arch_timing.blif -circuit_list_add=cholesky_mc_stratixiv_arch_timing.blif - -#Large benchmarks -circuit_list_add=directrf_stratixiv_arch_timing.blif -circuit_list_add=bitcoin_miner_stratixiv_arch_timing.blif -circuit_list_add=LU230_stratixiv_arch_timing.blif -circuit_list_add=sparcT1_chip2_stratixiv_arch_timing.blif -circuit_list_add=LU_Network_stratixiv_arch_timing.blif - -# Add architectures to list to sweep -arch_list_add=stratixiv_arch.timing.xml - -# Parse info and how to parse -parse_file=vpr_titan.txt - -# How to parse QoR info -qor_parse_file=qor_vpr_titan.txt -#qor_parse_file=qor_large.txt - -# Pass requirements -pass_requirements_file=pass_requirements_vpr_titan.txt - -#The Titan benchmarks are run at a fixed channel width of 300 to simulate a Stratix IV-like routing architecture -#A large number of routing iterations is set to ensure the router doesn't give up to easily on the larger benchmarks -#To be more run-time comparable to commercial tools like Quartus, we run with higher placer effort (inner_num=2) and lower astar_fac (1.0) -#Set a 24hr timeout so they don't run forever -script_params=-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map -timeout 86400 --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5 --seed 3 --flat_routing on diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat/config/golden_results.txt deleted file mode 100644 index aeab7fe3797..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_quick_qor_run_flat/config/golden_results.txt +++ /dev/null @@ -1,23 +0,0 @@ -arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time -stratixiv_arch.timing.xml gsm_switch_stratixiv_arch_timing.blif common 3434.92 136 21492 0 1848 0 1 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 9760656 100 36 504627 490068 5 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success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 4184456 23 46 223304 202401 1 131203 7461 138 102 14076 M9K auto 382.91 -1 481.59 3.87 14.1501 -1.40215e+06 -13.1501 11.4821 49.45 0.648403 0.438358 83.6769 57.0805 2176369 347924 886285 611522444 59989634 0 0 2.60164e+08 18482.8 20 15.0213 12.3857 -1.73557e+06 -14.0213 0 0 105.49 121.372 87.8932 164.95 -stratixiv_arch.timing.xml denoise_stratixiv_arch_timing.blif common 3182.96 852 14030 24 359 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 5971932 264 588 355537 274786 1 218574 15265 150 111 16650 LAB auto 395.29 -1 2053.18 13.33 866.716 -868475 -865.716 866.716 59.74 0.852057 0.609981 129.74 93.1704 3069575 1205817 3821898 2625594594 200491408 0 0 3.08278e+08 18515.2 43 857.427 857.427 -1.06208e+06 -856.427 0 0 316.47 210.711 159.272 198.99 -stratixiv_arch.timing.xml sparcT2_core_stratixiv_arch_timing.blif common 3101.89 451 14725 0 260 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 5492144 239 212 302755 300220 1 184812 15436 153 113 17289 LAB auto 720.50 -1 1616.14 9.31 10.5604 -686489 -9.56037 10.5604 74.77 0.872497 0.578117 133.503 89.1183 4841206 557658 2081616 1599598820 153094223 0 0 3.20293e+08 18525.8 65 10.8439 10.8439 -962235 -9.84391 0 0 295.90 247.633 179.457 246.21 -stratixiv_arch.timing.xml cholesky_bdti_stratixiv_arch_timing.blif common 2191.28 162 9680 132 600 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 5522328 94 68 331744 255478 1 156536 10574 169 125 21125 DSP auto 343.39 -1 889.63 8.09 8.69851 -566131 -7.69851 8.69851 109.08 1.20758 0.935206 125.961 91.4 2616338 369944 775061 1257487865 245527477 0 0 3.91827e+08 18548.0 18 9.26921 9.26921 -849140 -8.26921 0 0 268.77 166.745 126.095 403.77 -stratixiv_arch.timing.xml minres_stratixiv_arch_timing.blif common 2432.68 229 7818 78 1459 0 1 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 6819488 129 100 316623 257480 3 183470 9585 225 167 37575 M9K auto 381.42 -1 827.15 4.18 7.64836 -339381 -6.64836 4.9105 204.80 0.749549 0.556493 143.207 105.834 2913341 385664 736714 785197968 116848060 0 0 6.95909e+08 18520.5 15 8.94983 6.16821 -534628 -7.94983 0 0 140.68 181.401 138.116 657.28 -stratixiv_arch.timing.xml stap_qrd_stratixiv_arch_timing.blif common 2706.95 150 15899 75 553 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 4970724 68 82 284051 234177 1 144423 16677 158 117 18486 LAB auto 315.03 -1 1579.67 9.66 6.97142 -374581 -5.97142 6.97142 129.35 0.569765 0.447079 154.643 112.186 2649637 299124 721610 828065173 126669656 0 0 3.42752e+08 18541.2 16 7.53291 7.53291 -591536 -6.53291 0 0 196.94 202.379 151.111 327.94 -stratixiv_arch.timing.xml openCV_stratixiv_arch_timing.blif common 2406.79 208 7145 213 785 40 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 5944316 106 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