[Interchange] Clock routed through general interconnect

[acomodi]

In some designs (e.g. ram-test), the clock net crosses a clock region and gets into the general interconnect.

In the image above, the highlighted signal is the clock net that enters the general interconnect through a CLB site-thru.

Despite this route being accepted, it should not occur unless strictly needed.

I think this situation can be fixed with the following:

• Global clock routing
• Support timing-driven routing

[gatecat]

Global clock routing is the main thing here, and a priority on my side to fix - I'm mainly waiting on chipsalliance/fpga-interchange-schema#31 to get started on a first implementation. Timing-driven routing is unlikely to help much on its own.