diff --git a/project/build.properties b/project/build.properties
index 1e70b0c1..081fdbbc 100644
--- a/project/build.properties
+++ b/project/build.properties
@@ -1 +1 @@
-sbt.version=1.6.0
+sbt.version=1.10.0
diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
index 3a2e4ba4..0832c7ea 100644
--- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
+++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
@@ -217,7 +217,7 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
     toplevel
   }
 
-  val genConfig = SpinalConfig(targetDirectory = netlistDirectory, inlineRom = true).addStandardMemBlackboxing(blackboxByteEnables)
+  val genConfig = SpinalConfig(targetDirectory = netlistDirectory, inlineRom = true, withTimescale = true).addStandardMemBlackboxing(blackboxByteEnables)
   genConfig.generateVerilog(dutGen.setDefinitionName(netlistName))
 
 }
@@ -356,4 +356,4 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{
 //      }
 //    }
   }
-}
\ No newline at end of file
+}