From 55566eb56f54398400df8f29ebf333dfeb6e284e Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 1 Mar 2024 13:34:06 +0100 Subject: [PATCH] sync --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 6 ++++-- .../vexriscv/plugin/DBusCachedPlugin.scala | 18 +++++++++++------- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 651609ad..b33db4ba 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -43,6 +43,7 @@ class LsuTriggerInterface extends Bundle { val size = UInt(2 bits) val dpc = UInt(32 bits) val hit = Bool() + val hitBefore = Bool() } case class ExceptionPortInfo(port : Flow[ExceptionCause],stage : Stage, priority : Int, codeWidth : Int) @@ -959,7 +960,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep val select = RegInit(False) val matcher = Reg(Bits(4 bits)) init(0) csrrw(CSR.TDATA1, read, 19 -> select, 11 -> chain, 0 -> load, 1 -> store, 7 -> matcher) - csrr(CSR.TDATA1, read, 18 -> !execute) + csrr(CSR.TDATA1, read, 18 -> select) //TODO action sizelo select sizehi maskmax } @@ -1027,8 +1028,9 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep } lsuTrigger.hit := slots.map(s => s.tdata2.lsu.hit).orR + lsuTrigger.hitBefore := slots.map(s => s.tdata2.lsu.hit && !s.tdata1.select).orR val lsuBreak = new Area { - val enabled = RegNext(lsuTrigger.hit) + val enabled = RegNext(lsuTrigger.hit && !debugMode) val dpcReg = RegNext(lsuTrigger.dpc) when(enabled) { decode.arbitration.haltByOther := True diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala index fe5d8cdb..de0b550d 100644 --- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala @@ -596,15 +596,19 @@ class DBusCachedPlugin(val config : DataCacheConfig, } } - trigger.valid := arbitration.isFiring && input(MEMORY_ENABLE) - trigger.load := !input(MEMORY_WR) - trigger.store := input(MEMORY_WR) - trigger.size := input(INSTRUCTION)(13 downto 12).asUInt - trigger.virtual := U(input(REGFILE_WRITE_DATA)) - trigger.writeData := input(MEMORY_STORE_DATA_RF) + trigger.valid := arbitration.isValid && input(MEMORY_ENABLE) + trigger.load := !input(MEMORY_WR) + trigger.store := input(MEMORY_WR) + trigger.size := input(INSTRUCTION)(13 downto 12).asUInt + trigger.virtual := U(input(REGFILE_WRITE_DATA)) + trigger.writeData := input(MEMORY_STORE_DATA_RF) trigger.readData := rspFormated trigger.readDataValid := !redoBranch.valid && arbitration.isStuck - trigger.dpc := input(PC) + (if(pipeline.config.withRvc) ((input(IS_RVC)) ? U(2) | U(4)) else 4) + trigger.dpc := input(PC)// + (if(pipeline.config.withRvc) ((input(IS_RVC)) ? U(2) | U(4)) else 4) + when(trigger.hitBefore){ + arbitration.flushIt := True + arbitration.flushNext := True + } // val armed = RegInit(False) setWhen(trigger.hit) // when(arbitration.isValid && armed){ // exceptionBus.valid := True