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microcode.c
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microcode.c
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#include <stdio.h>
#include "microcode.h"
#include "dbg.h"
#define self mb_state* __restrict
#if GBA
#define IR_F_COL (IR & 7)
#define IR_F_ROW ((IR >> 3) & 7)
#else
#define IR_F_COL IR_column
#define IR_F_ROW IR_row
#endif
#define MB_AF_R ((mb->reg.A << 8) | mb->reg.F)
#define MB_AF_W(v) {mb->reg.A = ((v) >> 8) & 0xFF; mb->reg.F = (v) & MB_FLAG_BITS;}
#define MB_CC_CHECK (mbh_cc_check(IR, mb->reg.F))
#define USE_MIC struct mb_mi_cache* __restrict mic = &mb->micache;
#define USE_MI struct mi_dispatch* __restrict mi = mb->mi;
#pragma region Microcode I/O
#pragma region Resolve uncached region + fabric interface
#if CONFIG_ENABLE_LRU
// Resolve an aligned(!) pointer to a ROM bank,
// based on an input address and current banking settings.
// addr < 0x8000
//TODO: get rid of this
PGB_FUNC static inline const r8* __restrict mch_resolve_mic_bank_internal(const self mb, word r_addr)
{
USE_MI;
const r8* __restrict ret = mi->dispatch_ROM_Bank(mi->userdata, r_addr << MICACHE_R_BITS, mi->BANK_ROM);
return ret;
}
#endif
// Uncached resolve aligned readable const memory area, based on address
PGB_FUNC ATTR_FORCE_NOINLINE __attribute__((optimize("Os"))) static const r8* __restrict mch_resolve_mic_r_direct_read(const self mb, word r_addr)
{
USE_MI;
const r8* __restrict ret = NULL;
if(r_addr < MICACHE_R_VALUE(0x8000))
{
//TODO: optimize this for LRU
#if CONFIG_ENABLE_LRU
if(mi->ROM != NULL)
#endif
{
if(r_addr < MICACHE_R_VALUE(0x4000))
{
#if CONFIG_USE_FLAT_ROM
ret = &mi->ROM[0];
return &ret[r_addr << MICACHE_R_BITS];
#else
ret = mi->ROM[0];
if(ret != NULL)
return &ret[r_addr << MICACHE_R_BITS];
#endif
}
else
{
#if CONFIG_USE_FLAT_ROM
r_addr &= MICACHE_R_VALUE(0x3FFF);
ret = &mi->ROM[mi->BANK_ROM << 14];
return &ret[r_addr << MICACHE_R_BITS];
#else
ret = mi->ROM[mi->BANK_ROM];
if(ret != NULL)
{
r_addr &= MICACHE_R_VALUE(0x3FFF);
return &ret[r_addr << MICACHE_R_BITS];
}
#endif
}
}
#if CONFIG_ENABLE_LRU
ret = mch_resolve_mic_bank_internal(mb, r_addr);
#endif
return ret;
}
else if(r_addr < MICACHE_R_VALUE(0xA000))
{
const r8* __restrict ptr = &mi->VRAM[mi->BANK_VRAM << 13];
r_addr &= MICACHE_R_VALUE(0x1FFF);
return &(ptr[r_addr << MICACHE_R_BITS]);
}
else if(r_addr < MICACHE_R_VALUE(0xC000))
{
const r8* __restrict ptr = &mi->SRAM[mi->BANK_SRAM << 13];
r_addr &= MICACHE_R_VALUE(0x1FFF);
return &(ptr[r_addr << MICACHE_R_BITS]);
}
else // WRAM only [$C000; $FFFF] for OAMDMA
{
if(!(r_addr & MICACHE_R_VALUE(0x1000)))
{
r_addr &= MICACHE_R_VALUE(0x0FFF);
return &(mi->WRAM[r_addr << MICACHE_R_BITS]);
}
else
{
var bank = mi->BANK_WRAM;
if(!bank)
bank = 1;
r_addr &= MICACHE_R_VALUE(0x0FFF);
return &(mi->WRAM[(bank << 12) + (r_addr << MICACHE_R_BITS)]);
}
}
}
PGB_FUNC ATTR_FORCE_NOINLINE __attribute__((optimize("Os"))) static r8* __restrict mch_resolve_mic_r_direct_write(const self mb, word r_addr)
{
USE_MI;
if(r_addr < MICACHE_R_VALUE(0x8000))
{
// ROM is *Read-Only* Memory, can't write to it normally
return NULL;
}
else if(r_addr < MICACHE_R_VALUE(0xA000))
{
r8* __restrict ptr = &mi->VRAM[mi->BANK_VRAM << 13];
r_addr &= MICACHE_R_VALUE(0x1FFF);
return &(ptr[r_addr << MICACHE_R_BITS]);
}
else if(r_addr < MICACHE_R_VALUE(0xC000))
{
r8* __restrict ptr = &mi->SRAM[mi->BANK_SRAM << 13];
r_addr &= MICACHE_R_VALUE(0x1FFF);
return &(ptr[r_addr << MICACHE_R_BITS]);
}
else // WRAM only [$C000; $FFFF] for OAMDMA
{
if(!(r_addr & MICACHE_R_VALUE(0x1000)))
{
r_addr &= MICACHE_R_VALUE(0x0FFF);
return &(mi->WRAM[r_addr << MICACHE_R_BITS]);
}
else
{
var bank = mi->BANK_WRAM;
if(!bank)
bank = 1;
r_addr &= MICACHE_R_VALUE(0x0FFF);
return &(mi->WRAM[(bank << 12) + (r_addr << MICACHE_R_BITS)]);
}
}
}
#pragma endregion
#pragma region Resolve cached memory region (by address)
/*
All functions in this region: cached memory resolve
- addr < 0xE000
*/
#pragma region Resolve (read)
PGB_FUNC ATTR_FORCE_NOINLINE __attribute__((optimize("Os"))) static const r8* __restrict mch_resolve_mic_read_slow(self mb, word addr)
{
const r8* __restrict ptr;
var r_addr = MICACHE_R_VALUE(addr);
ptr = mch_resolve_mic_r_direct_read(mb, r_addr);
if(COMPILER_LIKELY(ptr != NULL))
{
#if !CONFIG_MIC_CACHE_BYPASS
USE_MIC;
mic->mc_read[r_addr] = ptr;
#endif
return &ptr[addr & MICACHE_R_SEL];
}
return NULL;
}
PGB_FUNC ATTR_HOT ATTR_FORCE_INLINE __attribute__((optimize("O2"))) static inline const r8* __restrict mch_resolve_mic_read(self mb, word addr)
{
#if !CONFIG_MIC_CACHE_BYPASS
var r_addr = MICACHE_R_VALUE(addr);
const r8* __restrict ptr;
ptr = mb->micache.mc_read[r_addr];
if(COMPILER_LIKELY(ptr != NULL))
return &ptr[addr & MICACHE_R_SEL];
#endif
return mch_resolve_mic_read_slow(mb, addr);
}
PGB_FUNC ATTR_FORCE_NOINLINE __attribute__((optimize("Os"))) static word mch_resolve_mic_read_slow_deref(self mb, word addr)
{
return *mch_resolve_mic_read_slow(mb, addr);
}
PGB_FUNC ATTR_HOT ATTR_FORCE_INLINE __attribute__((optimize("O2"))) static inline word mch_resolve_mic_read_deref(self mb, word addr)
{
#if !CONFIG_MIC_CACHE_BYPASS
var r_addr = MICACHE_R_VALUE(addr);
const r8* __restrict ptr;
ptr = mb->micache.mc_read[r_addr];
if(COMPILER_LIKELY(ptr != NULL))
return ptr[addr & MICACHE_R_SEL];
else
#endif
return mch_resolve_mic_read_slow_deref(mb, addr);
}
#pragma endregion
#pragma region Resolve (write)
PGB_FUNC ATTR_FORCE_NOINLINE __attribute__((optimize("Os"))) static void mch_resolve_mic_write_slow_deref(self mb, word addr, word data)
{
USE_MIC;
var r_addr = MICACHE_R_VALUE(addr);
r8* __restrict ptr;
ptr = mch_resolve_mic_r_direct_write(mb, r_addr);
if(COMPILER_LIKELY(ptr != NULL))
{
mic->mc_write[r_addr] = ptr;
ptr[addr & MICACHE_R_SEL] = data;
return;
}
*ptr = data;
}
PGB_FUNC ATTR_HOT __attribute__((optimize("Os"))) static void mch_resolve_write_deref(r8* __restrict ptr, word addr, word data)
{
addr &= MICACHE_R_SEL;
COMPILER_VARIABLE_BARRIER(addr);
ptr[addr] = data;
}
PGB_FUNC ATTR_HOT ATTR_FORCE_NOINLINE __attribute__((optimize("O2"))) static void mch_resolve_mic_write_deref(self mb, word addr, word data)
{
#if !CONFIG_MIC_CACHE_BYPASS
var r_addr = MICACHE_R_VALUE(addr);
r8* __restrict ptr;
ptr = mb->micache.mc_write[r_addr];
COMPILER_VARIABLE_BARRIER(ptr);
if(ptr != NULL)
{
mch_resolve_write_deref(ptr, addr, data); // prevent register allocator spill, as it's slower than a tail call
return;
}
else
#endif
mch_resolve_mic_write_slow_deref(mb, addr, data);
}
#pragma endregion
#pragma region Resolve (execute)
PGB_FUNC ATTR_FORCE_NOINLINE __attribute__((optimize("Os"))) static const r8* __restrict mch_resolve_mic_execute_slow(self mb, word addr)
{
const r8* __restrict ptr;
var r_addr = MICACHE_R_VALUE(addr);
ptr = mch_resolve_mic_r_direct_read(mb, r_addr);
if(COMPILER_LIKELY(ptr != NULL))
{
#if !CONFIG_MIC_CACHE_BYPASS
USE_MIC;
mic->mc_execute[r_addr] = ptr;
#endif
return &ptr[addr & MICACHE_R_SEL];
}
return NULL;
}
PGB_FUNC ATTR_HOT ATTR_FORCE_INLINE __attribute__((optimize("O2"))) static inline const r8* __restrict mch_resolve_mic_execute(self mb, word addr)
{
#if !CONFIG_MIC_CACHE_BYPASS
var r_addr = MICACHE_R_VALUE(addr);
const r8* __restrict ptr;
ptr = mb->micache.mc_execute[r_addr];
if(COMPILER_LIKELY(ptr != NULL))
return &ptr[addr & MICACHE_R_SEL];
#endif
return mch_resolve_mic_execute_slow(mb, addr);
}
PGB_FUNC ATTR_HOT ATTR_FORCE_NOINLINE __attribute__((optimize("Os"))) static const r8* __restrict mch_resolve_mic_execute_noinline(self mb, word addr)
{
return mch_resolve_mic_execute(mb, addr);
}
PGB_FUNC ATTR_FORCE_NOINLINE __attribute__((optimize("Os"))) static word mch_resolve_mic_execute_slow_deref(self mb, word addr)
{
return *mch_resolve_mic_execute_slow(mb, addr);
}
PGB_FUNC ATTR_HOT ATTR_FORCE_INLINE __attribute__((optimize("O2"))) static inline word mch_resolve_mic_execute_deref(self mb, word addr)
{
#if !CONFIG_MIC_CACHE_BYPASS
var r_addr = MICACHE_R_VALUE(addr);
const r8* __restrict ptr;
ptr = mb->micache.mc_execute[r_addr];
if(COMPILER_LIKELY(ptr != NULL))
return ptr[addr & MICACHE_R_SEL];
else
#endif
return mch_resolve_mic_execute_slow_deref(mb, addr);
}
#pragma endregion
#pragma endregion
#pragma region Dispatch special (IO + ROM)
PGB_FUNC static word mch_memory_dispatch_read_fexx_ffxx(const self mb, word addr)
{
if(addr >= 0xFF80) // HRAM + IE
{
var hm = addr & 0xFF;
if(hm != 0xFF)
{
return mb->mi->HRAM[hm - 0x80];
}
else
{
return mb->IE;
}
}
// Handle IO by fabric
return mb->mi->dispatch_IO(mb->mi->userdata, addr, MB_DATA_DONTCARE, MB_TYPE_READ);
}
PGB_FUNC static void mch_memory_dispatch_write_fexx_ffxx(self mb, word addr, word data)
{
if(addr >= 0xFF80) // HRAM + IE
{
var hm = addr & 0xFF;
if(hm != 0xFF)
{
mb->mi->HRAM[hm - 0x80] = data;
}
else
{
mb->IE = data & 0xFF;
}
return;
}
// Handle IO by fabric
mb->mi->dispatch_IO(mb->mi->userdata, addr, data, MB_TYPE_WRITE);
}
PGB_FUNC ATTR_FORCE_NOINLINE static void mch_memory_dispatch_write_ROM(const self mb, word addr, word data)
{
// Write to ROM has special meaning, handle by fabric
mb->mi->dispatch_ROM(mb->mi->userdata, addr, data, MB_TYPE_WRITE);
}
#pragma endregion
#pragma region Dispatch
// Handle read from memory by microcode, including ECHO RAM
PGB_FUNC ATTR_HOT ATTR_FORCE_NOINLINE __attribute__((optimize("Os"))) static word mch_memory_dispatch_read_(self mb, word addr)
{
if(COMPILER_LIKELY(addr < 0xFE00))
return mch_resolve_mic_read_deref(mb, addr);
else
return mch_memory_dispatch_read_fexx_ffxx(mb, addr);
}
#if CONFIG_DBG
PGB_FUNC static word mch_memory_dispatch_read(self, word addr)
{
DBGF("- /RD %04X -> ", addr);
word res = mch_memory_dispatch_read_(mb, addr);
DBGF("%02X\n", res);
return res;
}
#else
#define mch_memory_dispatch_read mch_memory_dispatch_read_
#endif
// Handle write to address from microcode, including ECHO RAM support
PGB_FUNC ATTR_HOT ATTR_FORCE_NOINLINE __attribute__((optimize("Os"))) static void mch_memory_dispatch_write(self mb, word addr, word data)
{
DBGF("- /WR %04X <- %02X\n", addr, data);
if(COMPILER_LIKELY(addr >= 0x8000))
{
if(COMPILER_LIKELY(addr < 0xFE00))
mch_resolve_mic_write_deref(mb, addr, data);
else
mch_memory_dispatch_write_fexx_ffxx(mb, addr, data);
}
else
mch_memory_dispatch_write_ROM(mb, addr, data);
}
// Fetch one byte as part of an instruction
PGB_FUNC ATTR_HOT ATTR_FORCE_INLINE __attribute__((optimize("Os"))) static word mch_memory_fetch_decode_1(self mb, word addr)
{
if(COMPILER_LIKELY(addr < 0xFE00))
return mch_resolve_mic_execute_deref(mb, addr);
else
return mch_memory_dispatch_read_fexx_ffxx(mb, addr);
}
PGB_FUNC ATTR_HOT ATTR_FORCE_NOINLINE static word mch_memory_fetch_decode_1_noinline(self mb, word addr)
{
return mch_memory_fetch_decode_1(mb, addr);
}
PGB_FUNC ATTR_FORCE_NOINLINE __attribute__((optimize("O2"))) static word mch_memory_fetch_decode_2_slow(self mb, word addr)
{
word addr2 = (addr + 1) & 0xFFFF;
word res1 = mch_memory_fetch_decode_1_noinline(mb, addr);
word res2 = mch_memory_fetch_decode_1_noinline(mb, addr2);
var res = res1;
res |= (res2) << 8;
return res;
}
PGB_FUNC ATTR_HOT ATTR_FORCE_NOINLINE __attribute__((optimize("O2"))) static word mch_resolve_mic_execute_deref_2_HRAM(self mb, word addr)
{
addr = (addr - 0x80) & 0xFF;
const volatile r8* __restrict ptr = &mb->mi->HRAM[addr];
var nres = ptr[0];
nres |= ptr[1] << 8;
return nres;
}
PGB_FUNC ATTR_HOT ATTR_FORCE_NOINLINE __attribute__((optimize("O2"))) static word mch_resolve_mic_execute_deref_2(self mb, word addr)
{
// This has to be volatile, otherwise
// an LDRH is emitted, which is no cool, as
// the pointer will very likely be not aligned.
// This sadly wastes precious CPU cycles,
// but it's necessary to avoid unaligned data abort.
const volatile r8* __restrict ptr = mch_resolve_mic_execute(mb, addr);
word nres = ptr[0];
nres |= ptr[1] << 8;
return nres;
}
// Fetch two bytes as part of an instruction
PGB_FUNC ATTR_HOT ATTR_FORCE_NOINLINE __attribute__((optimize("Os"))) static word mch_memory_fetch_decode_2(self mb, word addr)
{
#if !CONFIG_MIC_CACHE_BYPASS
if(COMPILER_LIKELY(addr < 0xFE00)) // yeah, this is an off-by-one error, and I don't care
{
//word r1 = MICACHE_R_VALUE(addr);
//word r2 = MICACHE_R_VALUE(addr + 1);
//if(COMPILER_LIKELY(r1 == r2))
word tmp = ~addr;
COMPILER_VARIABLE_BARRIER(tmp);
tmp &= MICACHE_R_SEL;
COMPILER_VARIABLE_BARRIER(tmp);
if(COMPILER_LIKELY(tmp)) // same as above commented code
{
return mch_resolve_mic_execute_deref_2(mb, addr);
}
}
else if(addr >= 0xFF80) // This is off by 2, but let's be honest, if this triggers, we're already lost
{
return mch_resolve_mic_execute_deref_2_HRAM(mb, addr);
}
#endif
return mch_memory_fetch_decode_2_slow(mb, addr);
}
// Fetch one byte from PC, incrementing it as well
PGB_FUNC ATTR_HOT static word mch_memory_fetch_PC(self mb)
{
word addr = mb->PC;
mb->PC = (addr + 1) & 0xFFFF;
var res = mch_memory_fetch_decode_1(mb, addr);
DBGF("- /M1 %04X <> %02X\n", addr, res);
return res;
}
PGB_FUNC ATTR_HOT static word mch_memory_fetch_PC_op_1(self mb)
{
word addr = mb->PC;
mb->PC = (addr + 1) & 0xFFFF;
var res = mch_memory_fetch_decode_1(mb, addr);
DBGF("- /O1 %04X <> %02X\n", addr, res);
return res;
}
// Fetch two bytes from PC, incrementing it both times as well
PGB_FUNC ATTR_HOT static word mch_memory_fetch_PC_op_2(self mb)
{
word addr = mb->PC;
mb->PC = (addr + 2) & 0xFFFF;
word resp = mch_memory_fetch_decode_2(mb, addr);
DBGF("- /O2 %04X <> %04X\n", addr, resp);
return resp;
}
#pragma endregion
#pragma endregion
#pragma region Flag mode control
PGB_FUNC static inline void mbh_fr_set_r8_add(self mb, word left, word right)
{
mb->FR1 = left;
mb->FR2 = right;
mb->FMC_MODE = MB_FMC_MODE_ADD_r8;
}
PGB_FUNC static inline void mbh_fr_set_r8_adc(self mb, word left, word right)
{
mb->FR1 = left;
mb->FR2 = right;
mb->FMC_MODE = MB_FMC_MODE_ADC_r8;
}
PGB_FUNC static inline void mbh_fr_set_r8_sub(self mb, word left, word right)
{
mb->FR1 = left;
mb->FR2 = right;
mb->FMC_MODE = MB_FMC_MODE_SUB_r8;
}
PGB_FUNC static inline void mbh_fr_set_r8_sbc(self mb, word left, word right)
{
mb->FR1 = left;
mb->FR2 = right;
mb->FMC_MODE = MB_FMC_MODE_SBC_r8;
}
PGB_FUNC static inline void mbh_fr_set_r16_add(self mb, word left, word right)
{
mb->FR1 = left;
mb->FR2 = right;
mb->FMC_MODE = MB_FMC_MODE_ADD_r16;
}
PGB_FUNC static inline void mbh_fr_set_r16_add_r8(self mb, word left, word right)
{
mb->FR1 = left;
mb->FR2 = right;
mb->FMC_MODE = MB_FMC_MODE_ADD_r16_r8;
}
PGB_FUNC word mbh_fr_get(self mb, word Fin)
{
if(mb->FMC_MODE == MB_FMC_MODE_NONE)
return Fin;
var n1 = mb->FR1;
var n2 = mb->FR2;
Fin &= ~MB_FLAG_H; //TODO: why clear HC here? explain.
switch(mb->FMC_MODE & 0xF)
{
default:
return Fin;
case MB_FMC_MODE_ADD_r16_r8:
{
//if(((n1 & 0xF00) + (n2 & 0xF00)) > 0xFFF)
if(((n1 & 0xF) + (n2 & 0xF)) > 0xF) // ???
Fin |= MB_FLAG_H;
break;
}
case MB_FMC_MODE_ADD_r16:
{
if(((n1 & 0xFFF) + (n2 & 0xFFF)) > 0xFFF)
Fin |= MB_FLAG_H;
break;
}
case MB_FMC_MODE_ADD_r8:
{
if(((n1 & 0xF) + (n2 & 0xF)) > 0xF)
Fin |= MB_FLAG_H;
break;
}
case MB_FMC_MODE_ADC_r8:
{
if(((n1 & 0xF) + (n2 & 0xF) + 1) > 0xF)
Fin |= MB_FLAG_H;
break;
}
case MB_FMC_MODE_SUB_r8:
{
if((n1 & 0xF) < (n2 & 0xF))
Fin |= MB_FLAG_H;
break;
}
case MB_FMC_MODE_SBC_r8:
{
if((n1 & 0xF) < ((n2 & 0xF) + 1))
Fin |= MB_FLAG_H;
break;
}
}
mb->FMC_MODE = MB_FMC_MODE_NONE;
return Fin;
}
PGB_FUNC static inline wbool mbh_cc_check_0(word F)
{
return ~F & MB_FLAG_Z; // NZ
}
PGB_FUNC static inline wbool mbh_cc_check_1(word F)
{
return F & MB_FLAG_Z; // Z
}
PGB_FUNC static inline wbool mbh_cc_check_2(word F)
{
return ~F & MB_FLAG_C; // NC
}
PGB_FUNC static inline wbool mbh_cc_check_3(word F)
{
return F & MB_FLAG_C; // C
}
PGB_FUNC static wbool mbh_cc_check(word IR, word F)
{
register word IR_r = (IR >> 3) & 3;
if(IR_r == MB_CC_NZ)
return mbh_cc_check_0(F); // NZ
else if(IR_r == MB_CC_Z)
return mbh_cc_check_1(F); // Z
else if(IR_r == MB_CC_NC)
return mbh_cc_check_2(F); // NC
else if(IR_r == MB_CC_C)
return mbh_cc_check_3(F); // C
__builtin_unreachable();
}
#pragma endregion
#pragma region disasm (unfinished)
#if CONFIG_DBG
static const char* str_r8[8] = {"B", "C", "D", "E", "H", "L", "[HL]", "A"};
static const char* str_aluop[8] = {"ADD", "ADC", "SUB", "SBC", "AND", "XOR", "ORR", "CMP"};
void mb_disasm(const struct mb_state* __restrict mb)
{
var IR = mb->IR.low;
switch(IR >> 6)
{
case 1:
printf("LD %s, %s", str_r8[(IR >> 3) & 7], str_r8[IR & 7]);
break;
case 2:
printf("%s A, %s", str_aluop[(IR >> 3) & 7], str_r8[IR & 7]);
break;
}
puts("");
}
static const char* str_cbop[4] = {0, "BIT", "SET", "RES"};
static const char* str_cbop0[8] = {"ROL", "ROR", "RCL", "RCR", "LSL", "ASR", "SWAP", "LSR"};
void mb_disasm_CB(const struct mb_state* __restrict mb, word CBIR)
{
var IR = CBIR;
if(IR >> 6)
{
printf("%s %s.%u", str_cbop[(IR >> 6) & 3], str_r8[IR & 7], (IR >> 3) & 7);
}
else
{
printf("%s %s", str_cbop0[(IR >> 3) & 7], str_r8[IR & 7]);
}
puts("");
}
#endif
#pragma endregion
PGB_FUNC ATTR_HOT word mb_exec(self mb)
{
register var IR = mb->IR.low;
r16* __restrict p_reg16_ptr;
// Instruction column left to right
var IR_column = IR & 7;
// Instruction row top to bottom
var IR_row = (IR >> 3) & 7;
// Cycle count
var ncycles = 0;
// Index of source or read-only register
var i_src;
// Index of destination or read-modify-write register index
var i_dst;
// Data for 8bit registers
var data_reg;
// Data for 16bit registers
var data_wide;
// Contains flags where necessary
var data_flags;
// Contains result data to be written back eventually
var data_result;
if(mb->IME) // Interrupts are enabled
{
var F = mbh_irq_get_pending(mb);
if(F) // Handle IREQ if there is any
{
++ncycles; // IDU decrement PC penalty cycle
data_wide = (mb->PC - 1) & 0xFFFF;
var i = 0;
for(;;)
{
if(F & (1 << i))
{
mb->PC = 0x40 | (i << 3);
break;
}
++i;
}
mb->IME = 0;
mb->IME_ASK = 0;
mb->IF &= ~(1 << i);
#if CONFIG_DBG
DBGF("IRQ #%u\n", i);
#endif
goto generic_push;
}
}
else if(mb->IME_ASK) // IME was asked to be turned on
{
mb->IME = 1;
mb->IME_ASK = 0;
}
#if CONFIG_DBG
if(_IS_DBG)
{
DBGF("Instruction %02X (%01o:%01o:%01o) ", IR, IR >> 6, IR & 7, (IR >> 3) & 7);
mb_disasm(mb);
}
#endif
// BROKEN, DO NOT USE YET
#if 0
switch(IR)
{
case 0x00: goto instr_00;
case 0x10: goto instr_10;
case 0x08: goto instr_08;
case 0x18: goto instr_18;
case 0x20: if(mbh_cc_check_0(mb->reg.F)) goto generic_jr; else goto instr_JNR_cc_e8_fail;
case 0x28: if(mbh_cc_check_1(mb->reg.F)) goto generic_jr; else goto instr_JNR_cc_e8_fail;
case 0x30: if(mbh_cc_check_2(mb->reg.F)) goto generic_jr; else goto instr_JNR_cc_e8_fail;
case 0x38: if(mbh_cc_check_3(mb->reg.F)) goto generic_jr; else goto instr_JNR_cc_e8_fail;
case 0x01:
p_reg16_ptr = &mb->reg.raw16[0];
goto instr_0x1_0;
case 0x11:
p_reg16_ptr = &mb->reg.raw16[1];
goto instr_0x1_0;
case 0x21:
p_reg16_ptr = &mb->reg.raw16[2];
goto instr_0x1_0;
case 0x31:
p_reg16_ptr = &mb->SP;
goto instr_0x1_0;
case 0x09:
p_reg16_ptr = &mb->reg.raw16[0];
goto instr_0x1_1;
case 0x19:
p_reg16_ptr = &mb->reg.raw16[1];
goto instr_0x1_1;
case 0x29:
p_reg16_ptr = &mb->reg.raw16[2];
goto instr_0x1_1;
case 0x39:
p_reg16_ptr = &mb->SP;
goto instr_0x1_1;
case 0x02:
case 0x12:
case 0x22:
case 0x32:
case 0x0A:
case 0x1A:
case 0x2A:
case 0x3A:
goto instr_0x2;
case 0x03:
case 0x13:
case 0x23:
case 0x33:
case 0x0B:
case 0x1B:
case 0x2B:
case 0x3B:
goto instr_0x3;
case 0x04:
case 0x14:
case 0x24:
case 0x34:
case 0x05:
case 0x15:
case 0x25:
case 0x35:
case 0x0C:
case 0x1C:
case 0x2C:
case 0x3C:
case 0x0D:
case 0x1D:
case 0x2D:
case 0x3D:
goto instr_0x45;
case 0x06:
case 0x16:
case 0x26:
case 0x36:
case 0x0E:
case 0x1E:
case 0x2E:
case 0x3E:
goto instr_0x6;
case 0x07: goto instr_007;
case 0x0F: goto instr_017;
case 0x17: goto instr_027;
case 0x1F: goto instr_037;
case 0x27: goto instr_047;
case 0x2F: goto instr_057;
case 0x37: goto instr_067;
case 0x3F: goto instr_077;
case 0x76: goto instr_0x76;
case 0x40:case 0x41:case 0x42:case 0x43:case 0x44:case 0x45:case 0x46:case 0x47:
case 0x48:case 0x49:case 0x4A:case 0x4B:case 0x4C:case 0x4D:case 0x4E:case 0x4F:
case 0x50:case 0x51:case 0x52:case 0x53:case 0x54:case 0x55:case 0x56:case 0x57:
case 0x58:case 0x59:case 0x5A:case 0x5B:case 0x5C:case 0x5D:case 0x5E:case 0x5F:
case 0x60:case 0x61:case 0x62:case 0x63:case 0x64:case 0x65:case 0x66:case 0x67:
case 0x68:case 0x69:case 0x6A:case 0x6B:case 0x6C:case 0x6D:case 0x6E:case 0x6F:
case 0x70:case 0x71:case 0x72:case 0x73:case 0x74:case 0x75: case 0x77:
case 0x78:case 0x79:case 0x7A:case 0x7B:case 0x7C:case 0x7D:case 0x7E:case 0x7F:
goto instr_MOV;
case 0x80:case 0x81:case 0x82:case 0x83:case 0x84:case 0x85:case 0x86:case 0x87:
case 0x88:case 0x89:case 0x8A:case 0x8B:case 0x8C:case 0x8D:case 0x8E:case 0x8F:
case 0x90:case 0x91:case 0x92:case 0x93:case 0x94:case 0x95:case 0x96:case 0x97:
case 0x98:case 0x99:case 0x9A:case 0x9B:case 0x9C:case 0x9D:case 0x9E:case 0x9F:
case 0xA0:case 0xA1:case 0xA2:case 0xA3:case 0xA4:case 0xA5:case 0xA6:case 0xA7:
case 0xA8:case 0xA9:case 0xAA:case 0xAB:case 0xAC:case 0xAD:case 0xAE:case 0xAF:
case 0xB0:case 0xB1:case 0xB2:case 0xB3:case 0xB4:case 0xB5:case 0xB6:case 0xB7:
case 0xB8:case 0xB9:case 0xBA:case 0xBB:case 0xBC:case 0xBD:case 0xBE:case 0xBF:
goto instr_ALU;
case 0xC0:
case 0xD0:
case 0xC8:
case 0xD8:
goto instr_RET_cc; // could be MB_CC_CHECK optimized, but the extra cycle is too much work to count
case 0xE0:
data_wide = 0xFF00 | mch_memory_fetch_PC_op_1(mb);
goto instr_340;
case 0xF0:
data_wide = 0xFF00 | mch_memory_fetch_PC_op_1(mb);
goto instr_360;
case 0xE8:
case 0xF8:
goto instr_weird_r16_r8;
case 0xC9: goto instr_311;
case 0xD9: goto instr_331;
case 0xE9: goto instr_351;
case 0xF9: goto instr_371;
case 0xC1:
case 0xD1:
case 0xE1:
case 0xF1:
goto instr_POP_r16;
case 0xEA:
data_wide = mch_memory_fetch_PC_op_2(mb);
goto instr_352;
case 0xFA:
data_wide = mch_memory_fetch_PC_op_2(mb);
goto instr_372;
case 0xE2:
data_wide = 0xFF00 | mb->reg.C;
goto instr_342;
case 0xF2:
data_wide = 0xFF00 | mb->reg.C;
goto instr_362;
case 0xC2: if(mbh_cc_check_0(mb->reg.F)) goto generic_jp_abs; else goto instr_JP_cc_n16_fail;
case 0xD2: if(mbh_cc_check_1(mb->reg.F)) goto generic_jp_abs; else goto instr_JP_cc_n16_fail;
case 0xCA: if(mbh_cc_check_2(mb->reg.F)) goto generic_jp_abs; else goto instr_JP_cc_n16_fail;