diff --git a/.gitlab-ci/bare-metal/poe-off b/.gitlab-ci/bare-metal/poe-off index 3332a7b0f3d..64517204f40 100755 --- a/.gitlab-ci/bare-metal/poe-off +++ b/.gitlab-ci/bare-metal/poe-off @@ -10,7 +10,7 @@ if [ -z "$BM_POE_ADDRESS" ]; then exit 1 fi -SNMP_KEY="SNMPv2-SMI::mib-2.105.1.1.1.3.1.$((48 + BM_POE_INTERFACE))" +SNMP_KEY="SNMPv2-SMI::mib-2.105.1.1.1.3.1.$((${BM_POE_BASE:-0} + BM_POE_INTERFACE))" SNMP_OFF="i 2" flock /var/run/poe.lock -c "snmpset -v2c -r 3 -t 30 -cmesaci $BM_POE_ADDRESS $SNMP_KEY $SNMP_OFF" diff --git a/.gitlab-ci/bare-metal/poe-on b/.gitlab-ci/bare-metal/poe-on index de41fc9b819..c5fde69791d 100755 --- a/.gitlab-ci/bare-metal/poe-on +++ b/.gitlab-ci/bare-metal/poe-on @@ -10,7 +10,7 @@ if [ -z "$BM_POE_ADDRESS" ]; then exit 1 fi -SNMP_KEY="SNMPv2-SMI::mib-2.105.1.1.1.3.1.$((48 + BM_POE_INTERFACE))" +SNMP_KEY="SNMPv2-SMI::mib-2.105.1.1.1.3.1.$((${BM_POE_BASE:-0} + BM_POE_INTERFACE))" SNMP_ON="i 1" SNMP_OFF="i 2" diff --git a/.pick_status.json b/.pick_status.json index afeda95ec6e..8a2660c6c46 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -1,4 +1,11714 @@ [ + { + "sha": "6f713a764fb412567caaabd9ae574822e79da383", + "description": "rusticl/event: fix deadlock when calling clGetEventProfilingInfo inside callbacks", + "nominated": true, + "nomination_type": 0, + "resolution": 1, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "14ec84da172b40932e70693237f57da8cff47272", + "description": "zink+nvk/ci: add flakes seen in latest nightly run", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "679639625785d0f743cdd03802052b71e9576305", + "description": "radv: Optimize memcpy in write_image_descriptor", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "75849bd4288e8758ace159bd5c3624ebca9fcbbc", + "description": "radv/ci: document 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}, + { + "sha": "a2218002addc7e60e66ba87e7a8c7fd49a81121a", + "description": "docs: update calendar for 24.0.7", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "bd725681e4225a04ca51cfaa895aa2396498baa5", + "description": "docs: add release notes for 24.0.7", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "c225f89d346e5c94b8b30334b1609d1b3b845e84", + "description": "anv: skip gfx push constants alloc optimization on gfx9/11", + "nominated": false, + "nomination_type": 1, + "resolution": 4, + "main_sha": null, + "because_sha": "62d96a65464317326cdc2686aa34eb30f8c21952", + "notes": null + }, + { + "sha": "065b3b04d2411f91cd34c7fec90e17157fd1d81e", + "description": "freedreno/ir3: Skip DAG validation on release builds", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "a3e5c156647aa9d72a3d37e0a3227b440ad8adef", + "description": "tu: Fix a6xx lineWidthGranularity", + "nominated": false, + "nomination_type": 1, + "resolution": 4, + "main_sha": null, + "because_sha": "48da361eb7b355f6ce79983d661dd0422e278967", + "notes": null + }, + { + "sha": "5c7f5362c025657b73eb440615a6af708d17904f", + "description": "tu: Add missing error path cleanup", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, + { + "sha": "9f72e22230e6385f17c93dc68c1f95d751deb484", + "description": "broadcom/compiler: remove unused parameters in vpm read", + "nominated": false, + "nomination_type": 3, + "resolution": 4, + "main_sha": null, + "because_sha": null, + "notes": null + }, { "sha": "b8e79d2769b4a4aed7e2103cf0405acc5bdadb86", "description": "mr-label-maker: fix yaml syntax", diff --git a/VERSION b/VERSION index 934c1d66356..b57d498036e 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -24.0.7 +24.0.9 diff --git a/docs/relnotes.rst b/docs/relnotes.rst index 89d38e2cf23..1238954e1c3 100644 --- a/docs/relnotes.rst +++ b/docs/relnotes.rst @@ -3,6 +3,8 @@ Release Notes The release notes summarize what's new or changed in each Mesa release. +- :doc:`24.0.9 release notes ` +- :doc:`24.0.8 release notes ` - :doc:`24.0.7 release notes ` - :doc:`24.0.6 release notes ` - :doc:`24.0.5 release notes ` @@ -415,6 +417,8 @@ The release notes summarize what's new or changed in each Mesa release. :maxdepth: 1 :hidden: + 24.0.9 + 24.0.8 24.0.7 24.0.6 24.0.5 diff --git a/docs/relnotes/24.0.8.rst b/docs/relnotes/24.0.8.rst new file mode 100644 index 00000000000..a90b0e7a6e5 --- /dev/null +++ b/docs/relnotes/24.0.8.rst @@ -0,0 +1,155 @@ +Mesa 24.0.8 Release Notes / 2024-05-22 +====================================== + +Mesa 24.0.8 is a bug fix release which fixes bugs found since the 24.0.7 release. + +Mesa 24.0.8 implements the OpenGL 4.6 API, but the version reported by +glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) / +glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used. +Some drivers don't support all the features required in OpenGL 4.6. OpenGL +4.6 is **only** available if requested at context creation. +Compatibility contexts may report a lower version depending on each driver. + +Mesa 24.0.8 implements the Vulkan 1.3 API, but the version reported by +the apiVersion property of the VkPhysicalDeviceProperties struct +depends on the particular driver being used. + +SHA256 checksum +--------------- + +:: + + d1ed86a266d5b7b8c136ae587ef5618ed1a9837a43440f3713622bf0123bf5c1 mesa-24.0.8.tar.xz + + +New features +------------ + +- None + + +Bug fixes +--------- + +- [24.1-rc4] fatal error: intel/dev/intel_wa.h: No such file or directory +- vcn: rewinding attached video in Totem cause [mmhub] page fault +- When using amd gpu deinterlace, tv bt709 properties mapping to 2 chroma +- VCN decoding freezes the whole system +- [RDNA2 [AV1] [VAAPI] hw decoding glitches in Thorium 123.0.6312.133 after https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28960 +- WSI: Support VK_IMAGE_ASPECT_MEMORY_PLANE_i_BIT_EXT for DRM Modifiers in Vulkan +- radv: Enshrouded GPU hang on RX 6800 +- NVK Zink: Wrong color in Unigine Valley benchmark +- [anv] FINISHME: support YUV colorspace with DRM format modifiers +- 24.0.6: build fails + + +Changes +------- + +Antoine Coutant (1): + +- drisw: fix build without dri3 + +Bas Nieuwenhuizen (1): + +- radv: Use zerovram for Enshrouded. + +David Heidelberg (2): + +- freedreno/ci: move the disabled jobs from include to the main file +- winsys/i915: depends on intel_wa.h + +David Rosca (6): + +- frontends/va: Only increment slice offset after first slice parameters +- radeonsi: Update buffer for other planes in si_alloc_resource +- frontends/va: Store slice types for H264 decode +- radeonsi/vcn: Ensure DPB has as many buffers as references +- radeonsi/vcn: Allow duplicate buffers in DPB +- radeonsi/vcn: Ensure at least one reference for H264 P/B frames + +Eric Engestrom (5): + +- docs: add sha256sum for 24.0.7 +- .pick_status.json: Update to 18c53157318d6c8e572062f6bb768dfb621a55fd +- .pick_status.json: Update to e154f90aa9e71cc98375866c3ab24c4e08e66cb7 +- .pick_status.json: Mark ae8fbe220ae67ffdce662c26bc4a634d475c0389 as denominated +- .pick_status.json: Update to a31996ce5a6b7eb3b324b71eb9e9c45173953c50 + +Faith Ekstrand (6): + +- nvk: Re-emit sample locations when rasterization samples changes +- nvk/meta: Restore set_sizes[0] +- nouveau/winsys: Take a reference to BOs found in the cache +- drm-uapi: Sync nouveau_drm.h +- nouveau/winsys: Add back nouveau_ws_bo_new_tiled() +- vulkan/wsi: Bind memory planes, not YCbCr planes. + +Friedrich Vock (2): + +- aco/tests: Insert p_logical_start/end in reduce_temp tests +- aco/spill: Insert p_start_linear_vgpr right after p_logical_end + +Georg Lehmann (1): + +- zink: use bitcasts instead of pack/unpack double opcodes + +José Expósito (1): + +- meson: Update proc_macro2 meson.build patch + +Karol Herbst (5): + +- rusticl/event: use Weak refs for dependencies +- Revert "rusticl/event: use Weak refs for dependencies" +- event: break long dependency chains on drop +- rusticl/mesa/context: flush context before destruction +- nir/lower_cl_images: set binding also for samplers + +Konstantin Seurer (3): + +- radv: Fix radv_shader_arena_block list corruption +- radv: Remove arenas from capture_replay_arena_vas +- radv: Zero initialize capture replay group handles + +Lionel Landwerlin (3): + +- anv: fix ycbcr plane indexing with indirect descriptors +- anv: fix push constant subgroup_id location +- nir/divergence: add missing load_printf_buffer_address + +Marek Olšák (1): + +- util: shift the mask in BITSET_TEST_RANGE_INSIDE_WORD to be relative to b + +Mike Blumenkrantz (8): + +- egl/x11: disable dri3 with LIBGL_KOPPER_DRI2=1 as expected +- zink: add a batch ref for committed sparse resources +- u_blitter: stop leaking saved blitter states on no-op blits +- frontends/dri: only release pipe when screen init fails +- frontends/dri: always init opencl_func_mutex in InitScreen hooks +- zink: clean up semaphore arrays on batch state destroy +- nir/lower_aaline: fix for scalarized outputs +- nir/linking: fix nir_assign_io_var_locations for scalarized dual blend + +Patrick Lerda (2): + +- clover: fix memory leak related to optimize +- r600: fix vertex state update clover regression + +Rhys Perry (1): + +- aco/waitcnt: fix DS/VMEM ordered writes when mixed + +Romain Naour (1): + +- glxext: don't try zink if not enabled in mesa + +Yiwei Zhang (5): + +- turnip: msm: clean up iova on error path +- turnip: msm: fix racy gem close for re-imported dma-buf +- turnip: virtio: fix error path in virtio_bo_init +- turnip: virtio: fix iova leak upon found already imported dmabuf +- turnip: virtio: fix racy gem close for re-imported dma-buf diff --git a/docs/relnotes/24.0.9.rst b/docs/relnotes/24.0.9.rst new file mode 100644 index 00000000000..55dfd512ad9 --- /dev/null +++ b/docs/relnotes/24.0.9.rst @@ -0,0 +1,155 @@ +Mesa 24.0.9 Release Notes / 2024-06-06 +====================================== + +Mesa 24.0.9 is a bug fix release which fixes bugs found since the 24.0.8 release. + +Mesa 24.0.9 implements the OpenGL 4.6 API, but the version reported by +glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) / +glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used. +Some drivers don't support all the features required in OpenGL 4.6. OpenGL +4.6 is **only** available if requested at context creation. +Compatibility contexts may report a lower version depending on each driver. + +Mesa 24.0.9 implements the Vulkan 1.3 API, but the version reported by +the apiVersion property of the VkPhysicalDeviceProperties struct +depends on the particular driver being used. + +SHA256 checksum +--------------- + +:: + + 51aa686ca4060e38711a9e8f60c8f1efaa516baf411946ed7f2c265cd582ca4c mesa-24.0.9.tar.xz + + +New features +------------ + +- None + + +Bug fixes +--------- + +- RustiCL: deadlock when calling clGetProfilingInfo() on callbacks +- dEQP-VK.pipeline.pipeline_library.shader_module_identifier.pipeline_from_id.graphics regression +- anv: unbounded shader cache +- radv: Crash due to nir validation fail in Enshrouded +- radv: Crash due to nir validation fail in Enshrouded +- panforst: T604 issue with using u32 for flat varyings + + +Changes +------- + +Alexandre Marquet (1): + +- pan/mdg: quirk to disable auto32 + +David Heidelberg (2): + +- subprojects: uprev perfetto to v45.0 +- ci/nouveau: move disabled jobs back from include into main gitlab-ci.yml + +David Rosca (1): + +- frontends/va: Fix leak when destroying VAEncCodedBufferType + +Eric Engestrom (11): + +- docs: add sha256sum for 24.0.8 +- .pick_status.json: Update to 18c736bcfc55b8fa309ede02332b9c7a2ca22e78 +- .pick_status.json: Mark 01bac643f6c088f7537edf18f2d4094881c1ecda as denominated +- .pick_status.json: Update to 4b6f7613c0bd161548f1bd45d42b65b4841a278a +- .pick_status.json: Mark eefe34127f8e8ae2ba91a7837b9dfef999dc3f87 as denominated +- .pick_status.json: Update to a1ea0956b46778d0331e4ef60ebd2be057fd0e9f +- .pick_status.json: Mark 410ca6a3e99c5c1c9c91f0f79bf43a35103cbd98 as denominated +- freedreno/a6xx: fix kernel -> compute handling +- panfrost: mark tests as fixed +- panfrost/ci: add missing genxml trigger path +- .pick_status.json: Update to 6f713a764fb412567caaabd9ae574822e79da383 + +Eric R. Smith (4): + +- get_color_read_type: make sure format/type combo is legal for gles +- glsl: test both inputs when sorting varyings for xfb +- panfrost: fix some omissions in valhall flow control +- panfrost: change default rounding mode for samplers + +Friedrich Vock (2): + +- radv: Use max_se instead of num_se where appropriate +- radeonsi: Use max_se instead of num_se where appropriate + +Iago Toral Quiroga (4): + +- broadcom/compiler: make add_node return the node index +- broadcom/compiler: don't assign payload registers to spilling setup temps +- broadcom/compiler: apply payload conflict to spill setup before RA +- v3dv: fix incorrect index buffer size + +Iván Briano (1): + +- anv: check cmd_buffer is on a transfer queue more properly + +Jose Maria Casanova Crespo (8): + +- v3d: fix CLE MMU errors avoiding using last bytes of CL BOs. +- v3dv: fix CLE MMU errors avoiding using last bytes of CL BOs. +- v3d: Increase alignment to 16k on CL BO on RPi5 +- v3dv: Increase alignment to 16k on CL BO on RPi5 +- v3dv: V3D_CL_MAX_INSTR_SIZE bytes in last CL instruction not needed +- v3dv: Emit stencil draw clear if needed for GFXH-1461 +- v3dv: really fix CLE MMU errors on 7.1HW Rpi5 +- v3d: really fix CLE MMU errors on 7.1HW Rpi5 + +Juan A. Suarez Romero (1): + +- ci: define SNMP base interface on runner + +Karol Herbst (5): + +- gallium/vl: stub vl_video_buffer_create_as_resource +- gallium/vl: remove stubs which are defined in mesa_util +- meson: centralize galliumvl_stub handling +- rusticl: link against libgalliumvl_stub +- rusticl/event: fix deadlock when calling clGetEventProfilingInfo inside callbacks + +Kevin Chuang (1): + +- anv: Properly fetch partial results in vkGetQueryPoolResults + +Lionel Landwerlin (5): + +- anv: use weak_ref mode for global pipeline caches +- anv: fix shader identifier handling +- intel/brw: ensure find_live_channel don't access arch register without sync +- anv: fix utrace compute walker timestamp captures +- anv: fix timestamp copies from secondary buffers + +Renato Pereyra (1): + +- anv: Attempt to compile all pipelines even after errors + +Rhys Perry (3): + +- aco: create lcssa phis for continue_or_break loops when necessary +- aco: create lcssa phis for continue_or_break loops when necessary +- radv: malloc graphics pipeline stages + +Samuel Pitoiset (6): + +- radv: allow 3d views with VK_IMAGE_CREATE_2D_VIEW_COMPATIBLE_BIT_EXT +- radv: set image view descriptors as buffer for non-graphics GPU +- radv: mark some formats as unsupported on GFX8/CARRIZO +- radv: only set ALPHA_IS_ON_MSB if the image has DCC on GFX6-9 +- radv: fix setting a custom pitch for CB on GFX10_3+ +- radv: fix flushing DB meta cache on GFX11.5 + +Tapani Pälli (1): + +- anv/android: enable emulated astc for applications + +Yusuf Khan (1): + +- zink/query: begin time elapsed queries even if we arent in a rp diff --git a/include/drm-uapi/nouveau_drm.h b/include/drm-uapi/nouveau_drm.h index 0bade1592f3..dd87f8f3079 100644 --- a/include/drm-uapi/nouveau_drm.h +++ b/include/drm-uapi/nouveau_drm.h @@ -54,11 +54,42 @@ extern "C" { */ #define NOUVEAU_GETPARAM_EXEC_PUSH_MAX 17 +/* + * NOUVEAU_GETPARAM_VRAM_BAR_SIZE - query bar size + * + * Query the VRAM BAR size. + */ +#define NOUVEAU_GETPARAM_VRAM_BAR_SIZE 18 + +/* + * NOUVEAU_GETPARAM_VRAM_USED + * + * Get remaining VRAM size. + */ +#define NOUVEAU_GETPARAM_VRAM_USED 19 + +/* + * NOUVEAU_GETPARAM_HAS_VMA_TILEMODE + * + * Query whether tile mode and PTE kind are accepted with VM allocs or not. + */ +#define NOUVEAU_GETPARAM_HAS_VMA_TILEMODE 20 + struct drm_nouveau_getparam { __u64 param; __u64 value; }; +/* + * Those are used to support selecting the main engine used on Kepler. + * This goes into drm_nouveau_channel_alloc::tt_ctxdma_handle + */ +#define NOUVEAU_FIFO_ENGINE_GR 0x01 +#define NOUVEAU_FIFO_ENGINE_VP 0x02 +#define NOUVEAU_FIFO_ENGINE_PPP 0x04 +#define NOUVEAU_FIFO_ENGINE_BSP 0x08 +#define NOUVEAU_FIFO_ENGINE_CE 0x30 + struct drm_nouveau_channel_alloc { __u32 fb_ctxdma_handle; __u32 tt_ctxdma_handle; @@ -81,6 +112,18 @@ struct drm_nouveau_channel_free { __s32 channel; }; +struct drm_nouveau_notifierobj_alloc { + __u32 channel; + __u32 handle; + __u32 size; + __u32 offset; +}; + +struct drm_nouveau_gpuobj_free { + __s32 channel; + __u32 handle; +}; + #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) @@ -238,34 +281,32 @@ struct drm_nouveau_vm_init { struct drm_nouveau_vm_bind_op { /** * @op: the operation type + * + * Supported values: + * + * %DRM_NOUVEAU_VM_BIND_OP_MAP - Map a GEM object to the GPU's VA + * space. Optionally, the &DRM_NOUVEAU_VM_BIND_SPARSE flag can be + * passed to instruct the kernel to create sparse mappings for the + * given range. + * + * %DRM_NOUVEAU_VM_BIND_OP_UNMAP - Unmap an existing mapping in the + * GPU's VA space. If the region the mapping is located in is a + * sparse region, new sparse mappings are created where the unmapped + * (memory backed) mapping was mapped previously. To remove a sparse + * region the &DRM_NOUVEAU_VM_BIND_SPARSE must be set. */ __u32 op; -/** - * @DRM_NOUVEAU_VM_BIND_OP_MAP: - * - * Map a GEM object to the GPU's VA space. Optionally, the - * &DRM_NOUVEAU_VM_BIND_SPARSE flag can be passed to instruct the kernel to - * create sparse mappings for the given range. - */ #define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0 -/** - * @DRM_NOUVEAU_VM_BIND_OP_UNMAP: - * - * Unmap an existing mapping in the GPU's VA space. If the region the mapping - * is located in is a sparse region, new sparse mappings are created where the - * unmapped (memory backed) mapping was mapped previously. To remove a sparse - * region the &DRM_NOUVEAU_VM_BIND_SPARSE must be set. - */ #define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1 /** * @flags: the flags for a &drm_nouveau_vm_bind_op + * + * Supported values: + * + * %DRM_NOUVEAU_VM_BIND_SPARSE - Indicates that an allocated VA + * space region should be sparse. */ __u32 flags; -/** - * @DRM_NOUVEAU_VM_BIND_SPARSE: - * - * Indicates that an allocated VA space region should be sparse. - */ #define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8) /** * @handle: the handle of the DRM GEM object to map @@ -301,17 +342,17 @@ struct drm_nouveau_vm_bind { __u32 op_count; /** * @flags: the flags for a &drm_nouveau_vm_bind ioctl + * + * Supported values: + * + * %DRM_NOUVEAU_VM_BIND_RUN_ASYNC - Indicates that the given VM_BIND + * operation should be executed asynchronously by the kernel. + * + * If this flag is not supplied the kernel executes the associated + * operations synchronously and doesn't accept any &drm_nouveau_sync + * objects. */ __u32 flags; -/** - * @DRM_NOUVEAU_VM_BIND_RUN_ASYNC: - * - * Indicates that the given VM_BIND operation should be executed asynchronously - * by the kernel. - * - * If this flag is not supplied the kernel executes the associated operations - * synchronously and doesn't accept any &drm_nouveau_sync objects. - */ #define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1 /** * @wait_count: the number of wait &drm_nouveau_syncs diff --git a/src/amd/ci/radv-navi21-aco-flakes.txt b/src/amd/ci/radv-navi21-aco-flakes.txt index 9e2e41634c1..2ff57de65bf 100644 --- a/src/amd/ci/radv-navi21-aco-flakes.txt +++ b/src/amd/ci/radv-navi21-aco-flakes.txt @@ -10,7 +10,4 @@ dEQP-VK.draw.renderpass.multi_draw.mosaic.indexed_mixed.max_draws.stride_extra_1 dEQP-VK.pipeline.*line_stipple_enable dEQP-VK.pipeline.*line_stipple_params -# New CTS flakes in 1.3.6.3 -dEQP-VK.ray_tracing_pipeline.pipeline_library.configurations.(single|multi)threaded_compilation.*_check_(all|capture_replay)_handles - dEQP-VK.query_pool.statistics_query.host_query_reset.geometry_shader_invocations.secondary.32bits_triangle_list_clear_depth diff --git a/src/amd/ci/radv-navi31-aco-flakes.txt b/src/amd/ci/radv-navi31-aco-flakes.txt index d1a8efcf746..e69de29bb2d 100644 --- a/src/amd/ci/radv-navi31-aco-flakes.txt +++ b/src/amd/ci/radv-navi31-aco-flakes.txt @@ -1,5 +0,0 @@ -# New CTS flakes in 1.3.6.3 -dEQP-VK.ray_tracing_pipeline.pipeline_library.configurations.multithreaded_compilation.*_check_all_handles -dEQP-VK.ray_tracing_pipeline.pipeline_library.configurations.multithreaded_compilation.*_check_capture_replay_handles -dEQP-VK.ray_tracing_pipeline.pipeline_library.configurations.singlethreaded_compilation.*_check_all_handles -dEQP-VK.ray_tracing_pipeline.pipeline_library.configurations.singlethreaded_compilation.*_check_capture_replay_handles diff --git a/src/amd/common/ac_shader_util.c b/src/amd/common/ac_shader_util.c index 24e53098843..5b062640634 100644 --- a/src/amd/common/ac_shader_util.c +++ b/src/amd/common/ac_shader_util.c @@ -1001,7 +1001,7 @@ void ac_get_scratch_tmpring_size(const struct radeon_info *info, unsigned max_scratch_waves = info->max_scratch_waves; if (info->gfx_level >= GFX11) - max_scratch_waves /= info->num_se; /* WAVES is per SE */ + max_scratch_waves /= info->max_se; /* WAVES is per SE */ /* TODO: We could decrease WAVES to make the whole buffer fit into the infinity cache. */ *tmpring_size = S_0286E8_WAVES(max_scratch_waves) | diff --git a/src/amd/compiler/aco_insert_waitcnt.cpp b/src/amd/compiler/aco_insert_waitcnt.cpp index 0209f44c377..784d992363c 100644 --- a/src/amd/compiler/aco_insert_waitcnt.cpp +++ b/src/amd/compiler/aco_insert_waitcnt.cpp @@ -428,18 +428,20 @@ check_instr(wait_ctx& ctx, wait_imm& wait, alu_delay_info& delay, Instruction* i if (it == ctx.gpr_map.end()) continue; + wait_imm reg_imm = it->second.imm; + /* Vector Memory reads and writes return in the order they were issued */ uint8_t vmem_type = get_vmem_type(instr); if (vmem_type && ((it->second.events & vm_events) == event_vmem) && it->second.vmem_types == vmem_type) - continue; + reg_imm.vm = wait_imm::unset_counter; /* LDS reads and writes return in the order they were issued. same for GDS */ if (instr->isDS() && (it->second.events & lgkm_events) == (instr->ds().gds ? event_gds : event_lds)) - continue; + reg_imm.lgkm = wait_imm::unset_counter; - wait.combine(it->second.imm); + wait.combine(reg_imm); } } } diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 251baa09813..3203b5ecdee 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -10205,6 +10205,29 @@ visit_block(isel_context* ctx, nir_block* block) ctx->cf_info.nir_to_aco[block->index] = ctx->block->index; } +static bool +all_uses_inside_loop(nir_def* def, nir_block* block_before_loop, nir_block* block_after_loop) +{ + nir_foreach_use_including_if (use, def) { + if (nir_src_is_if(use)) { + nir_block* branch_block = + nir_cf_node_as_block(nir_cf_node_prev(&nir_src_parent_if(use)->cf_node)); + if (branch_block->index <= block_before_loop->index || + branch_block->index >= block_after_loop->index) + return false; + } else { + nir_instr* instr = nir_src_parent_instr(use); + if ((instr->block->index <= block_before_loop->index || + instr->block->index >= block_after_loop->index) && + !(instr->type == nir_instr_type_phi && instr->block == block_after_loop)) { + return false; + } + } + } + + return true; +} + static Operand create_continue_phis(isel_context* ctx, unsigned first, unsigned last, aco_ptr& header_phi, Operand* vals) @@ -10251,6 +10274,65 @@ create_continue_phis(isel_context* ctx, unsigned first, unsigned last, return vals[last - first]; } +Temp +rename_temp(const std::map& renames, Temp tmp) +{ + auto it = renames.find(tmp.id()); + if (it != renames.end()) + return Temp(it->second, tmp.regClass()); + return tmp; +} + +static void +lcssa_workaround(isel_context* ctx, nir_loop* loop) +{ + assert(ctx->block->linear_preds.size() == ctx->block->logical_preds.size() + 1); + + nir_block* block_before_loop = nir_cf_node_as_block(nir_cf_node_prev(&loop->cf_node)); + nir_block* block_after_loop = nir_cf_node_as_block(nir_cf_node_next(&loop->cf_node)); + + std::map renames; + nir_foreach_block_in_cf_node (block, &loop->cf_node) { + nir_foreach_instr (instr, block) { + nir_def* def = nir_instr_def(instr); + if (!def) + continue; + + Temp tmp = get_ssa_temp(ctx, def); + if (!tmp.is_linear() || all_uses_inside_loop(def, block_before_loop, block_after_loop)) + continue; + + Temp new_tmp = ctx->program->allocateTmp(tmp.regClass()); + aco_ptr phi(create_instruction( + aco_opcode::p_linear_phi, Format::PSEUDO, ctx->block->linear_preds.size(), 1)); + for (unsigned i = 0; i < ctx->block->logical_preds.size(); i++) + phi->operands[i] = Operand(new_tmp); + phi->operands.back() = Operand(tmp.regClass()); + phi->definitions[0] = Definition(tmp); + ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi)); + + renames.emplace(tmp.id(), new_tmp.id()); + } + } + + if (renames.empty()) + return; + + for (unsigned i = ctx->block->index - 1; + ctx->program->blocks[i].loop_nest_depth > ctx->block->loop_nest_depth; i--) { + for (aco_ptr& instr : ctx->program->blocks[i].instructions) { + for (Definition& def : instr->definitions) { + if (def.isTemp()) + def.setTemp(rename_temp(renames, def.getTemp())); + } + for (Operand& op : instr->operands) { + if (op.isTemp()) + op.setTemp(rename_temp(renames, op.getTemp())); + } + } + } +} + static void begin_uniform_if_then(isel_context* ctx, if_context* ic, Temp cond); static void begin_uniform_if_else(isel_context* ctx, if_context* ic); static void end_uniform_if(isel_context* ctx, if_context* ic); @@ -10317,6 +10399,10 @@ visit_loop(isel_context* ctx, nir_loop* loop) } end_loop(ctx, &lc); + + /* Create extra LCSSA phis for continue_or_break */ + if (ctx->block->linear_preds.size() > ctx->block->logical_preds.size()) + lcssa_workaround(ctx, loop); } static void diff --git a/src/amd/compiler/aco_reduce_assign.cpp b/src/amd/compiler/aco_reduce_assign.cpp index 55fc525e485..2bc5add45ae 100644 --- a/src/amd/compiler/aco_reduce_assign.cpp +++ b/src/amd/compiler/aco_reduce_assign.cpp @@ -118,11 +118,16 @@ setup_reduce_temp(Program* program) * would insert at the end instead of using this one. */ } else { assert(last_top_level_block_idx < block.index); - /* insert before the branch at last top level block */ + /* insert after p_logical_end of the last top-level block */ std::vector>& instructions = program->blocks[last_top_level_block_idx].instructions; - instructions.insert(std::next(instructions.begin(), instructions.size() - 1), - std::move(create)); + auto insert_point = + std::find_if(instructions.rbegin(), instructions.rend(), + [](const auto& iter) { + return iter->opcode == aco_opcode::p_logical_end; + }) + .base(); + instructions.insert(insert_point, std::move(create)); inserted_at = last_top_level_block_idx; } } @@ -161,8 +166,13 @@ setup_reduce_temp(Program* program) assert(last_top_level_block_idx < block.index); std::vector>& instructions = program->blocks[last_top_level_block_idx].instructions; - instructions.insert(std::next(instructions.begin(), instructions.size() - 1), - std::move(create)); + auto insert_point = + std::find_if(instructions.rbegin(), instructions.rend(), + [](const auto& iter) { + return iter->opcode == aco_opcode::p_logical_end; + }) + .base(); + instructions.insert(insert_point, std::move(create)); vtmp_inserted_at = last_top_level_block_idx; } } diff --git a/src/amd/compiler/aco_spill.cpp b/src/amd/compiler/aco_spill.cpp index 8da3d49202b..47c4f803834 100644 --- a/src/amd/compiler/aco_spill.cpp +++ b/src/amd/compiler/aco_spill.cpp @@ -1845,10 +1845,16 @@ assign_spill_slots(spill_ctx& ctx, unsigned spills_to_vgpr) instructions.emplace_back(std::move(create)); } else { assert(last_top_level_block_idx < block.index); - /* insert before the branch at last top level block */ + /* insert after p_logical_end of the last top-level block */ std::vector>& block_instrs = ctx.program->blocks[last_top_level_block_idx].instructions; - block_instrs.insert(std::prev(block_instrs.end()), std::move(create)); + auto insert_point = + std::find_if(block_instrs.rbegin(), block_instrs.rend(), + [](const auto& iter) { + return iter->opcode == aco_opcode::p_logical_end; + }) + .base(); + block_instrs.insert(insert_point, std::move(create)); } } @@ -1885,10 +1891,16 @@ assign_spill_slots(spill_ctx& ctx, unsigned spills_to_vgpr) instructions.emplace_back(std::move(create)); } else { assert(last_top_level_block_idx < block.index); - /* insert before the branch at last top level block */ + /* insert after p_logical_end of the last top-level block */ std::vector>& block_instrs = ctx.program->blocks[last_top_level_block_idx].instructions; - block_instrs.insert(std::prev(block_instrs.end()), std::move(create)); + auto insert_point = + std::find_if(block_instrs.rbegin(), block_instrs.rend(), + [](const auto& iter) { + return iter->opcode == aco_opcode::p_logical_end; + }) + .base(); + block_instrs.insert(insert_point, std::move(create)); } } diff --git a/src/amd/compiler/tests/test_insert_waitcnt.cpp b/src/amd/compiler/tests/test_insert_waitcnt.cpp index 86d81845173..e17a39be195 100644 --- a/src/amd/compiler/tests/test_insert_waitcnt.cpp +++ b/src/amd/compiler/tests/test_insert_waitcnt.cpp @@ -53,3 +53,71 @@ BEGIN_TEST(insert_waitcnt.ds_ordered_count) finish_waitcnt_test(); END_TEST + +BEGIN_TEST(insert_waitcnt.waw.mixed_vmem_lds.vmem) + if (!setup_cs(NULL, GFX10)) + return; + + Definition def_v4(PhysReg(260), v1); + Operand op_v0(PhysReg(256), v1); + Operand desc0(PhysReg(0), s4); + + //>> BB0 + //! /* logical preds: / linear preds: / kind: top-level, */ + //! v1: %0:v[4] = buffer_load_dword %0:s[0-3], %0:v[0], 0 + bld.mubuf(aco_opcode::buffer_load_dword, def_v4, desc0, op_v0, Operand::zero(), 0, false); + + //>> BB1 + //! /* logical preds: / linear preds: / kind: */ + //! v1: %0:v[4] = ds_read_b32 %0:v[0] + bld.reset(program->create_and_insert_block()); + bld.ds(aco_opcode::ds_read_b32, def_v4, op_v0); + + bld.reset(program->create_and_insert_block()); + program->blocks[2].linear_preds.push_back(0); + program->blocks[2].linear_preds.push_back(1); + program->blocks[2].logical_preds.push_back(0); + program->blocks[2].logical_preds.push_back(1); + + //>> BB2 + //! /* logical preds: BB0, BB1, / linear preds: BB0, BB1, / kind: uniform, */ + //! s_waitcnt lgkmcnt(0) + //! v1: %0:v[4] = buffer_load_dword %0:s[0-3], %0:v[0], 0 + bld.mubuf(aco_opcode::buffer_load_dword, def_v4, desc0, op_v0, Operand::zero(), 0, false); + + finish_waitcnt_test(); +END_TEST + +BEGIN_TEST(insert_waitcnt.waw.mixed_vmem_lds.lds) + if (!setup_cs(NULL, GFX10)) + return; + + Definition def_v4(PhysReg(260), v1); + Operand op_v0(PhysReg(256), v1); + Operand desc0(PhysReg(0), s4); + + //>> BB0 + //! /* logical preds: / linear preds: / kind: top-level, */ + //! v1: %0:v[4] = buffer_load_dword %0:s[0-3], %0:v[0], 0 + bld.mubuf(aco_opcode::buffer_load_dword, def_v4, desc0, op_v0, Operand::zero(), 0, false); + + //>> BB1 + //! /* logical preds: / linear preds: / kind: */ + //! v1: %0:v[4] = ds_read_b32 %0:v[0] + bld.reset(program->create_and_insert_block()); + bld.ds(aco_opcode::ds_read_b32, def_v4, op_v0); + + bld.reset(program->create_and_insert_block()); + program->blocks[2].linear_preds.push_back(0); + program->blocks[2].linear_preds.push_back(1); + program->blocks[2].logical_preds.push_back(0); + program->blocks[2].logical_preds.push_back(1); + + //>> BB2 + //! /* logical preds: BB0, BB1, / linear preds: BB0, BB1, / kind: uniform, */ + //! s_waitcnt vmcnt(0) + //! v1: %0:v[4] = ds_read_b32 %0:v[0] + bld.ds(aco_opcode::ds_read_b32, def_v4, op_v0); + + finish_waitcnt_test(); +END_TEST diff --git a/src/amd/compiler/tests/test_reduce_assign.cpp b/src/amd/compiler/tests/test_reduce_assign.cpp index 7f44e55486f..8aae778bd98 100644 --- a/src/amd/compiler/tests/test_reduce_assign.cpp +++ b/src/amd/compiler/tests/test_reduce_assign.cpp @@ -41,6 +41,11 @@ BEGIN_TEST(setup_reduce_temp.divergent_if_phi) if (!setup_cs("s2 v1", GFX9)) return; + //>> p_logical_start + //>> p_logical_end + bld.pseudo(aco_opcode::p_logical_start); + bld.pseudo(aco_opcode::p_logical_end); + //>> lv1: %lv = p_start_linear_vgpr emit_divergent_if_else( program.get(), bld, Operand(inputs[0]), diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 182323a32e9..5c3b12bb3c1 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -1320,9 +1320,6 @@ radv_DestroyDevice(VkDevice _device, const VkAllocationCallbacks *pAllocator) if (!device) return; - if (device->capture_replay_arena_vas) - _mesa_hash_table_u64_destroy(device->capture_replay_arena_vas); - radv_device_finish_perf_counter_lock_cs(device); if (device->perf_counter_bo) device->ws->buffer_destroy(device->ws, device->perf_counter_bo); @@ -1372,6 +1369,8 @@ radv_DestroyDevice(VkDevice _device, const VkAllocationCallbacks *pAllocator) radv_finish_trace(device); radv_destroy_shader_arenas(device); + if (device->capture_replay_arena_vas) + _mesa_hash_table_u64_destroy(device->capture_replay_arena_vas); radv_sqtt_finish(device); @@ -1778,7 +1777,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff * * We set the pitch in MIP0_WIDTH. */ - if (device->physical_device->rad_info.gfx_level && iview->image->vk.image_type == VK_IMAGE_TYPE_2D && + if (device->physical_device->rad_info.gfx_level >= GFX10_3 && iview->image->vk.image_type == VK_IMAGE_TYPE_2D && iview->image->vk.array_layers == 1 && plane->surface.is_linear) { assert((plane->surface.u.gfx9.surf_pitch * plane->surface.bpe) % 256 == 0); diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c index 4c80501d8d3..d0ebd5dd2f4 100644 --- a/src/amd/vulkan/radv_formats.c +++ b/src/amd/vulkan/radv_formats.c @@ -181,7 +181,8 @@ radv_is_vertex_buffer_format_supported(VkFormat format) } uint32_t -radv_translate_tex_dataformat(VkFormat format, const struct util_format_description *desc, int first_non_void) +radv_translate_tex_dataformat(const struct radv_physical_device *pdev, VkFormat format, + const struct util_format_description *desc, int first_non_void) { bool uniform = true; int i; @@ -311,6 +312,9 @@ radv_translate_tex_dataformat(VkFormat format, const struct util_format_descript uniform = uniform && desc->channel[0].size == desc->channel[i].size; } + if (first_non_void < 0 || first_non_void > 3) + goto out_unknown; + /* Non-uniform formats. */ if (!uniform) { switch (desc->nr_channels) { @@ -320,6 +324,12 @@ radv_translate_tex_dataformat(VkFormat format, const struct util_format_descript } goto out_unknown; case 4: + /* 5551 and 1555 UINT formats fail on Gfx8/Carrizo´. */ + if (pdev->rad_info.family == CHIP_CARRIZO && desc->channel[1].size == 5 && desc->channel[2].size == 5 && + desc->channel[first_non_void].type == UTIL_FORMAT_TYPE_UNSIGNED && + desc->channel[first_non_void].pure_integer) + goto out_unknown; + if (desc->channel[0].size == 5 && desc->channel[1].size == 5 && desc->channel[2].size == 5 && desc->channel[3].size == 1) { return V_008F14_IMG_DATA_FORMAT_1_5_5_5; @@ -340,9 +350,6 @@ radv_translate_tex_dataformat(VkFormat format, const struct util_format_descript goto out_unknown; } - if (first_non_void < 0 || first_non_void > 3) - goto out_unknown; - /* uniform formats */ switch (desc->channel[first_non_void].size) { case 4: @@ -352,6 +359,11 @@ radv_translate_tex_dataformat(VkFormat format, const struct util_format_descript return V_008F14_IMG_DATA_FORMAT_4_4; #endif case 4: + /* 4444 UINT formats fail on Gfx8/Carrizo´. */ + if (pdev->rad_info.family == CHIP_CARRIZO && desc->channel[first_non_void].type == UTIL_FORMAT_TYPE_UNSIGNED && + desc->channel[first_non_void].pure_integer) + goto out_unknown; + return V_008F14_IMG_DATA_FORMAT_4_4_4_4; } break; @@ -461,7 +473,7 @@ radv_translate_tex_numformat(VkFormat format, const struct util_format_descripti } static bool -radv_is_sampler_format_supported(VkFormat format, bool *linear_sampling) +radv_is_sampler_format_supported(const struct radv_physical_device *pdev, VkFormat format, bool *linear_sampling) { const struct util_format_description *desc = vk_format_description(format); uint32_t num_format; @@ -477,7 +489,7 @@ radv_is_sampler_format_supported(VkFormat format, bool *linear_sampling) *linear_sampling = true; else *linear_sampling = false; - return radv_translate_tex_dataformat(format, vk_format_description(format), + return radv_translate_tex_dataformat(pdev, format, vk_format_description(format), vk_format_get_first_non_void_channel(format)) != ~0U; } @@ -499,7 +511,7 @@ radv_is_storage_image_format_supported(const struct radv_physical_device *physic if (vk_format_is_depth_or_stencil(format)) return false; - data_format = radv_translate_tex_dataformat(format, desc, vk_format_get_first_non_void_channel(format)); + data_format = radv_translate_tex_dataformat(physical_device, format, desc, vk_format_get_first_non_void_channel(format)); num_format = radv_translate_tex_numformat(format, desc, vk_format_get_first_non_void_channel(format)); if (data_format == ~0 || num_format == ~0) @@ -736,7 +748,7 @@ radv_physical_device_get_format_properties(struct radv_physical_device *physical } } else { bool linear_sampling; - if (radv_is_sampler_format_supported(format, &linear_sampling)) { + if (radv_is_sampler_format_supported(physical_device, format, &linear_sampling)) { linear |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT | VK_FORMAT_FEATURE_2_BLIT_SRC_BIT; tiled |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT | VK_FORMAT_FEATURE_2_BLIT_SRC_BIT; diff --git a/src/amd/vulkan/radv_image_view.c b/src/amd/vulkan/radv_image_view.c index a8e67016ec8..5ec9a92d0af 100644 --- a/src/amd/vulkan/radv_image_view.c +++ b/src/amd/vulkan/radv_image_view.c @@ -119,6 +119,13 @@ radv_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image * } else va += (uint64_t)base_level_info->offset_256B * 256; + if (!device->physical_device->rad_info.has_image_opcodes) { + /* Set it as a buffer descriptor. */ + state[0] = va; + state[1] |= S_008F04_BASE_ADDRESS_HI(va >> 32); + return; + } + state[0] = va >> 8; if (gfx_level >= GFX9 || base_level_info->mode == RADEON_SURF_MODE_2D) state[0] |= swizzle; @@ -244,6 +251,8 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima uint32_t *fmask_state, VkImageCreateFlags img_create_flags, const struct ac_surf_nbc_view *nbc_view, const VkImageViewSlicedCreateInfoEXT *sliced_3d) { + const bool create_2d_view_of_3d = + (img_create_flags & VK_IMAGE_CREATE_2D_VIEW_COMPATIBLE_BIT_EXT) && view_type == VK_IMAGE_VIEW_TYPE_2D; const struct util_format_description *desc; enum pipe_swizzle swizzle[4]; unsigned img_format; @@ -265,7 +274,7 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima radv_compose_swizzle(desc, mapping, swizzle); - if (img_create_flags & VK_IMAGE_CREATE_2D_VIEW_COMPATIBLE_BIT_EXT) { + if (create_2d_view_of_3d) { assert(image->vk.image_type == VK_IMAGE_TYPE_3D); type = V_008F1C_SQ_RSRC_IMG_3D; } else { @@ -300,7 +309,7 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima state[6] = 0; state[7] = 0; - if (img_create_flags & VK_IMAGE_CREATE_2D_VIEW_COMPATIBLE_BIT_EXT) { + if (create_2d_view_of_3d) { assert(type == V_008F1C_SQ_RSRC_IMG_3D); /* ARRAY_PITCH is only meaningful for 3D images, 0 means SRV, 1 means UAV. @@ -412,6 +421,8 @@ gfx6_make_texture_descriptor(struct radv_device *device, struct radv_image *imag unsigned width, unsigned height, unsigned depth, float min_lod, uint32_t *state, uint32_t *fmask_state, VkImageCreateFlags img_create_flags) { + const bool create_2d_view_of_3d = + (img_create_flags & VK_IMAGE_CREATE_2D_VIEW_COMPATIBLE_BIT_EXT) && view_type == VK_IMAGE_VIEW_TYPE_2D; const struct util_format_description *desc; enum pipe_swizzle swizzle[4]; int first_non_void; @@ -437,7 +448,7 @@ gfx6_make_texture_descriptor(struct radv_device *device, struct radv_image *imag num_format = 0; } - data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void); + data_format = radv_translate_tex_dataformat(device->physical_device, vk_format, desc, first_non_void); if (data_format == ~0) { data_format = 0; } @@ -451,8 +462,7 @@ gfx6_make_texture_descriptor(struct radv_device *device, struct radv_image *imag data_format = V_008F14_IMG_DATA_FORMAT_S8_16; } - if (device->physical_device->rad_info.gfx_level == GFX9 && - img_create_flags & VK_IMAGE_CREATE_2D_VIEW_COMPATIBLE_BIT_EXT) { + if (device->physical_device->rad_info.gfx_level == GFX9 && create_2d_view_of_3d) { assert(image->vk.image_type == VK_IMAGE_TYPE_3D); type = V_008F1C_SQ_RSRC_IMG_3D; } else { @@ -501,7 +511,8 @@ gfx6_make_texture_descriptor(struct radv_device *device, struct radv_image *imag state[4] |= S_008F20_DEPTH(depth - 1); state[5] |= S_008F24_LAST_ARRAY(last_layer); } - if (!(image->planes[0].surface.flags & RADEON_SURF_Z_OR_SBUFFER) && image->planes[0].surface.meta_offset) { + + if (radv_dcc_enabled(image, first_level)) { state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device, vk_format)); } else { if (device->instance->drirc.disable_aniso_single_level) { diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index ba6b167551a..205ec375b1c 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -2597,7 +2597,7 @@ radv_graphics_pipeline_compile(struct radv_graphics_pipeline *pipeline, const Vk unsigned char hash[20]; bool keep_executable_info = radv_pipeline_capture_shaders(device, pipeline->base.create_flags); bool keep_statistic_info = radv_pipeline_capture_shader_stats(device, pipeline->base.create_flags); - struct radv_shader_stage stages[MESA_VULKAN_SHADER_STAGES]; + struct radv_shader_stage *stages = malloc(sizeof(struct radv_shader_stage) * MESA_VULKAN_SHADER_STAGES); const VkPipelineCreationFeedbackCreateInfo *creation_feedback = vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO); VkPipelineCreationFeedback pipeline_feedback = { @@ -2609,6 +2609,9 @@ radv_graphics_pipeline_compile(struct radv_graphics_pipeline *pipeline, const Vk !!(pipeline->base.create_flags & VK_PIPELINE_CREATE_2_RETAIN_LINK_TIME_OPTIMIZATION_INFO_BIT_EXT); struct radv_retained_shaders *retained_shaders = NULL; + if (!stages) + return VK_ERROR_OUT_OF_HOST_MEMORY; + int64_t pipeline_start = os_time_get_nano(); for (unsigned i = 0; i < MESA_VULKAN_SHADER_STAGES; i++) { @@ -2669,8 +2672,10 @@ radv_graphics_pipeline_compile(struct radv_graphics_pipeline *pipeline, const Vk gfx_pipeline_lib->stages = radv_copy_shader_stage_create_info(device, pCreateInfo->stageCount, pCreateInfo->pStages, gfx_pipeline_lib->mem_ctx); - if (!gfx_pipeline_lib->stages) + if (!gfx_pipeline_lib->stages) { + free(stages); return VK_ERROR_OUT_OF_HOST_MEMORY; + } gfx_pipeline_lib->stage_count = pCreateInfo->stageCount; } @@ -2679,8 +2684,10 @@ radv_graphics_pipeline_compile(struct radv_graphics_pipeline *pipeline, const Vk goto done; } - if (pipeline->base.create_flags & VK_PIPELINE_CREATE_2_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_KHR) + if (pipeline->base.create_flags & VK_PIPELINE_CREATE_2_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_KHR) { + free(stages); return VK_PIPELINE_COMPILE_REQUIRED; + } if (retain_shaders) { struct radv_graphics_lib_pipeline *gfx_pipeline_lib = radv_pipeline_to_graphics_lib(&pipeline->base); @@ -2748,6 +2755,7 @@ radv_graphics_pipeline_compile(struct radv_graphics_pipeline *pipeline, const Vk } } + free(stages); return result; } diff --git a/src/amd/vulkan/radv_pipeline_rt.c b/src/amd/vulkan/radv_pipeline_rt.c index fe078b89495..36fce6d53b3 100644 --- a/src/amd/vulkan/radv_pipeline_rt.c +++ b/src/amd/vulkan/radv_pipeline_rt.c @@ -943,8 +943,12 @@ radv_GetRayTracingCaptureReplayShaderGroupHandlesKHR(VkDevice device, VkPipeline uint32_t recursive_shader = rt_pipeline->groups[firstGroup + i].recursive_shader; if (recursive_shader != VK_SHADER_UNUSED_KHR) { struct radv_shader *shader = rt_pipeline->stages[recursive_shader].shader; - if (shader) - data[i].recursive_shader_alloc = radv_serialize_shader_arena_block(shader->alloc); + if (shader) { + data[i].recursive_shader_alloc.offset = shader->alloc->offset; + data[i].recursive_shader_alloc.size = shader->alloc->size; + data[i].recursive_shader_alloc.arena_va = shader->alloc->arena->bo->va; + data[i].recursive_shader_alloc.arena_size = shader->alloc->arena->size; + } } data[i].non_recursive_idx = rt_pipeline->groups[firstGroup + i].handle.any_hit_index; } diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 74f5cbb7cb5..310091406b9 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2354,7 +2354,8 @@ bool radv_is_buffer_format_supported(VkFormat format, bool *scaled); uint32_t radv_colorformat_endian_swap(uint32_t colorformat); unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap); uint32_t radv_translate_dbformat(VkFormat format); -uint32_t radv_translate_tex_dataformat(VkFormat format, const struct util_format_description *desc, int first_non_void); +uint32_t radv_translate_tex_dataformat(const struct radv_physical_device *pdev, VkFormat format, + const struct util_format_description *desc, int first_non_void); uint32_t radv_translate_tex_numformat(VkFormat format, const struct util_format_description *desc, int first_non_void); bool radv_format_pack_clear_color(VkFormat format, uint32_t clear_vals[2], VkClearColorValue *value); bool radv_is_storage_image_format_supported(const struct radv_physical_device *physical_device, VkFormat format); diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c index 129b611a7fb..b143ca13d4d 100644 --- a/src/amd/vulkan/radv_queue.c +++ b/src/amd/vulkan/radv_queue.c @@ -637,7 +637,7 @@ radv_emit_graphics_scratch(struct radv_device *device, struct radeon_cmdbuf *cs, uint64_t va = radv_buffer_get_va(scratch_bo); /* WAVES is per SE for SPI_TMPRING_SIZE. */ - waves /= info->num_se; + waves /= info->max_se; radeon_set_context_reg_seq(cs, R_0286E8_SPI_TMPRING_SIZE, 3); radeon_emit(cs, S_0286E8_WAVES(waves) | S_0286E8_WAVESIZE(DIV_ROUND_UP(size_per_wave, 256))); @@ -675,7 +675,7 @@ radv_emit_compute_scratch(struct radv_device *device, struct radeon_cmdbuf *cs, radeon_emit(cs, scratch_va >> 8); radeon_emit(cs, scratch_va >> 40); - waves /= info->num_se; + waves /= info->max_se; } radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2); diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index e4df3864c5f..09b45ac715a 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -982,6 +982,7 @@ alloc_block_obj(struct radv_device *device) static void free_block_obj(struct radv_device *device, union radv_shader_arena_block *block) { + list_del(&block->pool); list_add(&block->pool, &device->shader_block_obj_pool); } @@ -1267,7 +1268,6 @@ radv_free_shader_memory(struct radv_device *device, union radv_shader_arena_bloc remove_hole(free_list, hole_prev); hole_prev->size += hole->size; - list_del(&hole->list); free_block_obj(device, hole); hole = hole_prev; @@ -1280,7 +1280,6 @@ radv_free_shader_memory(struct radv_device *device, union radv_shader_arena_bloc hole_next->offset -= hole->size; hole_next->size += hole->size; - list_del(&hole->list); free_block_obj(device, hole); hole = hole_next; @@ -1293,6 +1292,18 @@ radv_free_shader_memory(struct radv_device *device, union radv_shader_arena_bloc radv_rmv_log_bo_destroy(device, arena->bo); device->ws->buffer_destroy(device->ws, arena->bo); list_del(&arena->list); + + if (device->capture_replay_arena_vas) { + struct hash_entry *arena_entry = NULL; + hash_table_foreach (device->capture_replay_arena_vas->table, entry) { + if (entry->data == arena) { + arena_entry = entry; + break; + } + } + _mesa_hash_table_remove(device->capture_replay_arena_vas->table, arena_entry); + } + free(arena); } else if (free_list) { add_hole(free_list, hole); @@ -1301,18 +1312,6 @@ radv_free_shader_memory(struct radv_device *device, union radv_shader_arena_bloc mtx_unlock(&device->shader_arena_mutex); } -struct radv_serialized_shader_arena_block -radv_serialize_shader_arena_block(union radv_shader_arena_block *block) -{ - struct radv_serialized_shader_arena_block serialized_block = { - .offset = block->offset, - .size = block->size, - .arena_va = block->arena->bo->va, - .arena_size = block->arena->size, - }; - return serialized_block; -} - union radv_shader_arena_block * radv_replay_shader_arena_block(struct radv_device *device, const struct radv_serialized_shader_arena_block *src, void *ptr) diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index c4ceed01d1d..dbf942e28c3 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -775,8 +775,6 @@ union radv_shader_arena_block *radv_replay_shader_arena_block(struct radv_device const struct radv_serialized_shader_arena_block *src, void *ptr); -struct radv_serialized_shader_arena_block radv_serialize_shader_arena_block(union radv_shader_arena_block *block); - void radv_free_shader_memory(struct radv_device *device, union radv_shader_arena_block *alloc); struct radv_shader *radv_create_trap_handler_shader(struct radv_device *device); diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 294bebef365..2ca766340a6 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -1117,8 +1117,9 @@ gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level *sqtt_flush_bits |= RGP_FLUSH_FLUSH_CB | RGP_FLUSH_INVAL_CB; } + /* GFX11 can't flush DB_META and should use a TS event instead. */ /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_DB_META ? */ - if (gfx_level < GFX11 && (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB)) { + if (gfx_level != GFX11 && (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB)) { /* Flush HTILE. Will wait for idle later. */ radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); diff --git a/src/broadcom/common/v3d_limits.h b/src/broadcom/common/v3d_limits.h index 354c8784914..da3e3b8a834 100644 --- a/src/broadcom/common/v3d_limits.h +++ b/src/broadcom/common/v3d_limits.h @@ -24,8 +24,6 @@ #ifndef V3D_LIMITS_H #define V3D_LIMITS_H -#define V3D_CL_MAX_INSTR_SIZE 25 - /* Number of channels a QPU thread executes in parallel. Also known as * gl_SubGroupSizeARB. */ diff --git a/src/broadcom/compiler/v3d_compiler.h b/src/broadcom/compiler/v3d_compiler.h index 18281e42b12..8ba341bf635 100644 --- a/src/broadcom/compiler/v3d_compiler.h +++ b/src/broadcom/compiler/v3d_compiler.h @@ -603,6 +603,11 @@ struct v3d_ra_node_info { bool is_program_end; bool unused; + /* If this node may have an allocation conflict with a + * payload register. + */ + bool payload_conflict; + /* V3D 7.x */ bool is_ldunif_dst; } *info; diff --git a/src/broadcom/compiler/vir_register_allocate.c b/src/broadcom/compiler/vir_register_allocate.c index 53e84840899..f407eff8b3e 100644 --- a/src/broadcom/compiler/vir_register_allocate.c +++ b/src/broadcom/compiler/vir_register_allocate.c @@ -48,6 +48,13 @@ get_phys_index(const struct v3d_device_info *devinfo) #define CLASS_BITS_ACC (1 << 1) #define CLASS_BITS_R5 (1 << 4) +static inline bool +stage_has_payload(struct v3d_compile *c) +{ + return c->s->info.stage == MESA_SHADER_FRAGMENT || + c->s->info.stage == MESA_SHADER_COMPUTE; +} + static uint8_t get_class_bit_any(const struct v3d_device_info *devinfo) { @@ -372,7 +379,7 @@ ensure_nodes(struct v3d_compile *c) /* Creates the interference node for a new temp. We use this to keep the node * list updated during the spilling process, which generates new temps/nodes. */ -static void +static int add_node(struct v3d_compile *c, uint32_t temp, uint8_t class_bits) { ensure_nodes(c); @@ -387,6 +394,9 @@ add_node(struct v3d_compile *c, uint32_t temp, uint8_t class_bits) c->nodes.info[node].is_ldunif_dst = false; c->nodes.info[node].is_program_end = false; c->nodes.info[node].unused = false; + c->nodes.info[node].payload_conflict = false; + + return node; } /* The spill offset for this thread takes a bit of setup, so do it once at @@ -438,7 +448,9 @@ v3d_setup_spill_base(struct v3d_compile *c) i != c->spill_base.index) { temp_class |= CLASS_BITS_ACC; } - add_node(c, i, temp_class); + int node = add_node(c, i, temp_class); + c->nodes.info[node].payload_conflict = + stage_has_payload(c); } } @@ -940,10 +952,12 @@ v3d_ra_select_rf(struct v3d_ra_select_callback_data *v3d_ra, /* The last 3 instructions in a shader can't use some specific registers * (usually early rf registers, depends on v3d version) so try to * avoid allocating these to registers used by the last instructions - * in the shader. + * in the shader. Do the same for spilling setup instructions that + * may conflict with payload registers. */ const uint32_t safe_rf_start = v3d_ra->devinfo->ver == 42 ? 3 : 4; - if (v3d_ra->nodes->info[node].is_program_end && + if ((v3d_ra->nodes->info[node].is_program_end || + v3d_ra->nodes->info[node].payload_conflict) && v3d_ra->next_phys < safe_rf_start) { v3d_ra->next_phys = safe_rf_start; } @@ -1060,11 +1074,52 @@ tmu_spilling_allowed(struct v3d_compile *c) return c->spills + c->fills < c->max_tmu_spills; } +static bool +reg_is_payload(struct v3d_compile *c, struct qreg reg) +{ + if (reg.file != QFILE_REG) + return false; + + if (c->devinfo->ver >= 71) { + if (c->s->info.stage == MESA_SHADER_FRAGMENT) + return reg.index >= 1 && reg.index <= 3; + if (c->s->info.stage == MESA_SHADER_COMPUTE) + return reg.index == 2 || reg.index == 3; + return false; + } + + assert(c->devinfo->ver == 42); + if (c->s->info.stage == MESA_SHADER_FRAGMENT) + return reg.index <= 2; + if (c->s->info.stage == MESA_SHADER_COMPUTE) + return reg.index == 0 || reg.index == 2; + return false; +} + +static bool +inst_reads_payload(struct v3d_compile *c, struct qinst *inst) +{ + if (inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU) + return false; + + if (reg_is_payload(c, inst->dst)) + return true; + + if (reg_is_payload(c, inst->src[0])) + return true; + + if (vir_get_nsrc(inst) > 1 && reg_is_payload(c, inst->src[1])) + return true; + + return false; +} + static void update_graph_and_reg_classes_for_inst(struct v3d_compile *c, int *acc_nodes, int *implicit_rf_nodes, int last_ldvary_ip, + bool has_payload, struct qinst *inst) { int32_t ip = inst->ip; @@ -1180,6 +1235,33 @@ update_graph_and_reg_classes_for_inst(struct v3d_compile *c, } } + /* Spill setup instructions are the only ones that we emit before + * reading payload registers so we want to flag their temps so we + * don't assign them to payload registers and stomp them before we + * can read them. For the case where we may have emitted spill setup + * before RA (i.e. for scratch), we need to do this now. + */ + if (c->spill_size > 0 && has_payload && inst_reads_payload(c, inst)) { + struct qblock *first_block = vir_entry_block(c); + list_for_each_entry_from_rev(struct qinst, _i, inst->link.prev, + &first_block->instructions, link) { + if (_i->qpu.type != V3D_QPU_INSTR_TYPE_ALU) + continue; + if (_i->dst.file == QFILE_TEMP) { + int node = temp_to_node(c, _i->dst.index); + c->nodes.info[node].payload_conflict = true; + } + if (_i->src[0].file == QFILE_TEMP) { + int node = temp_to_node(c, _i->src[0].index); + c->nodes.info[node].payload_conflict = true; + } + if (vir_get_nsrc(_i) > 1 && _i->src[1].file == QFILE_TEMP) { + int node = temp_to_node(c, _i->src[1].index); + c->nodes.info[node].payload_conflict = true; + } + } + } + if (inst->dst.file == QFILE_TEMP) { /* Only a ldunif gets to write to R5, which only has a * single 32-bit channel of storage. @@ -1354,6 +1436,7 @@ v3d_register_allocate(struct v3d_compile *c) */ int ip = 0; int last_ldvary_ip = -1; + bool has_payload = stage_has_payload(c); vir_for_each_inst_inorder(inst, c) { inst->ip = ip++; @@ -1373,7 +1456,9 @@ v3d_register_allocate(struct v3d_compile *c) update_graph_and_reg_classes_for_inst(c, acc_nodes, implicit_rf_nodes, - last_ldvary_ip, inst); + last_ldvary_ip, + has_payload, + inst); } /* Flag the nodes that are used in the last instructions of the program diff --git a/src/broadcom/vulkan/v3dv_cl.c b/src/broadcom/vulkan/v3dv_cl.c index 851e1388a8d..af4066c7849 100644 --- a/src/broadcom/vulkan/v3dv_cl.c +++ b/src/broadcom/vulkan/v3dv_cl.c @@ -31,6 +31,16 @@ #include "broadcom/common/v3d_macros.h" #include "broadcom/cle/v3dx_pack.h" +/* The Control List Executor (CLE) pre-fetches V3D_CLE_READAHEAD bytes from + * the Control List buffer. The usage of these last bytes should be avoided or + * the CLE would pre-fetch the data after the end of the CL buffer, reporting + * the kernel "MMU error from client CLE". + */ +#define V3D42_CLE_READAHEAD 256u +#define V3D42_CLE_BUFFER_MIN_SIZE 4096u +#define V3D71_CLE_READAHEAD 1024u +#define V3D71_CLE_BUFFER_MIN_SIZE 16384u + void v3dv_cl_init(struct v3dv_job *job, struct v3dv_cl *cl) { @@ -55,14 +65,42 @@ v3dv_cl_destroy(struct v3dv_cl *cl) v3dv_cl_init(NULL, cl); } +enum v3dv_cl_chain_type { + V3D_CL_BO_CHAIN_NONE = 0, + V3D_CL_BO_CHAIN_WITH_BRANCH, + V3D_CL_BO_CHAIN_WITH_RETURN_FROM_SUB_LIST, +}; + static bool -cl_alloc_bo(struct v3dv_cl *cl, uint32_t space, bool use_branch) +cl_alloc_bo(struct v3dv_cl *cl, uint32_t space, enum + v3dv_cl_chain_type chain_type) { + /* The last bytes of a CLE buffer are unusable because of readahead + * prefetch, so we need to take it into account when allocating a new BO + * for the CL. We also reserve space for the BRANCH/RETURN_FROM_SUB_LIST + * packet so we can always emit these last packets to the BO when + * needed. We will need to increase cl->size by the packet length before + * calling cl_submit to use this reserved space. + */ + uint32_t unusable_space = 0; + uint32_t cle_readahead = V3DV_X(cl->job->device, CLE_READAHEAD); + uint32_t cle_buffer_min_size = V3DV_X(cl->job->device, CLE_BUFFER_MIN_SIZE); + switch (chain_type) { + case V3D_CL_BO_CHAIN_WITH_BRANCH: + unusable_space = cle_readahead + cl_packet_length(BRANCH); + break; + case V3D_CL_BO_CHAIN_WITH_RETURN_FROM_SUB_LIST: + unusable_space = cle_readahead + cl_packet_length(RETURN_FROM_SUB_LIST); + break; + case V3D_CL_BO_CHAIN_NONE: + break; + } + /* If we are growing, double the BO allocation size to reduce the number * of allocations with large command buffers. This has a very significant * impact on the number of draw calls per second reported by vkoverhead. */ - space = align(space, 4096); + space = align(space + unusable_space, cle_buffer_min_size); if (cl->bo) space = MAX2(cl->bo->size * 2, space); @@ -83,9 +121,28 @@ cl_alloc_bo(struct v3dv_cl *cl, uint32_t space, bool use_branch) } /* Chain to the new BO from the old one if requested */ - if (use_branch && cl->bo) { - cl_emit(cl, BRANCH, branch) { - branch.address = v3dv_cl_address(bo, 0); + if (cl->bo) { + switch (chain_type) { + case V3D_CL_BO_CHAIN_WITH_BRANCH: + cl->size += cl_packet_length(BRANCH); + assert(cl->size + cle_readahead <= cl->bo->size); + cl_emit(cl, BRANCH, branch) { + branch.address = v3dv_cl_address(bo, 0); + } + break; + case V3D_CL_BO_CHAIN_WITH_RETURN_FROM_SUB_LIST: + /* We do not want to emit branches from secondary command lists, instead, + * we will branch to them when we execute them in a primary using + * 'branch to sub list' commands, expecting each linked secondary to + * end with a 'return from sub list' command. + */ + cl->size += cl_packet_length(RETURN_FROM_SUB_LIST); + assert(cl->size + cle_readahead <= cl->bo->size); + cl_emit(cl, RETURN_FROM_SUB_LIST, ret); + FALLTHROUGH; + case V3D_CL_BO_CHAIN_NONE: + v3dv_job_add_bo_unchecked(cl->job, bo); + break; } } else { v3dv_job_add_bo_unchecked(cl->job, bo); @@ -93,7 +150,11 @@ cl_alloc_bo(struct v3dv_cl *cl, uint32_t space, bool use_branch) cl->bo = bo; cl->base = cl->bo->map; - cl->size = cl->bo->size; + /* Take only into account the usable size of the BO to guarantee that + * we never write in the last bytes of the CL buffer because of the + * readahead of the CLE + */ + cl->size = cl->bo->size - unusable_space; cl->next = cl->base; return true; @@ -109,37 +170,20 @@ v3dv_cl_ensure_space(struct v3dv_cl *cl, uint32_t space, uint32_t alignment) return offset; } - cl_alloc_bo(cl, space, false); + cl_alloc_bo(cl, space, V3D_CL_BO_CHAIN_NONE); + return 0; } void v3dv_cl_ensure_space_with_branch(struct v3dv_cl *cl, uint32_t space) { - /* We do not want to emit branches from secondary command lists, instead, - * we will branch to them when we execute them in a primary using - * 'branch to sub list' commands, expecting each linked secondary to - * end with a 'return from sub list' command. - */ - bool needs_return_from_sub_list = false; - if (cl->job->type == V3DV_JOB_TYPE_GPU_CL_SECONDARY && cl->size > 0) - needs_return_from_sub_list = true; - - /* - * The CLE processor in the simulator tries to read V3D_CL_MAX_INSTR_SIZE - * bytes form the CL for each new instruction. If the last instruction in our - * CL is smaller than that, and there are not at least V3D_CL_MAX_INSTR_SIZE - * bytes until the end of the BO, it will read out of bounds and possibly - * cause a GMP violation interrupt to trigger. Ensure we always have at - * least that many bytes available to read with the last instruction. - */ - space += V3D_CL_MAX_INSTR_SIZE; - if (v3dv_cl_offset(cl) + space <= cl->size) return; - if (needs_return_from_sub_list) - cl_emit(cl, RETURN_FROM_SUB_LIST, ret); + enum v3dv_cl_chain_type chain_type = V3D_CL_BO_CHAIN_WITH_BRANCH; + if (cl->job->type == V3DV_JOB_TYPE_GPU_CL_SECONDARY) + chain_type = V3D_CL_BO_CHAIN_WITH_RETURN_FROM_SUB_LIST; - cl_alloc_bo(cl, space, !needs_return_from_sub_list); + cl_alloc_bo(cl, space, chain_type); } diff --git a/src/broadcom/vulkan/v3dv_cl.h b/src/broadcom/vulkan/v3dv_cl.h index 7e17ac395c4..96721530f77 100644 --- a/src/broadcom/vulkan/v3dv_cl.h +++ b/src/broadcom/vulkan/v3dv_cl.h @@ -182,6 +182,7 @@ void v3dv_cl_ensure_space_with_branch(struct v3dv_cl *cl, uint32_t space); cl_packet_pack(packet)(cl, (uint8_t *)cl_out, &name); \ cl_advance_and_end(cl, cl_packet_length(packet)); \ _loop_terminate = NULL; \ + assert(v3dv_cl_offset(cl) <= (cl)->size); \ })) \ #define cl_emit_with_prepacked(cl, packet, prepacked, name) \ @@ -215,9 +216,10 @@ cl_pack_emit_reloc(struct v3dv_cl *cl, const struct v3dv_cl_reloc *reloc) v3dv_job_add_bo(cl->job, reloc->bo); } -#define cl_emit_prepacked_sized(cl, packet, size) do { \ - memcpy((cl)->next, packet, size); \ - cl_advance(&(cl)->next, size); \ +#define cl_emit_prepacked_sized(cl, packet, psize) do { \ + memcpy((cl)->next, packet, psize); \ + cl_advance(&(cl)->next, psize); \ + assert(v3dv_cl_offset(cl) <= (cl)->size); \ } while (0) #define cl_emit_prepacked(cl, packet) \ diff --git a/src/broadcom/vulkan/v3dv_cmd_buffer.c b/src/broadcom/vulkan/v3dv_cmd_buffer.c index dda20edc157..4b317ff21e7 100644 --- a/src/broadcom/vulkan/v3dv_cmd_buffer.c +++ b/src/broadcom/vulkan/v3dv_cmd_buffer.c @@ -1377,7 +1377,7 @@ cmd_buffer_emit_subpass_clears(struct v3dv_cmd_buffer *cmd_buffer) */ if (cmd_buffer->state.tile_aligned_render_area && !subpass->do_depth_clear_with_draw && - !subpass->do_depth_clear_with_draw) { + !subpass->do_stencil_clear_with_draw) { return; } diff --git a/src/broadcom/vulkan/v3dvx_cmd_buffer.c b/src/broadcom/vulkan/v3dvx_cmd_buffer.c index 011f5c8e101..65b18ae639c 100644 --- a/src/broadcom/vulkan/v3dvx_cmd_buffer.c +++ b/src/broadcom/vulkan/v3dvx_cmd_buffer.c @@ -2596,11 +2596,12 @@ v3dX(cmd_buffer_emit_index_buffer)(struct v3dv_cmd_buffer *cmd_buffer) &job->bcl, cl_packet_length(INDEX_BUFFER_SETUP)); v3dv_return_if_oom(cmd_buffer, NULL); - const uint32_t offset = cmd_buffer->state.index_buffer.offset; + const uint32_t offset = ibuffer->mem_offset + + cmd_buffer->state.index_buffer.offset; + assert(ibuffer->mem->bo->size >= offset); cl_emit(&job->bcl, INDEX_BUFFER_SETUP, ib) { - ib.address = v3dv_cl_address(ibuffer->mem->bo, - ibuffer->mem_offset + offset); - ib.size = ibuffer->mem->bo->size; + ib.address = v3dv_cl_address(ibuffer->mem->bo, offset); + ib.size = ibuffer->mem->bo->size - offset; } } diff --git a/src/compiler/glsl/gl_nir_link_varyings.c b/src/compiler/glsl/gl_nir_link_varyings.c index f13b3751265..6ca198da3f2 100644 --- a/src/compiler/glsl/gl_nir_link_varyings.c +++ b/src/compiler/glsl/gl_nir_link_varyings.c @@ -2320,9 +2320,17 @@ static int varying_matches_xfb_comparator(const void *x_generic, const void *y_generic) { const struct match *x = (const struct match *) x_generic; - - if (x->producer_var != NULL && x->producer_var->data.is_xfb_only) - return varying_matches_match_comparator(x_generic, y_generic); + const struct match *y = (const struct match *) y_generic; + /* if both varying are used by transform feedback, sort them */ + if (x->producer_var != NULL && x->producer_var->data.is_xfb_only) { + if (y->producer_var != NULL && y->producer_var->data.is_xfb_only) + return 0; + /* if x is varying and y is not, put y first */ + return +1; + } else if (y->producer_var != NULL && y->producer_var->data.is_xfb_only) { + /* if y is varying and x is not, leave x first */ + return -1; + } /* FIXME: When the comparator returns 0 it means the elements being * compared are equivalent. However the qsort documentation says: @@ -2345,8 +2353,11 @@ static int varying_matches_not_xfb_comparator(const void *x_generic, const void *y_generic) { const struct match *x = (const struct match *) x_generic; + const struct match *y = (const struct match *) y_generic; - if (x->producer_var != NULL && !x->producer_var->data.is_xfb) + if ( (x->producer_var != NULL && !x->producer_var->data.is_xfb) + && (y->producer_var != NULL && !y->producer_var->data.is_xfb) ) + /* if both are non-xfb, then sort them */ return varying_matches_match_comparator(x_generic, y_generic); /* FIXME: When the comparator returns 0 it means the elements being diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index 51c20baf0fb..216c092d281 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -216,6 +216,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr) case nir_intrinsic_load_rasterization_primitive_amd: case nir_intrinsic_load_global_constant_uniform_block_intel: case nir_intrinsic_cmat_length: + case nir_intrinsic_load_printf_buffer_address: is_divergent = false; break; diff --git a/src/compiler/nir/nir_linking_helpers.c b/src/compiler/nir/nir_linking_helpers.c index 44d632f0a56..f3c85791d54 100644 --- a/src/compiler/nir/nir_linking_helpers.c +++ b/src/compiler/nir/nir_linking_helpers.c @@ -1492,7 +1492,7 @@ nir_assign_io_var_locations(nir_shader *shader, nir_variable_mode mode, unsigned *size, gl_shader_stage stage) { unsigned location = 0; - unsigned assigned_locations[VARYING_SLOT_TESS_MAX]; + unsigned assigned_locations[VARYING_SLOT_TESS_MAX][2]; uint64_t processed_locs[2] = { 0 }; struct exec_list io_vars; @@ -1584,7 +1584,7 @@ nir_assign_io_var_locations(nir_shader *shader, nir_variable_mode mode, if (processed) { /* TODO handle overlapping per-view variables */ assert(!var->data.per_view); - unsigned driver_location = assigned_locations[var->data.location]; + unsigned driver_location = assigned_locations[var->data.location][var->data.index]; var->data.driver_location = driver_location; /* An array may be packed such that is crosses multiple other arrays @@ -1605,7 +1605,7 @@ nir_assign_io_var_locations(nir_shader *shader, nir_variable_mode mode, unsigned num_unallocated_slots = last_slot_location - location; unsigned first_unallocated_slot = var_size - num_unallocated_slots; for (unsigned i = first_unallocated_slot; i < var_size; i++) { - assigned_locations[var->data.location + i] = location; + assigned_locations[var->data.location + i][var->data.index] = location; location++; } } @@ -1613,7 +1613,7 @@ nir_assign_io_var_locations(nir_shader *shader, nir_variable_mode mode, } for (unsigned i = 0; i < var_size; i++) { - assigned_locations[var->data.location + i] = location + i; + assigned_locations[var->data.location + i][var->data.index] = location + i; } var->data.driver_location = location; diff --git a/src/compiler/nir/nir_lower_cl_images.c b/src/compiler/nir/nir_lower_cl_images.c index c172128b650..13063593aad 100644 --- a/src/compiler/nir/nir_lower_cl_images.c +++ b/src/compiler/nir/nir_lower_cl_images.c @@ -161,6 +161,7 @@ nir_lower_cl_images(nir_shader *shader, bool lower_image_derefs, bool lower_samp assert(var->data.location > last_loc); last_loc = var->data.location; var->data.driver_location = num_samplers++; + var->data.binding = var->data.driver_location; } else { /* CL shouldn't have any sampled images */ assert(!glsl_type_is_sampler(var->type)); diff --git a/src/egl/drivers/dri2/platform_x11.c b/src/egl/drivers/dri2/platform_x11.c index 6af987ed7ad..ecee10f47bf 100644 --- a/src/egl/drivers/dri2/platform_x11.c +++ b/src/egl/drivers/dri2/platform_x11.c @@ -1518,7 +1518,8 @@ dri2_initialize_x11_swrast(_EGLDisplay *disp) */ dri2_dpy->driver_name = strdup(disp->Options.Zink ? "zink" : "swrast"); if (disp->Options.Zink && - !debug_get_bool_option("LIBGL_DRI3_DISABLE", false)) + !debug_get_bool_option("LIBGL_DRI3_DISABLE", false) && + !debug_get_bool_option("LIBGL_KOPPER_DRI2", false)) dri3_x11_connect(dri2_dpy); if (!dri2_load_driver_swrast(disp)) goto cleanup; diff --git a/src/freedreno/ci/gitlab-ci-inc.yml b/src/freedreno/ci/gitlab-ci-inc.yml index 5367b48c8cf..f71dcb1c067 100644 --- a/src/freedreno/ci/gitlab-ci-inc.yml +++ b/src/freedreno/ci/gitlab-ci-inc.yml @@ -292,25 +292,6 @@ tags: - google-freedreno-db410c -# New jobs. Leave it as manual for now. -.a306_piglit: - extends: - - .piglit-test - - .a306-test - - .google-freedreno-manual-rules - variables: - HWCI_START_XORG: 1 - -# Something happened and now this hangchecks and doesn't recover. Unkown when -# it started. -.a306_piglit_gl: - extends: - - .a306_piglit - variables: - PIGLIT_PROFILES: quick_gl - BM_KERNEL_EXTRA_ARGS: "msm.num_hw_submissions=1" - FDO_CI_CONCURRENT: 3 - # 8 devices (2023-04-15) .a530-test: extends: diff --git a/src/freedreno/ci/gitlab-ci.yml b/src/freedreno/ci/gitlab-ci.yml index f3c0b1738e2..9d19c21502a 100644 --- a/src/freedreno/ci/gitlab-ci.yml +++ b/src/freedreno/ci/gitlab-ci.yml @@ -10,6 +10,25 @@ a306_gl: FDO_CI_CONCURRENT: 6 parallel: 5 +# New jobs. Leave it as manual for now. +.a306_piglit: + extends: + - .piglit-test + - .a306-test + - .google-freedreno-manual-rules + variables: + HWCI_START_XORG: 1 + +# Something happened and now this hangchecks and doesn't recover. Unkown when +# it started. +.a306_piglit_gl: + extends: + - .a306_piglit + variables: + PIGLIT_PROFILES: quick_gl + BM_KERNEL_EXTRA_ARGS: "msm.num_hw_submissions=1" + FDO_CI_CONCURRENT: 3 + a306_piglit_shader: extends: - .a306_piglit diff --git a/src/freedreno/vulkan/.clang-format b/src/freedreno/vulkan/.clang-format index f7f9e5755db..8a1ae374067 100644 --- a/src/freedreno/vulkan/.clang-format +++ b/src/freedreno/vulkan/.clang-format @@ -20,5 +20,8 @@ IncludeCategories: - Regex: '.*' Priority: 1 +ForEachMacros: + - u_vector_foreach + SpaceAfterCStyleCast: true SpaceBeforeCpp11BracedList: true diff --git a/src/freedreno/vulkan/tu_knl.h b/src/freedreno/vulkan/tu_knl.h index e9293e3d08b..f10ba6fdd09 100644 --- a/src/freedreno/vulkan/tu_knl.h +++ b/src/freedreno/vulkan/tu_knl.h @@ -15,12 +15,12 @@ struct tu_u_trace_syncobj; struct vdrm_bo; -enum tu_bo_alloc_flags -{ +enum tu_bo_alloc_flags { TU_BO_ALLOC_NO_FLAGS = 0, TU_BO_ALLOC_ALLOW_DUMP = 1 << 0, TU_BO_ALLOC_GPU_READ_ONLY = 1 << 1, TU_BO_ALLOC_REPLAYABLE = 1 << 2, + TU_BO_ALLOC_DMABUF = 1 << 4, }; /* Define tu_timeline_sync type based on drm syncobj for a point type diff --git a/src/freedreno/vulkan/tu_knl_drm_msm.cc b/src/freedreno/vulkan/tu_knl_drm_msm.cc index 581a65e0e5b..7f48b3cb48e 100644 --- a/src/freedreno/vulkan/tu_knl_drm_msm.cc +++ b/src/freedreno/vulkan/tu_knl_drm_msm.cc @@ -321,44 +321,68 @@ tu_free_zombie_vma_locked(struct tu_device *dev, bool wait) last_signaled_fence = vma->fence; } - /* Ensure that internal kernel's vma is freed. */ - struct drm_msm_gem_info req = { - .handle = vma->gem_handle, - .info = MSM_INFO_SET_IOVA, - .value = 0, - }; + if (vma->gem_handle) { + /* Ensure that internal kernel's vma is freed. */ + struct drm_msm_gem_info req = { + .handle = vma->gem_handle, + .info = MSM_INFO_SET_IOVA, + .value = 0, + }; + + int ret = + drmCommandWriteRead(dev->fd, DRM_MSM_GEM_INFO, &req, sizeof(req)); + if (ret < 0) { + mesa_loge("MSM_INFO_SET_IOVA(0) failed! %d (%s)", ret, + strerror(errno)); + return VK_ERROR_UNKNOWN; + } - int ret = - drmCommandWriteRead(dev->fd, DRM_MSM_GEM_INFO, &req, sizeof(req)); - if (ret < 0) { - mesa_loge("MSM_INFO_SET_IOVA(0) failed! %d (%s)", ret, - strerror(errno)); - return VK_ERROR_UNKNOWN; - } + tu_gem_close(dev, vma->gem_handle); - tu_gem_close(dev, vma->gem_handle); + util_vma_heap_free(&dev->vma, vma->iova, vma->size); + } - util_vma_heap_free(&dev->vma, vma->iova, vma->size); u_vector_remove(&dev->zombie_vmas); } return VK_SUCCESS; } +static bool +tu_restore_from_zombie_vma_locked(struct tu_device *dev, + uint32_t gem_handle, + uint64_t *iova) +{ + struct tu_zombie_vma *vma; + u_vector_foreach (vma, &dev->zombie_vmas) { + if (vma->gem_handle == gem_handle) { + *iova = vma->iova; + + /* mark to skip later gem and iova cleanup */ + vma->gem_handle = 0; + return true; + } + } + + return false; +} + static VkResult -msm_allocate_userspace_iova(struct tu_device *dev, - uint32_t gem_handle, - uint64_t size, - uint64_t client_iova, - enum tu_bo_alloc_flags flags, - uint64_t *iova) +msm_allocate_userspace_iova_locked(struct tu_device *dev, + uint32_t gem_handle, + uint64_t size, + uint64_t client_iova, + enum tu_bo_alloc_flags flags, + uint64_t *iova) { VkResult result; - mtx_lock(&dev->vma_mutex); - *iova = 0; + if ((flags & TU_BO_ALLOC_DMABUF) && + tu_restore_from_zombie_vma_locked(dev, gem_handle, iova)) + return VK_SUCCESS; + tu_free_zombie_vma_locked(dev, false); result = tu_allocate_userspace_iova(dev, size, client_iova, flags, iova); @@ -372,8 +396,6 @@ msm_allocate_userspace_iova(struct tu_device *dev, result = tu_allocate_userspace_iova(dev, size, client_iova, flags, iova); } - mtx_unlock(&dev->vma_mutex); - if (result != VK_SUCCESS) return result; @@ -386,6 +408,7 @@ msm_allocate_userspace_iova(struct tu_device *dev, int ret = drmCommandWriteRead(dev->fd, DRM_MSM_GEM_INFO, &req, sizeof(req)); if (ret < 0) { + util_vma_heap_free(&dev->vma, *iova, size); mesa_loge("MSM_INFO_SET_IOVA failed! %d (%s)", ret, strerror(errno)); return VK_ERROR_OUT_OF_HOST_MEMORY; } @@ -420,8 +443,8 @@ tu_bo_init(struct tu_device *dev, assert(!client_iova || dev->physical_device->has_set_iova); if (dev->physical_device->has_set_iova) { - result = msm_allocate_userspace_iova(dev, gem_handle, size, client_iova, - flags, &iova); + result = msm_allocate_userspace_iova_locked(dev, gem_handle, size, + client_iova, flags, &iova); } else { result = tu_allocate_kernel_iova(dev, gem_handle, &iova); } @@ -445,6 +468,8 @@ tu_bo_init(struct tu_device *dev, if (!new_ptr) { dev->bo_count--; mtx_unlock(&dev->bo_mutex); + if (dev->physical_device->has_set_iova) + util_vma_heap_free(&dev->vma, iova, size); tu_gem_close(dev, gem_handle); return VK_ERROR_OUT_OF_HOST_MEMORY; } @@ -506,6 +531,20 @@ tu_bo_set_kernel_name(struct tu_device *dev, struct tu_bo *bo, const char *name) } } +static inline void +msm_vma_lock(struct tu_device *dev) +{ + if (dev->physical_device->has_set_iova) + mtx_lock(&dev->vma_mutex); +} + +static inline void +msm_vma_unlock(struct tu_device *dev) +{ + if (dev->physical_device->has_set_iova) + mtx_unlock(&dev->vma_mutex); +} + static VkResult msm_bo_init(struct tu_device *dev, struct tu_bo **out_bo, @@ -541,9 +580,15 @@ msm_bo_init(struct tu_device *dev, struct tu_bo* bo = tu_device_lookup_bo(dev, req.handle); assert(bo && bo->gem_handle == 0); + assert(!(flags & TU_BO_ALLOC_DMABUF)); + + msm_vma_lock(dev); + VkResult result = tu_bo_init(dev, bo, req.handle, size, client_iova, flags, name); + msm_vma_unlock(dev); + if (result != VK_SUCCESS) memset(bo, 0, sizeof(*bo)); else @@ -591,11 +636,13 @@ msm_bo_init_dmabuf(struct tu_device *dev, * to happen in parallel. */ u_rwlock_wrlock(&dev->dma_bo_lock); + msm_vma_lock(dev); uint32_t gem_handle; int ret = drmPrimeFDToHandle(dev->fd, prime_fd, &gem_handle); if (ret) { + msm_vma_unlock(dev); u_rwlock_wrunlock(&dev->dma_bo_lock); return vk_error(dev, VK_ERROR_INVALID_EXTERNAL_HANDLE); } @@ -604,6 +651,7 @@ msm_bo_init_dmabuf(struct tu_device *dev, if (bo->refcnt != 0) { p_atomic_inc(&bo->refcnt); + msm_vma_unlock(dev); u_rwlock_wrunlock(&dev->dma_bo_lock); *out_bo = bo; @@ -611,13 +659,14 @@ msm_bo_init_dmabuf(struct tu_device *dev, } VkResult result = - tu_bo_init(dev, bo, gem_handle, size, 0, TU_BO_ALLOC_NO_FLAGS, "dmabuf"); + tu_bo_init(dev, bo, gem_handle, size, 0, TU_BO_ALLOC_DMABUF, "dmabuf"); if (result != VK_SUCCESS) memset(bo, 0, sizeof(*bo)); else *out_bo = bo; + msm_vma_unlock(dev); u_rwlock_wrunlock(&dev->dma_bo_lock); return result; diff --git a/src/freedreno/vulkan/tu_knl_drm_virtio.cc b/src/freedreno/vulkan/tu_knl_drm_virtio.cc index 999a4af2fd4..e69c370dbab 100644 --- a/src/freedreno/vulkan/tu_knl_drm_virtio.cc +++ b/src/freedreno/vulkan/tu_knl_drm_virtio.cc @@ -412,14 +412,16 @@ tu_free_zombie_vma_locked(struct tu_device *dev, bool wait) last_signaled_fence = vma->fence; } - set_iova(dev, vma->res_id, 0); - u_vector_remove(&dev->zombie_vmas); - struct tu_zombie_vma *vma2 = (struct tu_zombie_vma *) - u_vector_add(&vdev->zombie_vmas_stage_2); + if (vma->gem_handle) { + set_iova(dev, vma->res_id, 0); + + struct tu_zombie_vma *vma2 = + (struct tu_zombie_vma *) u_vector_add(&vdev->zombie_vmas_stage_2); - *vma2 = *vma; + *vma2 = *vma; + } } /* And _then_ close the GEM handles: */ @@ -434,19 +436,44 @@ tu_free_zombie_vma_locked(struct tu_device *dev, bool wait) return VK_SUCCESS; } +static bool +tu_restore_from_zombie_vma_locked(struct tu_device *dev, + uint32_t gem_handle, + uint64_t *iova) +{ + struct tu_zombie_vma *vma; + u_vector_foreach (vma, &dev->zombie_vmas) { + if (vma->gem_handle == gem_handle) { + *iova = vma->iova; + + /* mark to skip later vdrm bo and iova cleanup */ + vma->gem_handle = 0; + return true; + } + } + + return false; +} + static VkResult -virtio_allocate_userspace_iova(struct tu_device *dev, - uint64_t size, - uint64_t client_iova, - enum tu_bo_alloc_flags flags, - uint64_t *iova) +virtio_allocate_userspace_iova_locked(struct tu_device *dev, + uint32_t gem_handle, + uint64_t size, + uint64_t client_iova, + enum tu_bo_alloc_flags flags, + uint64_t *iova) { VkResult result; - mtx_lock(&dev->vma_mutex); - *iova = 0; + if (flags & TU_BO_ALLOC_DMABUF) { + assert(gem_handle); + + if (tu_restore_from_zombie_vma_locked(dev, gem_handle, iova)) + return VK_SUCCESS; + } + tu_free_zombie_vma_locked(dev, false); result = tu_allocate_userspace_iova(dev, size, client_iova, flags, iova); @@ -460,8 +487,6 @@ virtio_allocate_userspace_iova(struct tu_device *dev, result = tu_allocate_userspace_iova(dev, size, client_iova, flags, iova); } - mtx_unlock(&dev->vma_mutex); - return result; } @@ -571,12 +596,8 @@ virtio_bo_init(struct tu_device *dev, .size = size, }; VkResult result; - - result = virtio_allocate_userspace_iova(dev, size, client_iova, - flags, &req.iova); - if (result != VK_SUCCESS) { - return result; - } + uint32_t res_id; + struct tu_bo *bo; if (mem_property & VK_MEMORY_PROPERTY_HOST_CACHED_BIT) { if (mem_property & VK_MEMORY_PROPERTY_HOST_COHERENT_BIT) { @@ -601,6 +622,16 @@ virtio_bo_init(struct tu_device *dev, if (flags & TU_BO_ALLOC_GPU_READ_ONLY) req.flags |= MSM_BO_GPU_READONLY; + assert(!(flags & TU_BO_ALLOC_DMABUF)); + + mtx_lock(&dev->vma_mutex); + result = virtio_allocate_userspace_iova_locked(dev, 0, size, client_iova, + flags, &req.iova); + mtx_unlock(&dev->vma_mutex); + + if (result != VK_SUCCESS) + return result; + /* tunneled cmds are processed separately on host side, * before the renderer->get_blob() callback.. the blob_id * is used to link the created bo to the get_blob() call @@ -611,27 +642,28 @@ virtio_bo_init(struct tu_device *dev, vdrm_bo_create(vdev->vdrm, size, blob_flags, req.blob_id, &req.hdr); if (!handle) { - util_vma_heap_free(&dev->vma, req.iova, size); - return vk_error(dev, VK_ERROR_OUT_OF_DEVICE_MEMORY); + result = VK_ERROR_OUT_OF_DEVICE_MEMORY; + goto fail; } - uint32_t res_id = vdrm_handle_to_res_id(vdev->vdrm, handle); - struct tu_bo* bo = tu_device_lookup_bo(dev, res_id); + res_id = vdrm_handle_to_res_id(vdev->vdrm, handle); + bo = tu_device_lookup_bo(dev, res_id); assert(bo && bo->gem_handle == 0); bo->res_id = res_id; result = tu_bo_init(dev, bo, handle, size, req.iova, flags, name); - if (result != VK_SUCCESS) + if (result != VK_SUCCESS) { memset(bo, 0, sizeof(*bo)); - else - *out_bo = bo; + goto fail; + } + + *out_bo = bo; /* We don't use bo->name here because for the !TU_DEBUG=bo case bo->name is NULL. */ tu_bo_set_kernel_name(dev, bo, name); - if (result == VK_SUCCESS && - (mem_property & VK_MEMORY_PROPERTY_HOST_CACHED_BIT) && + if ((mem_property & VK_MEMORY_PROPERTY_HOST_CACHED_BIT) && !(mem_property & VK_MEMORY_PROPERTY_HOST_COHERENT_BIT)) { tu_bo_map(dev, bo); @@ -644,6 +676,12 @@ virtio_bo_init(struct tu_device *dev, tu_sync_cache_bo(dev, bo, 0, VK_WHOLE_SIZE, TU_MEM_SYNC_CACHE_TO_GPU); } + return VK_SUCCESS; + +fail: + mtx_lock(&dev->vma_mutex); + util_vma_heap_free(&dev->vma, req.iova, size); + mtx_unlock(&dev->vma_mutex); return result; } @@ -666,11 +704,6 @@ virtio_bo_init_dmabuf(struct tu_device *dev, /* iova allocation needs to consider the object's *real* size: */ size = real_size; - uint64_t iova; - result = virtio_allocate_userspace_iova(dev, size, 0, TU_BO_ALLOC_NO_FLAGS, &iova); - if (result != VK_SUCCESS) - return result; - /* Importing the same dmabuf several times would yield the same * gem_handle. Thus there could be a race when destroying * BO and importing the same dmabuf from different threads. @@ -678,8 +711,10 @@ virtio_bo_init_dmabuf(struct tu_device *dev, * to happen in parallel. */ u_rwlock_wrlock(&dev->dma_bo_lock); + mtx_lock(&dev->vma_mutex); uint32_t handle, res_id; + uint64_t iova; handle = vdrm_dmabuf_to_handle(vdrm, prime_fd); if (!handle) { @@ -689,6 +724,7 @@ virtio_bo_init_dmabuf(struct tu_device *dev, res_id = vdrm_handle_to_res_id(vdrm, handle); if (!res_id) { + /* XXX gem_handle potentially leaked here since no refcnt */ result = vk_error(dev, VK_ERROR_INVALID_EXTERNAL_HANDLE); goto out_unlock; } @@ -702,21 +738,25 @@ virtio_bo_init_dmabuf(struct tu_device *dev, goto out_unlock; } - result = tu_bo_init(dev, bo, handle, size, iova, - TU_BO_ALLOC_NO_FLAGS, "dmabuf"); - if (result != VK_SUCCESS) - memset(bo, 0, sizeof(*bo)); - else - *out_bo = bo; + result = virtio_allocate_userspace_iova_locked(dev, handle, size, 0, + TU_BO_ALLOC_DMABUF, &iova); + if (result != VK_SUCCESS) { + vdrm_bo_close(dev->vdev->vdrm, handle); + goto out_unlock; + } -out_unlock: - u_rwlock_wrunlock(&dev->dma_bo_lock); + result = + tu_bo_init(dev, bo, handle, size, iova, TU_BO_ALLOC_NO_FLAGS, "dmabuf"); if (result != VK_SUCCESS) { - mtx_lock(&dev->vma_mutex); util_vma_heap_free(&dev->vma, iova, size); - mtx_unlock(&dev->vma_mutex); + memset(bo, 0, sizeof(*bo)); + } else { + *out_bo = bo; } +out_unlock: + mtx_unlock(&dev->vma_mutex); + u_rwlock_wrunlock(&dev->dma_bo_lock); return result; } diff --git a/src/gallium/auxiliary/meson.build b/src/gallium/auxiliary/meson.build index 96b0272c69b..17522637bcc 100644 --- a/src/gallium/auxiliary/meson.build +++ b/src/gallium/auxiliary/meson.build @@ -549,7 +549,7 @@ if with_tests ) endif -libgalliumvl_stub = static_library( +_libgalliumvl_stub = static_library( 'galliumvl_stub', 'vl/vl_stubs.c', c_args : [c_msvc_compat_args], @@ -571,6 +571,15 @@ libgalliumvl = static_library( build_by_default : false, ) +# some drivers export their screen creation function globally, so all frontends have to contain the +# full libgalliumvl. So we'll handle this here globally for everybody. +if (with_gallium_va or with_gallium_vdpau or with_gallium_omx != 'disabled' or + with_dri or with_gallium_radeonsi) + libgalliumvl_stub = libgalliumvl +else + libgalliumvl_stub = _libgalliumvl_stub +endif + # XXX: The dependencies here may be off... libgalliumvlwinsys = static_library( 'galliumvlwinsys', diff --git a/src/gallium/auxiliary/nir/nir_draw_helpers.c b/src/gallium/auxiliary/nir/nir_draw_helpers.c index 630f37b97e7..e10687cf8ef 100644 --- a/src/gallium/auxiliary/nir/nir_draw_helpers.c +++ b/src/gallium/auxiliary/nir/nir_draw_helpers.c @@ -177,6 +177,9 @@ lower_aaline_instr(nir_builder *b, nir_instr *instr, void *data) return false; if (var->data.location < FRAG_RESULT_DATA0 && var->data.location != FRAG_RESULT_COLOR) return false; + uint32_t mask = nir_intrinsic_write_mask(intrin) << var->data.location_frac; + if (!(mask & BITFIELD_BIT(3))) + return false; nir_def *out_input = intrin->src[1].ssa; b->cursor = nir_before_instr(instr); @@ -223,12 +226,10 @@ lower_aaline_instr(nir_builder *b, nir_instr *instr, void *data) tmp = nir_fmul(b, nir_channel(b, tmp, 0), nir_fmin(b, nir_channel(b, tmp, 1), max)); - tmp = nir_fmul(b, nir_channel(b, out_input, 3), tmp); + tmp = nir_fmul(b, nir_channel(b, out_input, out_input->num_components - 1), tmp); - nir_def *out = nir_vec4(b, nir_channel(b, out_input, 0), - nir_channel(b, out_input, 1), - nir_channel(b, out_input, 2), - tmp); + nir_def *out = nir_vector_insert_imm(b, out_input, tmp, + out_input->num_components - 1); nir_src_rewrite(&intrin->src[1], out); return true; } diff --git a/src/gallium/auxiliary/util/u_blitter.c b/src/gallium/auxiliary/util/u_blitter.c index be24ec084aa..3300a0f776c 100644 --- a/src/gallium/auxiliary/util/u_blitter.c +++ b/src/gallium/auxiliary/util/u_blitter.c @@ -2014,6 +2014,7 @@ void util_blitter_blit_generic(struct blitter_context *blitter, unsigned dst_sample) { struct blitter_context_priv *ctx = (struct blitter_context_priv*)blitter; + unsigned count = 0; struct pipe_context *pipe = ctx->base.pipe; enum pipe_texture_target src_target = src->target; unsigned src_samples = src->texture->nr_samples; @@ -2038,7 +2039,7 @@ void util_blitter_blit_generic(struct blitter_context *blitter, /* Return if there is nothing to do. */ if (!dst_has_color && !dst_has_depth && !dst_has_stencil) { - return; + goto out; } bool is_scaled = dstbox->width != abs(srcbox->width) || @@ -2170,7 +2171,6 @@ void util_blitter_blit_generic(struct blitter_context *blitter, } /* Set samplers. */ - unsigned count = 0; if (src_has_depth && src_has_stencil && (dst_has_color || (dst_has_depth && dst_has_stencil))) { /* Setup two samplers, one for depth and the other one for stencil. */ @@ -2223,7 +2223,8 @@ void util_blitter_blit_generic(struct blitter_context *blitter, do_blits(ctx, dst, dstbox, src, src_width0, src_height0, srcbox, dst_has_depth || dst_has_stencil, use_txf, sample0_only, dst_sample); - + util_blitter_unset_running_flag(blitter); +out: util_blitter_restore_vertex_states(blitter); util_blitter_restore_fragment_states(blitter); util_blitter_restore_textures_internal(blitter, count); @@ -2232,7 +2233,6 @@ void util_blitter_blit_generic(struct blitter_context *blitter, pipe->set_scissor_states(pipe, 0, 1, &ctx->base.saved_scissor); } util_blitter_restore_render_cond(blitter); - util_blitter_unset_running_flag(blitter); } void diff --git a/src/gallium/auxiliary/vl/vl_stubs.c b/src/gallium/auxiliary/vl/vl_stubs.c index 194e7a8700b..cd6b73b850b 100644 --- a/src/gallium/auxiliary/vl/vl_stubs.c +++ b/src/gallium/auxiliary/vl/vl_stubs.c @@ -108,6 +108,16 @@ vl_video_buffer_create_ex2(struct pipe_context *pipe, return NULL; } +struct pipe_video_buffer * +vl_video_buffer_create_as_resource(struct pipe_context *pipe, + const struct pipe_video_buffer *tmpl, + const uint64_t *modifiers, + int modifiers_count) +{ + assert(0); + return NULL; +} + void vl_video_buffer_destroy(struct pipe_video_buffer *buffer) { @@ -145,9 +155,3 @@ vl_create_mpeg12_decoder(struct pipe_context *pipe, assert(0); return NULL; } - -/* - * vl_zscan - */ -const int vl_zscan_normal[] = {0}; -const int vl_zscan_alternate[] = {0}; diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.cc b/src/gallium/drivers/freedreno/a6xx/fd6_program.cc index 4ee1852b757..183bba9b1af 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_program.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.cc @@ -119,7 +119,7 @@ fd6_emit_shader(struct fd_context *ctx, struct fd_ringbuffer *ring, #endif gl_shader_stage type = so->type; - if (type == MESA_SHADER_COMPUTE) + if (type == MESA_SHADER_KERNEL) type = MESA_SHADER_COMPUTE; enum a6xx_threadsize thrsz = diff --git a/src/gallium/drivers/nouveau/ci/gitlab-ci-inc.yml b/src/gallium/drivers/nouveau/ci/gitlab-ci-inc.yml index a2fb4821bc4..5d041b61282 100644 --- a/src/gallium/drivers/nouveau/ci/gitlab-ci-inc.yml +++ b/src/gallium/drivers/nouveau/ci/gitlab-ci-inc.yml @@ -70,20 +70,3 @@ tags: - google-nouveau-jetson-nano -# Single Jetson Nano board at anholt's house. -.gm20b-gles-full: - extends: - - .gm20b-test - - .nouveau-manual-rules - timeout: 2h - variables: - HWCI_TEST_SCRIPT: "/install/deqp-runner.sh" - DEQP_SUITE: nouveau-gm20b - TEST_PHASE_TIMEOUT: 120 - -.gm20b-gles: - extends: - - .gm20b-gles-full - timeout: 30m - variables: - DEQP_FRACTION: 10 diff --git a/src/gallium/drivers/nouveau/ci/gitlab-ci.yml b/src/gallium/drivers/nouveau/ci/gitlab-ci.yml index 90ee2b58d82..673d77eaee2 100644 --- a/src/gallium/drivers/nouveau/ci/gitlab-ci.yml +++ b/src/gallium/drivers/nouveau/ci/gitlab-ci.yml @@ -12,3 +12,21 @@ gk20a-gles: DEQP_SUITE: nouveau-gk20a FARM : anholt DEVICE_TYPE: anholt-jetson + +# Single Jetson Nano board at anholt's house. +.gm20b-gles-full: + extends: + - .gm20b-test + - .nouveau-manual-rules + timeout: 2h + variables: + HWCI_TEST_SCRIPT: "/install/deqp-runner.sh" + DEQP_SUITE: nouveau-gm20b + TEST_PHASE_TIMEOUT: 120 + +.gm20b-gles: + extends: + - .gm20b-gles-full + timeout: 30m + variables: + DEQP_FRACTION: 10 diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index fe6cb10b1e9..511a74e3dd4 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -2137,7 +2137,8 @@ static void evergreen_emit_vertex_buffers(struct r600_context *rctx, { struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; struct r600_fetch_shader *shader = (struct r600_fetch_shader*)rctx->vertex_fetch_shader.cso; - uint32_t dirty_mask = state->dirty_mask & shader->buffer_mask; + uint32_t buffer_mask = shader ? shader->buffer_mask : ~0; + uint32_t dirty_mask = state->dirty_mask & buffer_mask; while (dirty_mask) { struct pipe_vertex_buffer *vb; @@ -2176,7 +2177,7 @@ static void evergreen_emit_vertex_buffers(struct r600_context *rctx, radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer, RADEON_USAGE_READ | RADEON_PRIO_VERTEX_BUFFER)); } - state->dirty_mask &= ~shader->buffer_mask; + state->dirty_mask &= ~buffer_mask; } static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom) diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_dec.c b/src/gallium/drivers/radeonsi/radeon_vcn_dec.c index ad12990fa60..ee52d8c7f5a 100644 --- a/src/gallium/drivers/radeonsi/radeon_vcn_dec.c +++ b/src/gallium/drivers/radeonsi/radeon_vcn_dec.c @@ -239,15 +239,13 @@ static rvcn_dec_message_avc_t get_h264_msg(struct radeon_decoder *dec, } } - /* if reference picture exists, however no reference picture found at the end - curr_pic_ref_frame_num == 0, which is not reasonable, should be corrected. */ - if (result.used_for_reference_flags && (result.curr_pic_ref_frame_num == 0)) { - for (i = 0; i < ARRAY_SIZE(result.ref_frame_list); i++) { - result.ref_frame_list[i] = pic->ref[i] ? - (uintptr_t)vl_video_buffer_get_associated_data(pic->ref[i], &dec->base) : 0xff; - if (result.ref_frame_list[i] != 0xff) { + /* need at least one reference for P/B frames */ + if (result.curr_pic_ref_frame_num == 0 && pic->slice_parameter.slice_info_present) { + for (i = 0; i < pic->slice_count; i++) { + if (pic->slice_parameter.slice_type[i] % 5 != 2) { result.curr_pic_ref_frame_num++; - result.non_existing_frame_flags &= ~(1 << i); + result.ref_frame_list[0] = 0; + result.non_existing_frame_flags &= ~1; break; } } @@ -279,7 +277,8 @@ static rvcn_dec_message_avc_t get_h264_msg(struct radeon_decoder *dec, dec->ref_codec.bts = CODEC_8_BITS; dec->ref_codec.index = result.decoded_pic_idx; dec->ref_codec.ref_size = 16; - memset(dec->ref_codec.ref_list, 0xff, sizeof(dec->ref_codec.ref_list)); + dec->ref_codec.num_refs = result.curr_pic_ref_frame_num; + STATIC_ASSERT(sizeof(dec->ref_codec.ref_list) == sizeof(result.ref_frame_list)); memcpy(dec->ref_codec.ref_list, result.ref_frame_list, sizeof(result.ref_frame_list)); } @@ -292,7 +291,7 @@ static rvcn_dec_message_hevc_t get_h265_msg(struct radeon_decoder *dec, struct pipe_h265_picture_desc *pic) { rvcn_dec_message_hevc_t result; - unsigned i, j; + unsigned i, j, num_refs = 0; memset(&result, 0, sizeof(result)); result.sps_info_flags = 0; @@ -413,9 +412,10 @@ static rvcn_dec_message_hevc_t get_h265_msg(struct radeon_decoder *dec, result.poc_list[i] = pic->PicOrderCntVal[i]; - if (ref) + if (ref) { ref_pic = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base); - else + num_refs++; + } else ref_pic = 0x7F; result.ref_pic_list[i] = ref_pic; } @@ -469,7 +469,8 @@ static rvcn_dec_message_hevc_t get_h265_msg(struct radeon_decoder *dec, CODEC_10_BITS : CODEC_8_BITS; dec->ref_codec.index = result.curr_idx; dec->ref_codec.ref_size = 15; - memset(dec->ref_codec.ref_list, 0x7f, sizeof(dec->ref_codec.ref_list)); + dec->ref_codec.num_refs = num_refs; + STATIC_ASSERT(sizeof(dec->ref_codec.ref_list) == sizeof(result.ref_pic_list)); memcpy(dec->ref_codec.ref_list, result.ref_pic_list, sizeof(result.ref_pic_list)); } return result; @@ -507,7 +508,7 @@ static rvcn_dec_message_vp9_t get_vp9_msg(struct radeon_decoder *dec, struct pipe_vp9_picture_desc *pic) { rvcn_dec_message_vp9_t result; - unsigned i ,j; + unsigned i, j, num_refs = 0; memset(&result, 0, sizeof(result)); @@ -641,9 +642,13 @@ static rvcn_dec_message_vp9_t get_vp9_msg(struct radeon_decoder *dec, get_current_pic_index(dec, target, &result.curr_pic_idx); for (i = 0; i < 8; i++) { - result.ref_frame_map[i] = - (pic->ref[i]) ? (uintptr_t)vl_video_buffer_get_associated_data(pic->ref[i], &dec->base) - : 0x7f; + uintptr_t ref_frame; + if (pic->ref[i]) { + ref_frame = (uintptr_t)vl_video_buffer_get_associated_data(pic->ref[i], &dec->base); + num_refs++; + } else + ref_frame = 0x7f; + result.ref_frame_map[i] = ref_frame; } result.frame_refs[0] = result.ref_frame_map[pic->picture_parameter.pic_fields.last_ref_frame]; @@ -669,6 +674,7 @@ static rvcn_dec_message_vp9_t get_vp9_msg(struct radeon_decoder *dec, CODEC_10_BITS : CODEC_8_BITS; dec->ref_codec.index = result.curr_pic_idx; dec->ref_codec.ref_size = 8; + dec->ref_codec.num_refs = num_refs; memset(dec->ref_codec.ref_list, 0x7f, sizeof(dec->ref_codec.ref_list)); memcpy(dec->ref_codec.ref_list, result.ref_frame_map, sizeof(result.ref_frame_map)); } @@ -959,7 +965,7 @@ static rvcn_dec_message_av1_t get_av1_msg(struct radeon_decoder *dec, struct pipe_av1_picture_desc *pic) { rvcn_dec_message_av1_t result; - unsigned i, j; + unsigned i, j, num_refs = 0; uint16_t tile_count = pic->picture_parameter.tile_cols * pic->picture_parameter.tile_rows; memset(&result, 0, sizeof(result)); @@ -1151,9 +1157,13 @@ static rvcn_dec_message_av1_t get_av1_msg(struct radeon_decoder *dec, result.order_hint_bits = pic->picture_parameter.order_hint_bits_minus_1 + 1; for (i = 0; i < NUM_AV1_REFS; ++i) { - result.ref_frame_map[i] = - (pic->ref[i]) ? (uintptr_t)vl_video_buffer_get_associated_data(pic->ref[i], &dec->base) - : 0x7f; + uintptr_t ref_frame; + if (pic->ref[i]) { + ref_frame = (uintptr_t)vl_video_buffer_get_associated_data(pic->ref[i], &dec->base); + num_refs++; + } else + ref_frame = 0x7f; + result.ref_frame_map[i] = ref_frame; } for (i = 0; i < NUM_AV1_REFS_PER_FRAME; ++i) result.frame_refs[i] = result.ref_frame_map[pic->picture_parameter.ref_frame_idx[i]]; @@ -1300,6 +1310,7 @@ static rvcn_dec_message_av1_t get_av1_msg(struct radeon_decoder *dec, dec->ref_codec.bts = pic->picture_parameter.bit_depth_idx ? CODEC_10_BITS : CODEC_8_BITS; dec->ref_codec.index = result.curr_pic_idx; dec->ref_codec.ref_size = 8; + dec->ref_codec.num_refs = num_refs; memset(dec->ref_codec.ref_list, 0x7f, sizeof(dec->ref_codec.ref_list)); memcpy(dec->ref_codec.ref_list, result.ref_frame_map, sizeof(result.ref_frame_map)); } @@ -1816,6 +1827,7 @@ static unsigned rvcn_dec_dynamic_dpb_t2_message(struct radeon_decoder *dec, rvcn size = size * 3 / 2; list_for_each_entry_safe(struct rvcn_dec_dynamic_dpb_t2, d, &dec->dpb_ref_list, list) { + bool found = false; for (i = 0; i < dec->ref_codec.ref_size; ++i) { if (((dec->ref_codec.ref_list[i] & 0x7f) != 0x7f) && (d->index == (dec->ref_codec.ref_list[i] & 0x7f))) { if (!dummy) @@ -1829,10 +1841,10 @@ static unsigned rvcn_dec_dynamic_dpb_t2_message(struct radeon_decoder *dec, rvcn dynamic_dpb_t2->dpbAddrLo[i] = addr; dynamic_dpb_t2->dpbAddrHi[i] = addr >> 32; ++dynamic_dpb_t2->dpbArraySize; - break; + found = true; } } - if (i == dec->ref_codec.ref_size) { + if (!found) { if (d->dpb.res->b.b.width0 * d->dpb.res->b.b.height0 != size) { list_del(&d->list); list_addtail(&d->list, &dec->dpb_unref_list); @@ -1887,6 +1899,23 @@ static unsigned rvcn_dec_dynamic_dpb_t2_message(struct radeon_decoder *dec, rvcn list_addtail(&dpb->list, &dec->dpb_ref_list); } + if (dynamic_dpb_t2->dpbArraySize < dec->ref_codec.num_refs) { + struct rvcn_dec_dynamic_dpb_t2 *d = + list_first_entry(&dec->dpb_ref_list, struct rvcn_dec_dynamic_dpb_t2, list); + addr = dec->ws->buffer_get_virtual_address(d->dpb.res->buf); + if (!addr && dummy) + addr = dec->ws->buffer_get_virtual_address(dummy->dpb.res->buf); + assert(addr); + for (i = 0; i < dec->ref_codec.num_refs; ++i) { + if (dynamic_dpb_t2->dpbAddrLo[i] || dynamic_dpb_t2->dpbAddrHi[i]) + continue; + dynamic_dpb_t2->dpbAddrLo[i] = addr; + dynamic_dpb_t2->dpbAddrHi[i] = addr >> 32; + ++dynamic_dpb_t2->dpbArraySize; + } + assert(dynamic_dpb_t2->dpbArraySize == dec->ref_codec.num_refs); + } + dec->ws->cs_add_buffer(&dec->cs, dpb->dpb.res->buf, RADEON_USAGE_READWRITE | RADEON_USAGE_SYNCHRONIZED, RADEON_DOMAIN_VRAM); addr = dec->ws->buffer_get_virtual_address(dpb->dpb.res->buf); diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_dec.h b/src/gallium/drivers/radeonsi/radeon_vcn_dec.h index 1be65c7ded8..3d502ce7b66 100644 --- a/src/gallium/drivers/radeonsi/radeon_vcn_dec.h +++ b/src/gallium/drivers/radeonsi/radeon_vcn_dec.h @@ -120,6 +120,7 @@ struct radeon_decoder { } bts; uint8_t index; unsigned ref_size; + unsigned num_refs; uint8_t ref_list[16]; } ref_codec; diff --git a/src/gallium/drivers/radeonsi/si_buffer.c b/src/gallium/drivers/radeonsi/si_buffer.c index 85d0ea5dffc..f4dfd27881f 100644 --- a/src/gallium/drivers/radeonsi/si_buffer.c +++ b/src/gallium/drivers/radeonsi/si_buffer.c @@ -176,6 +176,15 @@ bool si_alloc_resource(struct si_screen *sscreen, struct si_resource *res) util_range_set_empty(&res->valid_buffer_range); res->TC_L2_dirty = false; + if (res->b.b.target != PIPE_BUFFER && !(res->b.b.flags & SI_RESOURCE_AUX_PLANE)) { + /* The buffer is shared with other planes. */ + struct si_resource *plane = (struct si_resource *)res->b.b.next; + for (; plane; plane = (struct si_resource *)plane->b.b.next) { + radeon_bo_reference(sscreen->ws, &plane->buf, res->buf); + plane->gpu_address = res->gpu_address; + } + } + /* Print debug information. */ if (sscreen->debug_flags & DBG(VM) && res->b.b.target == PIPE_BUFFER) { fprintf(stderr, "VM start=0x%" PRIX64 " end=0x%" PRIX64 " | Buffer %" PRIu64 " bytes | Flags: ", diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index c28acdd428d..7075acfba2d 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -6289,7 +6289,7 @@ static void gfx10_init_gfx_preamble_state(struct si_context *sctx) for (unsigned i = 0; i < 4; ++i) si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 + i * 4, - i < sscreen->info.num_se ? compute_cu_en : 0x0); + i < sscreen->info.max_se ? compute_cu_en : 0x0); si_pm4_set_reg(pm4, R_00B890_COMPUTE_USER_ACCUM_0, 0); si_pm4_set_reg(pm4, R_00B894_COMPUTE_USER_ACCUM_1, 0); @@ -6299,7 +6299,7 @@ static void gfx10_init_gfx_preamble_state(struct si_context *sctx) if (sctx->gfx_level >= GFX11) { for (unsigned i = 4; i < 8; ++i) si_pm4_set_reg(pm4, R_00B8AC_COMPUTE_STATIC_THREAD_MGMT_SE4 + (i - 4) * 4, - i < sscreen->info.num_se ? compute_cu_en : 0x0); + i < sscreen->info.max_se ? compute_cu_en : 0x0); /* How many threads should go to 1 SE before moving onto the next. Think of GL1 cache hits. * Only these values are valid: 0 (disabled), 64, 128, 256, 512 diff --git a/src/gallium/drivers/v3d/v3d_cl.c b/src/gallium/drivers/v3d/v3d_cl.c index d8ee4ffc206..42cfd6282bf 100644 --- a/src/gallium/drivers/v3d/v3d_cl.c +++ b/src/gallium/drivers/v3d/v3d_cl.c @@ -32,6 +32,16 @@ #include "broadcom/common/v3d_macros.h" #include "broadcom/cle/v3dx_pack.h" +/* The Control List Executor (CLE) pre-fetches V3D_CLE_READAHEAD bytes from + * the Control List buffer. The usage of these last bytes should be avoided or + * the CLE would pre-fetch the data after the end of the CL buffer, reporting + * the kernel "MMU error from client CLE". + */ +#define V3D42_CLE_READAHEAD 256u +#define V3D42_CLE_BUFFER_MIN_SIZE 4096u +#define V3D71_CLE_READAHEAD 1024u +#define V3D71_CLE_BUFFER_MIN_SIZE 16384u + void v3d_init_cl(struct v3d_job *job, struct v3d_cl *cl) { @@ -50,9 +60,12 @@ v3d_cl_ensure_space(struct v3d_cl *cl, uint32_t space, uint32_t alignment) cl->next = cl->base + offset; return offset; } - + struct v3d_device_info *devinfo = &cl->job->v3d->screen->devinfo; + uint32_t cle_buffer_min_size = V3DV_X(devinfo, CLE_BUFFER_MIN_SIZE); v3d_bo_unreference(&cl->bo); - cl->bo = v3d_bo_alloc(cl->job->v3d->screen, align(space, 4096), "CL"); + cl->bo = v3d_bo_alloc(cl->job->v3d->screen, + align(space, cle_buffer_min_size), + "CL"); cl->base = v3d_bo_map(cl->bo); cl->size = cl->bo->size; cl->next = cl->base; @@ -63,14 +76,30 @@ v3d_cl_ensure_space(struct v3d_cl *cl, uint32_t space, uint32_t alignment) void v3d_cl_ensure_space_with_branch(struct v3d_cl *cl, uint32_t space) { - if (cl_offset(cl) + space + cl_packet_length(BRANCH) <= cl->size) + if (cl_offset(cl) + space <= cl->size) return; - struct v3d_bo *new_bo = v3d_bo_alloc(cl->job->v3d->screen, space, "CL"); - assert(space <= new_bo->size); + /* The last V3D_CLE_READAHEAD bytes of the buffer are unusable, so we + * need to take them into account when allocating a new BO for the + * CL. We have to be sure that we have room for a BRANCH packet so we + * can always chain a next BO if needed. We will need to increase + * cl->size by the packet length before calling cl_summit to use this + * reserved space. + */ + struct v3d_device_info *devinfo = &cl->job->v3d->screen->devinfo; + uint32_t cle_readahead = V3DV_X(devinfo, CLE_READAHEAD); + uint32_t cle_buffer_min_size = V3DV_X(devinfo, CLE_BUFFER_MIN_SIZE); + uint32_t unusable_size = cle_readahead + cl_packet_length(BRANCH); + struct v3d_bo *new_bo = v3d_bo_alloc(cl->job->v3d->screen, + align(space + unusable_size, + cle_buffer_min_size), + "CL"); + assert(space + unusable_size <= new_bo->size); /* Chain to the new BO from the old one. */ if (cl->bo) { + cl->size += cl_packet_length(BRANCH); + assert(cl->size + cle_readahead <= cl->bo->size); cl_emit(cl, BRANCH, branch) { branch.address = cl_address(new_bo, 0); } @@ -82,7 +111,11 @@ v3d_cl_ensure_space_with_branch(struct v3d_cl *cl, uint32_t space) cl->bo = new_bo; cl->base = v3d_bo_map(cl->bo); - cl->size = cl->bo->size; + /* Take only into account the usable size of the BO to guarantee that + * we never write in the last bytes of the CL buffer because of the + * readahead of the CLE + */ + cl->size = cl->bo->size - unusable_size; cl->next = cl->base; } diff --git a/src/gallium/drivers/v3d/v3d_cl.h b/src/gallium/drivers/v3d/v3d_cl.h index de966d2baad..76d8c3aa300 100644 --- a/src/gallium/drivers/v3d/v3d_cl.h +++ b/src/gallium/drivers/v3d/v3d_cl.h @@ -234,6 +234,7 @@ cl_get_emit_space(struct v3d_cl_out **cl, size_t size) cl_advance(&cl_out, cl_packet_length(packet)); \ cl_end(cl, cl_out); \ _loop_terminate = NULL; \ + assert(cl_offset(cl) <= (cl)->size); \ })) \ #define cl_emit_with_prepacked(cl, packet, prepacked, name) \ @@ -253,9 +254,10 @@ cl_get_emit_space(struct v3d_cl_out **cl, size_t size) _loop_terminate = NULL; \ })) \ -#define cl_emit_prepacked_sized(cl, packet, size) do { \ - memcpy((cl)->next, packet, size); \ - cl_advance(&(cl)->next, size); \ +#define cl_emit_prepacked_sized(cl, packet, psize) do { \ + memcpy((cl)->next, packet, psize); \ + cl_advance(&(cl)->next, psize); \ + assert(cl_offset(cl) <= (cl)->size); \ } while (0) #define cl_emit_prepacked(cl, packet) \ diff --git a/src/gallium/drivers/zink/ci/zink-anv-tgl-fails.txt b/src/gallium/drivers/zink/ci/zink-anv-tgl-fails.txt index e9d05f3a463..1f4373e869d 100644 --- a/src/gallium/drivers/zink/ci/zink-anv-tgl-fails.txt +++ b/src/gallium/drivers/zink/ci/zink-anv-tgl-fails.txt @@ -668,3 +668,8 @@ KHR-GL46.sparse_texture_tests.SparseTextureCommitment,Crash # Assertion `size % ZINK_SPARSE_BUFFER_PAGE_SIZE == 0 || offset + size == bo->base.size' failed. spec@arb_sparse_buffer@basic,Crash spec@arb_sparse_buffer@buffer-data,Crash + +# Failing on a bunch of drivers with an assert on the weak_ref +# pipeline cache, seems to be a zink issue not destroying a +# shader/pipeline before calling vkDestroyPipeline() +spec@ext_external_objects@vk-vert-buf-reuse,Crash diff --git a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c index 91a406e7801..e59df2b9ce4 100644 --- a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c +++ b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c @@ -1933,13 +1933,7 @@ emit_alu(struct ntv_context *ctx, nir_alu_instr *alu) result = emit_builtin_unop(ctx, GLSLstd450PackHalf2x16, get_def_type(ctx, &alu->def, nir_type_uint), src[0]); break; - case nir_op_unpack_64_2x32: - assert(nir_op_infos[alu->op].num_inputs == 1); - result = emit_builtin_unop(ctx, GLSLstd450UnpackDouble2x32, get_def_type(ctx, &alu->def, nir_type_uint), src[0]); - break; - BUILTIN_UNOPF(nir_op_unpack_half_2x16, GLSLstd450UnpackHalf2x16) - BUILTIN_UNOPF(nir_op_pack_64_2x32, GLSLstd450PackDouble2x32) #undef BUILTIN_UNOP #undef BUILTIN_UNOPF @@ -2125,9 +2119,11 @@ emit_alu(struct ntv_context *ctx, nir_alu_instr *alu) /* those are all simple bitcasts, we could do better, but it doesn't matter */ case nir_op_pack_32_4x8: case nir_op_pack_32_2x16: + case nir_op_pack_64_2x32: case nir_op_pack_64_4x16: case nir_op_unpack_32_4x8: case nir_op_unpack_32_2x16: + case nir_op_unpack_64_2x32: case nir_op_unpack_64_4x16: { result = emit_bitcast(ctx, dest_type, src[0]); break; diff --git a/src/gallium/drivers/zink/zink_batch.c b/src/gallium/drivers/zink/zink_batch.c index e774d1f7c5b..b8abb68e53d 100644 --- a/src/gallium/drivers/zink/zink_batch.c +++ b/src/gallium/drivers/zink/zink_batch.c @@ -309,6 +309,11 @@ zink_batch_state_destroy(struct zink_screen *screen, struct zink_batch_state *bs util_dynarray_fini(&bs->bindless_releases[0]); util_dynarray_fini(&bs->bindless_releases[1]); util_dynarray_fini(&bs->acquires); + util_dynarray_fini(&bs->signal_semaphores); + util_dynarray_fini(&bs->wait_semaphores); + util_dynarray_fini(&bs->wait_semaphore_stages); + util_dynarray_fini(&bs->fd_wait_semaphores); + util_dynarray_fini(&bs->fd_wait_semaphore_stages); util_dynarray_fini(&bs->acquire_flags); unsigned num_mfences = util_dynarray_num_elements(&bs->fence.mfences, void *); struct zink_tc_fence **mfence = bs->fence.mfences.data; diff --git a/src/gallium/drivers/zink/zink_context.c b/src/gallium/drivers/zink/zink_context.c index 46d7b9ee691..31c9f38f012 100644 --- a/src/gallium/drivers/zink/zink_context.c +++ b/src/gallium/drivers/zink/zink_context.c @@ -4846,8 +4846,11 @@ zink_resource_commit(struct pipe_context *pctx, struct pipe_resource *pres, unsi VkSemaphore sem = VK_NULL_HANDLE; bool ret = zink_bo_commit(ctx, res, level, box, commit, &sem); if (ret) { - if (sem) + if (sem) { zink_batch_add_wait_semaphore(&ctx->batch, sem); + zink_batch_reference_resource_rw(&ctx->batch, res, true); + ctx->batch.has_work = true; + } } else { check_device_lost(ctx); } diff --git a/src/gallium/drivers/zink/zink_query.c b/src/gallium/drivers/zink/zink_query.c index c10fb4fd8f4..e00bcafa047 100644 --- a/src/gallium/drivers/zink/zink_query.c +++ b/src/gallium/drivers/zink/zink_query.c @@ -971,7 +971,7 @@ zink_begin_query(struct pipe_context *pctx, util_dynarray_clear(&query->starts); query->start_offset = 0; - if (batch->in_rp) { + if (batch->in_rp || (query->type == PIPE_QUERY_TIME_ELAPSED)) { begin_query(ctx, batch, query); } else { /* never directly start queries out of renderpass, always defer */ diff --git a/src/gallium/frontends/clover/llvm/invocation.cpp b/src/gallium/frontends/clover/llvm/invocation.cpp index 6ab32befbcd..e899b205d22 100644 --- a/src/gallium/frontends/clover/llvm/invocation.cpp +++ b/src/gallium/frontends/clover/llvm/invocation.cpp @@ -513,6 +513,7 @@ namespace { LLVMRunPasses(wrap(&mod), opt_str, tm, opts); LLVMDisposeTargetMachine(tm); + LLVMDisposePassBuilderOptions(opts); } std::unique_ptr diff --git a/src/gallium/frontends/dri/dri2.c b/src/gallium/frontends/dri/dri2.c index ad68f3b08c0..d0f87d9c46f 100644 --- a/src/gallium/frontends/dri/dri2.c +++ b/src/gallium/frontends/dri/dri2.c @@ -2385,7 +2385,7 @@ dri2_init_screen(struct dri_screen *screen) pscreen = pipe_loader_create_screen(screen->dev); if (!pscreen) - goto fail; + return NULL; dri_init_options(screen); screen->throttle = pscreen->get_param(pscreen, PIPE_CAP_THROTTLE); @@ -2419,7 +2419,7 @@ dri2_init_screen(struct dri_screen *screen) return configs; fail: - dri_release_screen(screen); + pipe_loader_release(&screen->dev, 1); return NULL; } diff --git a/src/gallium/frontends/dri/drisw.c b/src/gallium/frontends/dri/drisw.c index 7c6a75a228b..4c9b66cedfb 100644 --- a/src/gallium/frontends/dri/drisw.c +++ b/src/gallium/frontends/dri/drisw.c @@ -546,6 +546,8 @@ drisw_init_screen(struct dri_screen *screen) struct pipe_screen *pscreen = NULL; const struct drisw_loader_funcs *lf = &drisw_lf; + (void) mtx_init(&screen->opencl_func_mutex, mtx_plain); + screen->swrast_no_present = debug_get_option_swrast_no_present(); if (loader->base.version >= 4) { @@ -565,7 +567,7 @@ drisw_init_screen(struct dri_screen *screen) pscreen = pipe_loader_create_screen(screen->dev); if (!pscreen) - goto fail; + return NULL; dri_init_options(screen); configs = dri_init_screen(screen, pscreen); @@ -593,7 +595,7 @@ drisw_init_screen(struct dri_screen *screen) return configs; fail: - dri_release_screen(screen); + pipe_loader_release(&screen->dev, 1); return NULL; } diff --git a/src/gallium/frontends/dri/kopper.c b/src/gallium/frontends/dri/kopper.c index 61893e7012c..d247f2223c7 100644 --- a/src/gallium/frontends/dri/kopper.c +++ b/src/gallium/frontends/dri/kopper.c @@ -115,6 +115,8 @@ kopper_init_screen(struct dri_screen *screen) const __DRIconfig **configs; struct pipe_screen *pscreen = NULL; + (void) mtx_init(&screen->opencl_func_mutex, mtx_plain); + if (!screen->kopper_loader) { fprintf(stderr, "mesa: Kopper interface not found!\n" " Ensure the versions of %s built with this version of Zink are\n" @@ -134,7 +136,7 @@ kopper_init_screen(struct dri_screen *screen) pscreen = pipe_loader_create_screen(screen->dev); if (!pscreen) - goto fail; + return NULL; dri_init_options(screen); screen->unwrapped_screen = trace_screen_unwrap(pscreen); @@ -167,7 +169,7 @@ kopper_init_screen(struct dri_screen *screen) return configs; fail: - dri_release_screen(screen); + pipe_loader_release(&screen->dev, 1); return NULL; } diff --git a/src/gallium/frontends/rusticl/core/event.rs b/src/gallium/frontends/rusticl/core/event.rs index 6389d6de831..29b43fe30c7 100644 --- a/src/gallium/frontends/rusticl/core/event.rs +++ b/src/gallium/frontends/rusticl/core/event.rs @@ -10,6 +10,7 @@ use mesa_rust_util::static_assert; use rusticl_opencl_gen::*; use std::collections::HashSet; +use std::mem; use std::slice; use std::sync::Arc; use std::sync::Condvar; @@ -109,7 +110,7 @@ impl Event { self.state().status } - fn set_status(&self, lock: &mut MutexGuard, new: cl_int) { + fn set_status(&self, mut lock: MutexGuard, new: cl_int) { lock.status = new; // signal on completion or an error @@ -122,14 +123,17 @@ impl Event { if [CL_COMPLETE, CL_RUNNING, CL_SUBMITTED].contains(&cb_idx) { if let Some(cbs) = lock.cbs.get_mut(cb_idx as usize) { - cbs.drain(..).for_each(|cb| cb.call(self, new)); + let cbs = mem::take(cbs); + // applications might want to access the event in the callback, so drop the lock + // before calling into the callbacks. + drop(lock); + cbs.into_iter().for_each(|cb| cb.call(self, new)); } } } pub fn set_user_status(&self, status: cl_int) { - let mut lock = self.state(); - self.set_status(&mut lock, status); + self.set_status(self.state(), status); } pub fn is_error(&self) -> bool { @@ -175,10 +179,8 @@ impl Event { } pub(super) fn signal(&self) { - let mut lock = self.state(); - - self.set_status(&mut lock, CL_RUNNING as cl_int); - self.set_status(&mut lock, CL_COMPLETE as cl_int); + self.set_status(self.state(), CL_RUNNING as cl_int); + self.set_status(self.state(), CL_COMPLETE as cl_int); } pub fn wait(&self) -> cl_int { @@ -234,7 +236,7 @@ impl Event { lock.time_start = query_start.unwrap().read_blocked(); lock.time_end = query_end.unwrap().read_blocked(); } - self.set_status(&mut lock, new); + self.set_status(lock, new); } } @@ -272,6 +274,27 @@ impl Event { } } +impl Drop for Event { + // implement drop in order to prevent stack overflows of long dependency chains. + // + // This abuses the fact that `Arc::into_inner` only succeeds when there is one strong reference + // so we turn a recursive drop chain into a drop list for events having no other references. + fn drop(&mut self) { + if self.deps.is_empty() { + return; + } + + let mut deps_list = vec![mem::take(&mut self.deps)]; + while let Some(deps) = deps_list.pop() { + for dep in deps { + if let Some(mut dep) = Arc::into_inner(dep) { + deps_list.push(mem::take(&mut dep.deps)); + } + } + } + } +} + // TODO worker thread per device // Condvar to wait on new events to work on // notify condvar when flushing queue events to worker diff --git a/src/gallium/frontends/rusticl/mesa/pipe/context.rs b/src/gallium/frontends/rusticl/mesa/pipe/context.rs index b01e24ebf28..b2ff2cfeb2f 100644 --- a/src/gallium/frontends/rusticl/mesa/pipe/context.rs +++ b/src/gallium/frontends/rusticl/mesa/pipe/context.rs @@ -658,6 +658,7 @@ impl PipeContext { impl Drop for PipeContext { fn drop(&mut self) { + self.flush().wait(); unsafe { self.pipe.as_ref().destroy.unwrap()(self.pipe.as_ptr()); } diff --git a/src/gallium/frontends/va/buffer.c b/src/gallium/frontends/va/buffer.c index bbe0c75f23e..c11cead3802 100644 --- a/src/gallium/frontends/va/buffer.c +++ b/src/gallium/frontends/va/buffer.c @@ -316,7 +316,7 @@ vlVaDestroyBuffer(VADriverContextP ctx, VABufferID buf_id) if (buf->type == VAEncCodedBufferType) { VACodedBufferSegment* node = buf->data; - while(!node) { + while (node) { VACodedBufferSegment* next = (VACodedBufferSegment*) node->next; FREE(node); node = next; diff --git a/src/gallium/frontends/va/picture.c b/src/gallium/frontends/va/picture.c index 7bddd86db97..1a3cf42ff83 100644 --- a/src/gallium/frontends/va/picture.c +++ b/src/gallium/frontends/va/picture.c @@ -1033,7 +1033,8 @@ vlVaRenderPicture(VADriverContextP ctx, VAContextID context_id, VABufferID *buff case VASliceDataBufferType: vaStatus = handleVASliceDataBufferType(context, buf); - slice_offset += buf->size; + if (slice_idx) + slice_offset += buf->size; break; case VAProcPipelineParameterBufferType: diff --git a/src/gallium/frontends/va/picture_h264.c b/src/gallium/frontends/va/picture_h264.c index 62d94b51db5..f5e99fd795c 100644 --- a/src/gallium/frontends/va/picture_h264.c +++ b/src/gallium/frontends/va/picture_h264.c @@ -186,6 +186,7 @@ void vlVaHandleSliceParameterBufferH264(vlVaContext *context, vlVaBuffer *buf) assert(context->desc.h264.slice_count < max_pipe_h264_slices); context->desc.h264.slice_parameter.slice_info_present = true; + context->desc.h264.slice_parameter.slice_type[context->desc.h264.slice_count] = h264->slice_type; context->desc.h264.slice_parameter.slice_data_size[context->desc.h264.slice_count] = h264->slice_data_size; context->desc.h264.slice_parameter.slice_data_offset[context->desc.h264.slice_count] = h264->slice_data_offset; diff --git a/src/gallium/include/pipe/p_video_state.h b/src/gallium/include/pipe/p_video_state.h index ccebd5310f4..671823b37ae 100644 --- a/src/gallium/include/pipe/p_video_state.h +++ b/src/gallium/include/pipe/p_video_state.h @@ -411,6 +411,7 @@ struct pipe_h264_picture_desc { bool slice_info_present; uint32_t slice_count; + uint8_t slice_type[128]; uint32_t slice_data_size[128]; uint32_t slice_data_offset[128]; enum pipe_slice_buffer_placement_type slice_data_flag[128]; diff --git a/src/gallium/targets/d3dadapter9/meson.build b/src/gallium/targets/d3dadapter9/meson.build index 282859fd932..d5c75a7fb96 100644 --- a/src/gallium/targets/d3dadapter9/meson.build +++ b/src/gallium/targets/d3dadapter9/meson.build @@ -29,7 +29,7 @@ gallium_nine_link_depends = [] gallium_nine_link_with = [ libgallium, libnine_st, libpipe_loader_static, libws_null, libwsw, libswdri, - libswkmsdri, + libswkmsdri, libgalliumvl_stub, ] if with_ld_version_script @@ -37,13 +37,6 @@ if with_ld_version_script gallium_nine_link_depends += files('d3dadapter9.sym') endif -if (with_gallium_va or with_gallium_vdpau or with_gallium_omx != 'disabled' or - with_dri) - gallium_nine_link_with += libgalliumvl -else - gallium_nine_link_with += libgalliumvl_stub -endif - libgallium_nine = shared_library( 'd3dadapter9', files('description.c', 'getproc.c', 'drm.c'), diff --git a/src/gallium/targets/pipe-loader/meson.build b/src/gallium/targets/pipe-loader/meson.build index 943faec469d..48497fa9feb 100644 --- a/src/gallium/targets/pipe-loader/meson.build +++ b/src/gallium/targets/pipe-loader/meson.build @@ -20,19 +20,13 @@ pipe_loader_link_args = [ld_args_gc_sections, ld_args_build_id] pipe_loader_link_deps = [] -pipe_loader_link_with = [libgallium] +pipe_loader_link_with = [libgallium, libgalliumvl_stub] pipe_loader_comp_args = [] pipe_loader_incs = [ inc_include, inc_src, inc_util, inc_gallium, inc_gallium_drivers, inc_gallium_winsys, inc_gallium_aux, ] -if (with_gallium_va or with_gallium_vdpau or with_gallium_omx != 'disabled' or - with_dri or with_gallium_radeonsi) - pipe_loader_link_with += libgalliumvl -else - pipe_loader_link_with += libgalliumvl_stub -endif if (with_gallium_va or with_gallium_vdpau or with_gallium_omx != 'disabled') pipe_loader_link_with += libgalliumvlwinsys endif diff --git a/src/gallium/targets/rusticl/meson.build b/src/gallium/targets/rusticl/meson.build index b2963fe6dfa..e1acaca7e68 100644 --- a/src/gallium/targets/rusticl/meson.build +++ b/src/gallium/targets/rusticl/meson.build @@ -42,6 +42,7 @@ librusticl = shared_library( ], link_whole : librusticl, link_with : [ + libgalliumvl_stub, libpipe_loader_static, libswdri, libswkmsdri, diff --git a/src/gallium/winsys/i915/drm/meson.build b/src/gallium/winsys/i915/drm/meson.build index 57597972417..d68f74327ea 100644 --- a/src/gallium/winsys/i915/drm/meson.build +++ b/src/gallium/winsys/i915/drm/meson.build @@ -28,5 +28,5 @@ libi915drm = static_library( inc_include, inc_src, inc_gallium, inc_gallium_aux, inc_gallium_drivers ], link_with : [libintel_common], - dependencies : [dep_libdrm, dep_libdrm_intel], + dependencies : [dep_libdrm, dep_libdrm_intel, idep_intel_dev_wa], ) diff --git a/src/glx/drisw_glx.c b/src/glx/drisw_glx.c index cbba547d7eb..f9465c4a512 100644 --- a/src/glx/drisw_glx.c +++ b/src/glx/drisw_glx.c @@ -32,7 +32,9 @@ #include #include "dri_common.h" #include "drisw_priv.h" +#ifdef HAVE_DRI3 #include "dri3_priv.h" +#endif #include #include #include diff --git a/src/glx/glxext.c b/src/glx/glxext.c index fd53e00b4cc..31e85113abf 100644 --- a/src/glx/glxext.c +++ b/src/glx/glxext.c @@ -908,9 +908,11 @@ __glXInitialize(Display * dpy) #endif /* HAVE_DRI3 */ if (!debug_get_bool_option("LIBGL_DRI2_DISABLE", false)) dpyPriv->dri2Display = dri2CreateDisplay(dpy); +#if defined(HAVE_ZINK) if (!dpyPriv->dri3Display && !dpyPriv->dri2Display) try_zink = !debug_get_bool_option("LIBGL_KOPPER_DISABLE", false) && !getenv("GALLIUM_DRIVER"); +#endif /* HAVE_ZINK */ } #endif /* GLX_USE_DRM */ if (glx_direct) diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index 820ac0f4ef5..1a1ca11202d 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -779,6 +779,7 @@ enum opcode { SHADER_OPCODE_BTD_SPAWN_LOGICAL, SHADER_OPCODE_BTD_RETIRE_LOGICAL, + SHADER_OPCODE_READ_MASK_REG, SHADER_OPCODE_READ_SR_REG, RT_OPCODE_TRACE_RAY_LOGICAL, diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index adbbff41467..75339fb07fd 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -5752,7 +5752,6 @@ fs_visitor::lower_find_live_channel() * instruction has execution masking disabled, so it's kind of * useless there. */ - fs_reg exec_mask(retype(brw_mask_reg(0), BRW_REGISTER_TYPE_UD)); const fs_builder ibld(this, block, inst); if (!inst->is_partial_write()) @@ -5760,6 +5759,10 @@ fs_visitor::lower_find_live_channel() const fs_builder ubld = fs_builder(this, block, inst).exec_all().group(1, 0); + fs_reg exec_mask = ubld.vgrf(BRW_REGISTER_TYPE_UD); + ubld.UNDEF(exec_mask); + ubld.emit(SHADER_OPCODE_READ_MASK_REG, exec_mask, brw_imm_ud(0)); + /* ce0 doesn't consider the thread dispatch mask (DMask or VMask), * so combine the execution and dispatch masks to obtain the true mask. * diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 1c1391e0896..9f193728fbf 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -2324,6 +2324,26 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, brw_float_controls_mode(p, src[0].d, src[1].d); break; + case SHADER_OPCODE_READ_MASK_REG: + if (devinfo->ver >= 12) { + /* There is a SWSB restriction that requires that any time sr0 is + * accessed both the instruction doing the access and the next one + * have SWSB set to RegDist(1). + */ + if (brw_get_default_swsb(p).mode != TGL_SBID_NULL) + brw_SYNC(p, TGL_SYNC_NOP); + assert(src[0].file == BRW_IMMEDIATE_VALUE); + brw_set_default_swsb(p, tgl_swsb_regdist(1)); + brw_MOV(p, dst, retype(brw_mask_reg(src[0].ud), + BRW_REGISTER_TYPE_UD)); + brw_set_default_swsb(p, tgl_swsb_regdist(1)); + brw_AND(p, dst, dst, brw_imm_ud(0xffffffff)); + } else { + brw_MOV(p, dst, retype(brw_mask_reg(src[0].ud), + BRW_REGISTER_TYPE_UD)); + } + break; + case SHADER_OPCODE_READ_SR_REG: if (devinfo->ver >= 12) { /* There is a SWSB restriction that requires that any time sr0 is diff --git a/src/intel/compiler/brw_ir_performance.cpp b/src/intel/compiler/brw_ir_performance.cpp index 9ab7ef563b0..f14a3cc9716 100644 --- a/src/intel/compiler/brw_ir_performance.cpp +++ b/src/intel/compiler/brw_ir_performance.cpp @@ -363,6 +363,7 @@ namespace { case TCS_OPCODE_SRC0_010_IS_ZERO: case TCS_OPCODE_GET_PRIMITIVE_ID: case TES_OPCODE_GET_PRIMITIVE_ID: + case SHADER_OPCODE_READ_MASK_REG: case SHADER_OPCODE_READ_SR_REG: if (devinfo->ver >= 11) { return calculate_desc(info, EU_UNIT_FPU, 0, 2, 0, 0, 2, diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index c500f5e2b4f..e36389f724d 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -531,6 +531,8 @@ brw_instruction_name(const struct brw_isa_info *isa, enum opcode op) return "btd_spawn_logical"; case SHADER_OPCODE_BTD_RETIRE_LOGICAL: return "btd_retire_logical"; + case SHADER_OPCODE_READ_MASK_REG: + return "read_mask_reg"; case SHADER_OPCODE_READ_SR_REG: return "read_sr_reg"; } diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index c048b32a2f1..86b5f1ebcc1 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -3550,7 +3550,7 @@ VkResult anv_CreateDevice( if (result != VK_SUCCESS) goto fail_trtt; - struct vk_pipeline_cache_create_info pcc_info = { }; + struct vk_pipeline_cache_create_info pcc_info = { .weak_ref = true, }; device->default_pipeline_cache = vk_pipeline_cache_create(&device->vk, &pcc_info, NULL); if (!device->default_pipeline_cache) { @@ -3563,9 +3563,12 @@ VkResult anv_CreateDevice( * shaders to remain resident while it runs. Therefore, we need a special * cache just for BLORP/RT that's forced to always be enabled. */ - pcc_info.force_enable = true; + struct vk_pipeline_cache_create_info internal_pcc_info = { + .force_enable = true, + .weak_ref = false, + }; device->internal_cache = - vk_pipeline_cache_create(&device->vk, &pcc_info, NULL); + vk_pipeline_cache_create(&device->vk, &internal_pcc_info, NULL); if (device->internal_cache == NULL) { result = vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY); goto fail_default_pipeline_cache; diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c index 8d61c740cc0..44e0b7cb247 100644 --- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c +++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c @@ -743,7 +743,7 @@ build_desc_addr_for_res_index(nir_builder *b, static nir_def * build_desc_addr_for_binding(nir_builder *b, unsigned set, unsigned binding, - nir_def *array_index, + nir_def *array_index, unsigned plane, const struct apply_pipeline_layout_state *state) { const struct anv_descriptor_set_binding_layout *bind_layout = @@ -759,6 +759,10 @@ build_desc_addr_for_binding(nir_builder *b, array_index, bind_layout->descriptor_surface_stride), bind_layout->descriptor_surface_offset); + if (plane != 0) { + desc_offset = nir_iadd_imm( + b, desc_offset, plane * bind_layout->descriptor_data_surface_size); + } return nir_vec4(b, nir_unpack_64_2x32_split_x(b, set_addr), nir_unpack_64_2x32_split_y(b, set_addr), @@ -766,14 +770,21 @@ build_desc_addr_for_binding(nir_builder *b, desc_offset); } - case nir_address_format_32bit_index_offset: + case nir_address_format_32bit_index_offset: { + nir_def *desc_offset = + nir_iadd_imm(b, + nir_imul_imm(b, + array_index, + bind_layout->descriptor_surface_stride), + bind_layout->descriptor_surface_offset); + if (plane != 0) { + desc_offset = nir_iadd_imm( + b, desc_offset, plane * bind_layout->descriptor_data_surface_size); + } return nir_vec2(b, nir_imm_int(b, state->set[set].desc_offset), - nir_iadd_imm(b, - nir_imul_imm(b, - array_index, - bind_layout->descriptor_surface_stride), - bind_layout->descriptor_surface_offset)); + desc_offset); + } default: unreachable("Unhandled address format"); @@ -827,7 +838,8 @@ build_surface_index_for_binding(nir_builder *b, set_offset = nir_imm_int(b, 0xdeaddead); nir_def *desc_addr = - build_desc_addr_for_binding(b, set, binding, array_index, state); + build_desc_addr_for_binding(b, set, binding, array_index, + plane, state); surface_index = build_load_descriptor_mem(b, desc_addr, 0, 1, 32, state); @@ -908,7 +920,8 @@ build_sampler_handle_for_binding(nir_builder *b, set_offset = nir_imm_int(b, 0xdeaddead); nir_def *desc_addr = - build_desc_addr_for_binding(b, set, binding, array_index, state); + build_desc_addr_for_binding(b, set, binding, array_index, + plane, state); /* This is anv_sampled_image_descriptor, the sampler handle is always * in component 1. @@ -1384,7 +1397,8 @@ lower_load_accel_struct_desc(nir_builder *b, struct res_index_defs res = unpack_res_index(b, res_index); nir_def *desc_addr = - build_desc_addr_for_binding(b, set, binding, res.array_index, state); + build_desc_addr_for_binding(b, set, binding, res.array_index, + 0 /* plane */, state); /* Acceleration structure descriptors are always uint64_t */ nir_def *desc = build_load_descriptor_mem(b, desc_addr, 0, 1, 64, state); @@ -1613,7 +1627,7 @@ lower_image_size_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin, } nir_def *desc_addr = build_desc_addr_for_binding( - b, set, binding, array_index, state); + b, set, binding, array_index, 0 /* plane */, state); b->cursor = nir_after_instr(&intrin->instr); diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 7d3c974254e..4fcbe1e1604 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -839,7 +839,7 @@ anv_pipeline_hash_ray_tracing_combined_shader(struct anv_ray_tracing_pipeline *p _mesa_sha1_final(&ctx, sha1_out); } -static nir_shader * +static VkResult anv_pipeline_stage_get_nir(struct anv_pipeline *pipeline, struct vk_pipeline_cache *cache, void *mem_ctx, @@ -849,25 +849,35 @@ anv_pipeline_stage_get_nir(struct anv_pipeline *pipeline, pipeline->device->physical->compiler; const nir_shader_compiler_options *nir_options = compiler->nir_options[stage->stage]; - nir_shader *nir; - nir = anv_device_search_for_nir(pipeline->device, cache, - nir_options, - stage->shader_sha1, - mem_ctx); - if (nir) { - assert(nir->info.stage == stage->stage); - return nir; + stage->nir = anv_device_search_for_nir(pipeline->device, cache, + nir_options, + stage->shader_sha1, + mem_ctx); + if (stage->nir) { + assert(stage->nir->info.stage == stage->stage); + return VK_SUCCESS; } - nir = anv_shader_stage_to_nir(pipeline->device, stage->info, - stage->key.base.robust_flags, mem_ctx); - if (nir) { - anv_device_upload_nir(pipeline->device, cache, nir, stage->shader_sha1); - return nir; + /* VkPipelineShaderStageCreateInfo: + * + * "If a pipeline is not found, pipeline compilation is not possible and + * the implementation must fail as specified by + * VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT." + */ + if (vk_pipeline_shader_stage_has_identifier(stage->info)) + return VK_PIPELINE_COMPILE_REQUIRED; + + stage->nir = anv_shader_stage_to_nir(pipeline->device, stage->info, + stage->key.base.robust_flags, mem_ctx); + if (stage->nir) { + anv_device_upload_nir(pipeline->device, cache, + stage->nir, stage->shader_sha1); + return VK_SUCCESS; } - return NULL; + return vk_errorf(&pipeline->device->vk, VK_ERROR_UNKNOWN, + "Unable to load NIR"); } static const struct vk_ycbcr_conversion_state * @@ -2014,10 +2024,10 @@ anv_graphics_pipeline_load_nir(struct anv_graphics_base_pipeline *pipeline, * an imported library for the same stage. */ if (stages[s].imported.bin == NULL) { - stages[s].nir = anv_pipeline_stage_get_nir(&pipeline->base, cache, - mem_ctx, &stages[s]); - if (stages[s].nir == NULL) - return vk_error(pipeline, VK_ERROR_UNKNOWN); + VkResult result = anv_pipeline_stage_get_nir(&pipeline->base, cache, + mem_ctx, &stages[s]); + if (result != VK_SUCCESS) + return result; } else { stages[s].nir = need_clone ? nir_shader_clone(mem_ctx, stages[s].imported.nir) : @@ -2220,9 +2230,9 @@ anv_graphics_pipeline_compile(struct anv_graphics_base_pipeline *pipeline, vk_perf(VK_LOG_OBJS(cache ? &cache->base : &pipeline->base.device->vk.base), "Found all ISA shaders in the cache but not all NIR shaders."); + } else { + anv_graphics_lib_retain_shaders(pipeline, stages, false /* will_compile */); } - - anv_graphics_lib_retain_shaders(pipeline, stages, false /* will_compile */); } if (result == VK_SUCCESS) @@ -2621,10 +2631,11 @@ anv_pipeline_compile_cs(struct anv_compute_pipeline *pipeline, .binding = UINT32_MAX, }; - stage.nir = anv_pipeline_stage_get_nir(&pipeline->base, cache, mem_ctx, &stage); - if (stage.nir == NULL) { + VkResult result = anv_pipeline_stage_get_nir(&pipeline->base, cache, + mem_ctx, &stage); + if (result != VK_SUCCESS) { ralloc_free(mem_ctx); - return vk_error(pipeline, VK_ERROR_UNKNOWN); + return result; } anv_pipeline_nir_preprocess(&pipeline->base, &stage); @@ -2781,20 +2792,12 @@ VkResult anv_CreateComputePipelines( &pCreateInfos[i], pAllocator, &pPipelines[i]); - if (res == VK_SUCCESS) - continue; - - /* Bail out on the first error != VK_PIPELINE_COMPILE_REQUIRED as it - * is not obvious what error should be report upon 2 different failures. - * */ - result = res; - if (res != VK_PIPELINE_COMPILE_REQUIRED) - break; - - pPipelines[i] = VK_NULL_HANDLE; - - if (flags & VK_PIPELINE_CREATE_2_EARLY_RETURN_ON_FAILURE_BIT_KHR) - break; + if (res != VK_SUCCESS) { + result = res; + if (flags & VK_PIPELINE_CREATE_2_EARLY_RETURN_ON_FAILURE_BIT_KHR) + break; + pPipelines[i] = VK_NULL_HANDLE; + } } for (; i < count; i++) @@ -3317,20 +3320,12 @@ VkResult anv_CreateGraphicsPipelines( pAllocator, &pPipelines[i]); } - if (res == VK_SUCCESS) - continue; - - /* Bail out on the first error != VK_PIPELINE_COMPILE_REQUIRED as it - * is not obvious what error should be report upon 2 different failures. - * */ - result = res; - if (res != VK_PIPELINE_COMPILE_REQUIRED) - break; - - pPipelines[i] = VK_NULL_HANDLE; - - if (flags & VK_PIPELINE_CREATE_2_EARLY_RETURN_ON_FAILURE_BIT_KHR) - break; + if (res != VK_SUCCESS) { + result = res; + if (flags & VK_PIPELINE_CREATE_2_EARLY_RETURN_ON_FAILURE_BIT_KHR) + break; + pPipelines[i] = VK_NULL_HANDLE; + } } for (; i < count; i++) @@ -3649,10 +3644,11 @@ anv_pipeline_compile_ray_tracing(struct anv_ray_tracing_pipeline *pipeline, int64_t stage_start = os_time_get_nano(); - stages[i].nir = anv_pipeline_stage_get_nir(&pipeline->base, cache, - tmp_pipeline_ctx, &stages[i]); - if (stages[i].nir == NULL) - return vk_error(pipeline, VK_ERROR_OUT_OF_HOST_MEMORY); + VkResult result = anv_pipeline_stage_get_nir(&pipeline->base, cache, + tmp_pipeline_ctx, + &stages[i]); + if (result != VK_SUCCESS) + return result; anv_pipeline_nir_preprocess(&pipeline->base, &stages[i]); @@ -4154,19 +4150,12 @@ anv_CreateRayTracingPipelinesKHR( &pCreateInfos[i], pAllocator, &pPipelines[i]); - if (res == VK_SUCCESS) - continue; - - /* Bail out on the first error as it is not obvious what error should be - * report upon 2 different failures. */ - result = res; - if (result != VK_PIPELINE_COMPILE_REQUIRED) - break; - - pPipelines[i] = VK_NULL_HANDLE; - - if (flags & VK_PIPELINE_CREATE_2_EARLY_RETURN_ON_FAILURE_BIT_KHR) - break; + if (res != VK_SUCCESS) { + result = res; + if (flags & VK_PIPELINE_CREATE_2_EARLY_RETURN_ON_FAILURE_BIT_KHR) + break; + pPipelines[i] = VK_NULL_HANDLE; + } } for (; i < createInfoCount; i++) diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index cb87ebe5f80..251919c2efd 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -1667,6 +1667,10 @@ struct anv_device { struct anv_bo_pool batch_bo_pool; /** Memory pool for utrace timestamp buffers */ struct anv_bo_pool utrace_bo_pool; + /** + * Size of the timestamp captured for utrace. + */ + uint32_t utrace_timestamp_size; /** Memory pool for BVH build buffers */ struct anv_bo_pool bvh_bo_pool; @@ -3180,6 +3184,12 @@ struct anv_push_constants { /** Dynamic offsets for dynamic UBOs and SSBOs */ uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS]; + /* Robust access pushed registers. */ + uint64_t push_reg_mask[MESA_SHADER_STAGES]; + + /** Ray query globals (RT_DISPATCH_GLOBALS) */ + uint64_t ray_query_globals; + union { struct { /** Dynamic MSAA value */ @@ -3200,16 +3210,12 @@ struct anv_push_constants { * * This is never set by software but is implicitly filled out when * uploading the push constants for compute shaders. + * + * This *MUST* be the last field of the anv_push_constants structure. */ uint32_t subgroup_id; } cs; }; - - /* Robust access pushed registers. */ - uint64_t push_reg_mask[MESA_SHADER_STAGES]; - - /** Ray query globals (RT_DISPATCH_GLOBALS) */ - uint64_t ray_query_globals; }; struct anv_surface_state { diff --git a/src/intel/vulkan/anv_utrace.c b/src/intel/vulkan/anv_utrace.c index 56d445958a8..b5b20182a12 100644 --- a/src/intel/vulkan/anv_utrace.c +++ b/src/intel/vulkan/anv_utrace.c @@ -49,7 +49,7 @@ union anv_utrace_timestamp { * [2] = 32b Context Timestamp End * [3] = 32b Global Timestamp End" */ - uint32_t compute_walker[4]; + uint32_t compute_walker[8]; }; static uint32_t @@ -499,6 +499,8 @@ anv_device_utrace_init(struct anv_device *device) intel_engines_class_to_string(queue->family->engine_class), queue->vk.index_in_family); } + + device->utrace_timestamp_size = sizeof(union anv_utrace_timestamp); } void diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c index 342b197c6f1..c099a8dedfe 100644 --- a/src/intel/vulkan/genX_blorp_exec.c +++ b/src/intel/vulkan/genX_blorp_exec.c @@ -429,7 +429,7 @@ blorp_exec_on_blitter(struct blorp_batch *batch, assert(batch->flags & BLORP_BATCH_USE_BLITTER); struct anv_cmd_buffer *cmd_buffer = batch->driver_batch; - assert(cmd_buffer->queue_family->queueFlags == VK_QUEUE_TRANSFER_BIT); + assert(anv_cmd_buffer_is_blitter_queue(cmd_buffer)); blorp_exec(batch, params); } diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 65c503aadd9..e799b6df39b 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -3713,14 +3713,16 @@ cmd_buffer_emit_copy_ts_buffer(struct u_trace_context *utctx, void *ts_to, uint32_t to_offset, uint32_t count) { + struct anv_device *device = + container_of(utctx, struct anv_device, ds.trace_context); struct anv_memcpy_state *memcpy_state = cmdstream; struct anv_address from_addr = (struct anv_address) { - .bo = ts_from, .offset = from_offset * sizeof(uint64_t) }; + .bo = ts_from, .offset = from_offset * device->utrace_timestamp_size }; struct anv_address to_addr = (struct anv_address) { - .bo = ts_to, .offset = to_offset * sizeof(uint64_t) }; + .bo = ts_to, .offset = to_offset * device->utrace_timestamp_size }; genX(emit_so_memcpy)(memcpy_state, to_addr, from_addr, - count * sizeof(uint64_t)); + count * device->utrace_timestamp_size); } void diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c index e4f10721d28..b6bc348b5e2 100644 --- a/src/intel/vulkan/genX_query.c +++ b/src/intel/vulkan/genX_query.c @@ -554,7 +554,8 @@ VkResult genX(GetQueryPoolResults)( while (statistics) { UNUSED uint32_t stat = u_bit_scan(&statistics); if (write_results) { - uint64_t result = slot[idx * 2 + 2] - slot[idx * 2 + 1]; + /* If a query is not available but VK_QUERY_RESULT_PARTIAL_BIT is set, write 0. */ + uint64_t result = available ? slot[idx * 2 + 2] - slot[idx * 2 + 1] : 0; cpu_write_query_result(pData, flags, idx, result); } idx++; @@ -565,11 +566,17 @@ VkResult genX(GetQueryPoolResults)( case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT: { uint64_t *slot = query_slot(pool, firstQuery + i); - if (write_results) - cpu_write_query_result(pData, flags, idx, slot[2] - slot[1]); + if (write_results) { + /* If a query is not available but VK_QUERY_RESULT_PARTIAL_BIT is set, write 0. */ + uint64_t result = available ? slot[2] - slot[1] : 0; + cpu_write_query_result(pData, flags, idx, result); + } idx++; - if (write_results) - cpu_write_query_result(pData, flags, idx, slot[4] - slot[3]); + if (write_results) { + /* If a query is not available but VK_QUERY_RESULT_PARTIAL_BIT is set, write 0. */ + uint64_t result = available ? slot[4] - slot[3] : 0; + cpu_write_query_result(pData, flags, idx, result); + } idx++; break; } diff --git a/src/intel/vulkan/layers/anv_android_layer.c b/src/intel/vulkan/layers/anv_android_layer.c index e36eb820ab6..4a7d0dd7170 100644 --- a/src/intel/vulkan/layers/anv_android_layer.c +++ b/src/intel/vulkan/layers/anv_android_layer.c @@ -38,7 +38,8 @@ android_CreateImageView(VkDevice _device, * format. */ if (fmt && fmt->layout == UTIL_FORMAT_LAYOUT_ASTC && - device->info->verx10 >= 125) { + device->info->verx10 >= 125 && + !(device->physical->has_astc_ldr || device->physical->emu_astc_ldr)) { return vk_errorf(device, VK_ERROR_OUT_OF_HOST_MEMORY, "ASTC format not supported (%s).", __func__); } diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c index 962cd7c5334..281c3ee2bd5 100644 --- a/src/mesa/main/framebuffer.c +++ b/src/mesa/main/framebuffer.c @@ -972,13 +972,36 @@ _mesa_get_color_read_type(struct gl_context *ctx, GLenum data_type; GLuint comps; - _mesa_uncompressed_format_to_type_and_comps(format, &data_type, &comps); - + _mesa_uncompressed_format_to_type_and_comps(format, &data_type, + &comps); + if (_mesa_is_gles(ctx)) { + /* GLES allows only a limited set of format/type combinations for + reading, namely the ones specified in table 8.2 of the GLES 3.2 + spec. In particular *_REV types are not allowed. The + EXT_read_format_bgra extension does add some *_REV types, but + only in conjunction with BGRA formats, and we return BGRA + from _mesa_get_color_read_format for very few cases. Work + around that here. + Note that EXT_texture_type_2_10_10_10_REV does add support + for that texture type and RGBA, so exclude that from our test. + */ + GLenum data_format = _mesa_get_color_read_format(ctx, fb, caller); + if (data_format == GL_RGBA) { + switch (data_type) { + case GL_UNSIGNED_SHORT_4_4_4_4_REV: + data_type = GL_UNSIGNED_SHORT_4_4_4_4; + break; + case GL_UNSIGNED_SHORT_1_5_5_5_REV: + data_type = GL_UNSIGNED_SHORT_5_5_5_1; + break; + default: + break; + } + } + } return data_type; } } - - /** * Returns the read renderbuffer for the specified format. */ diff --git a/src/nouveau/vulkan/nvk_cmd_draw.c b/src/nouveau/vulkan/nvk_cmd_draw.c index f0380b46790..d8e4e625f7e 100644 --- a/src/nouveau/vulkan/nvk_cmd_draw.c +++ b/src/nouveau/vulkan/nvk_cmd_draw.c @@ -1438,13 +1438,15 @@ nvk_flush_ms_state(struct nvk_cmd_buffer *cmd) }); } - if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_SAMPLE_LOCATIONS) || + if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES) || + BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_SAMPLE_LOCATIONS) || BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_SAMPLE_LOCATIONS_ENABLE)) { const struct vk_sample_locations_state *sl; if (dyn->ms.sample_locations_enable) { sl = dyn->ms.sample_locations; } else { - sl = vk_standard_sample_locations_state(dyn->ms.rasterization_samples); + const uint32_t samples = MAX2(1, dyn->ms.rasterization_samples); + sl = vk_standard_sample_locations_state(samples); } for (uint32_t i = 0; i < sl->per_pixel; i++) { diff --git a/src/nouveau/vulkan/nvk_cmd_meta.c b/src/nouveau/vulkan/nvk_cmd_meta.c index 39135ae5967..bb354901222 100644 --- a/src/nouveau/vulkan/nvk_cmd_meta.c +++ b/src/nouveau/vulkan/nvk_cmd_meta.c @@ -130,6 +130,7 @@ nvk_meta_end(struct nvk_cmd_buffer *cmd, { if (save->desc0) { cmd->state.gfx.descriptors.sets[0] = save->desc0; + cmd->state.gfx.descriptors.set_sizes[0] = save->desc0->size; cmd->state.gfx.descriptors.root.sets[0] = nvk_descriptor_set_addr(save->desc0); cmd->state.gfx.descriptors.sets_dirty |= BITFIELD_BIT(0); cmd->state.gfx.descriptors.push_dirty &= ~BITFIELD_BIT(0); diff --git a/src/nouveau/winsys/nouveau_bo.c b/src/nouveau/winsys/nouveau_bo.c index 6ee022b14a3..591070de20d 100644 --- a/src/nouveau/winsys/nouveau_bo.c +++ b/src/nouveau/winsys/nouveau_bo.c @@ -10,6 +10,9 @@ #include #include +#include "nvidia/classes/cl9097.h" +#include "nvidia/classes/clc597.h" + static void bo_bind(struct nouveau_ws_device *dev, uint32_t handle, uint64_t addr, @@ -170,9 +173,10 @@ nouveau_ws_bo_new_mapped(struct nouveau_ws_device *dev, } static struct nouveau_ws_bo * -nouveau_ws_bo_new_locked(struct nouveau_ws_device *dev, - uint64_t size, uint64_t align, - enum nouveau_ws_bo_flags flags) +nouveau_ws_bo_new_tiled_locked(struct nouveau_ws_device *dev, + uint64_t size, uint64_t align, + uint8_t pte_kind, uint16_t tile_mode, + enum nouveau_ws_bo_flags flags) { struct drm_nouveau_gem_new req = {}; @@ -205,6 +209,9 @@ nouveau_ws_bo_new_locked(struct nouveau_ws_device *dev, if (flags & NOUVEAU_WS_BO_NO_SHARE) req.info.domain |= NOUVEAU_GEM_DOMAIN_NO_SHARE; + req.info.tile_flags = (uint32_t)pte_kind << 8; + req.info.tile_mode = tile_mode; + req.info.size = size; req.align = align; @@ -242,19 +249,29 @@ nouveau_ws_bo_new_locked(struct nouveau_ws_device *dev, } struct nouveau_ws_bo * -nouveau_ws_bo_new(struct nouveau_ws_device *dev, - uint64_t size, uint64_t align, - enum nouveau_ws_bo_flags flags) +nouveau_ws_bo_new_tiled(struct nouveau_ws_device *dev, + uint64_t size, uint64_t align, + uint8_t pte_kind, uint16_t tile_mode, + enum nouveau_ws_bo_flags flags) { struct nouveau_ws_bo *bo; simple_mtx_lock(&dev->bos_lock); - bo = nouveau_ws_bo_new_locked(dev, size, align, flags); + bo = nouveau_ws_bo_new_tiled_locked(dev, size, align, + pte_kind, tile_mode, flags); simple_mtx_unlock(&dev->bos_lock); return bo; } +struct nouveau_ws_bo * +nouveau_ws_bo_new(struct nouveau_ws_device *dev, + uint64_t size, uint64_t align, + enum nouveau_ws_bo_flags flags) +{ + return nouveau_ws_bo_new_tiled(dev, size, align, 0, 0, flags); +} + static struct nouveau_ws_bo * nouveau_ws_bo_from_dma_buf_locked(struct nouveau_ws_device *dev, int fd) { @@ -265,8 +282,11 @@ nouveau_ws_bo_from_dma_buf_locked(struct nouveau_ws_device *dev, int fd) struct hash_entry *entry = _mesa_hash_table_search(dev->bos, (void *)(uintptr_t)handle); - if (entry != NULL) - return entry->data; + if (entry != NULL) { + struct nouveau_ws_bo *bo = entry->data; + nouveau_ws_bo_ref(bo); + return bo; + } /* * If we got here, no BO exists for the retrieved handle. If we error diff --git a/src/nouveau/winsys/nouveau_bo.h b/src/nouveau/winsys/nouveau_bo.h index d931bea44f9..14bd87a10cc 100644 --- a/src/nouveau/winsys/nouveau_bo.h +++ b/src/nouveau/winsys/nouveau_bo.h @@ -68,6 +68,11 @@ struct nouveau_ws_bo *nouveau_ws_bo_new_mapped(struct nouveau_ws_device *, enum nouveau_ws_bo_flags, enum nouveau_ws_bo_map_flags map_flags, void **map_out); +struct nouveau_ws_bo *nouveau_ws_bo_new_tiled(struct nouveau_ws_device *, + uint64_t size, uint64_t align, + uint8_t pte_kind, + uint16_t tile_mode, + enum nouveau_ws_bo_flags); struct nouveau_ws_bo *nouveau_ws_bo_from_dma_buf(struct nouveau_ws_device *, int fd); void nouveau_ws_bo_destroy(struct nouveau_ws_bo *); diff --git a/src/nouveau/winsys/nouveau_device.c b/src/nouveau/winsys/nouveau_device.c index 5e0f0f9c94c..f1e0a3494c0 100644 --- a/src/nouveau/winsys/nouveau_device.c +++ b/src/nouveau/winsys/nouveau_device.c @@ -380,3 +380,13 @@ nouveau_ws_device_destroy(struct nouveau_ws_device *device) close(device->fd); FREE(device); } + +bool +nouveau_ws_device_has_tiled_bo(struct nouveau_ws_device *device) +{ + uint64_t has = 0; + if (nouveau_ws_param(device->fd, NOUVEAU_GETPARAM_HAS_VMA_TILEMODE, &has)) + return false; + + return has != 0; +} diff --git a/src/nouveau/winsys/nouveau_device.h b/src/nouveau/winsys/nouveau_device.h index 413a2e827e1..0f4eb0cc71a 100644 --- a/src/nouveau/winsys/nouveau_device.h +++ b/src/nouveau/winsys/nouveau_device.h @@ -64,6 +64,8 @@ struct nouveau_ws_device { struct nouveau_ws_device *nouveau_ws_device_new(struct _drmDevice *drm_device); void nouveau_ws_device_destroy(struct nouveau_ws_device *); +bool nouveau_ws_device_has_tiled_bo(struct nouveau_ws_device *device); + #ifdef __cplusplus } #endif diff --git a/src/panfrost/ci/gitlab-ci.yml b/src/panfrost/ci/gitlab-ci.yml index a2f15d22552..4faf3f2fe26 100644 --- a/src/panfrost/ci/gitlab-ci.yml +++ b/src/panfrost/ci/gitlab-ci.yml @@ -17,6 +17,7 @@ - src/panfrost/ci/$PIGLIT_TRACES_FILE - src/panfrost/include/* - src/panfrost/lib/* + - src/panfrost/lib/genxml/* - src/panfrost/lib/kmod/* - src/panfrost/shared/* - src/panfrost/util/* diff --git a/src/panfrost/ci/panfrost-g52-fails.txt b/src/panfrost/ci/panfrost-g52-fails.txt index 77215b7deda..1081f02dbec 100644 --- a/src/panfrost/ci/panfrost-g52-fails.txt +++ b/src/panfrost/ci/panfrost-g52-fails.txt @@ -101,7 +101,6 @@ spec@arb_texture_multisample@arb_texture_multisample-dsa-texelfetch@Texture type spec@arb_texture_multisample@arb_texture_multisample-dsa-texelfetch@Texture type: GL_RGBA8,Fail spec@arb_texture_multisample@arb_texture_multisample-dsa-texelfetch@Texture type: GL_RGBA8I,Fail spec@arb_texture_multisample@arb_texture_multisample-dsa-texelfetch@Texture type: GL_SRGB8_ALPHA8,Fail -spec@arb_texture_rectangle@1-1-linear-texture,Fail spec@arb_texture_rectangle@tex-miplevel-selection gl2:texture() 2drect,Crash spec@arb_texture_rectangle@tex-miplevel-selection gl2:texture() 2drectshadow,Crash spec@arb_texture_rectangle@tex-miplevel-selection gl2:textureproj 2drect,Crash diff --git a/src/panfrost/compiler/valhall/va_insert_flow.c b/src/panfrost/compiler/valhall/va_insert_flow.c index 5cbe6a13ad6..00560c60b31 100644 --- a/src/panfrost/compiler/valhall/va_insert_flow.c +++ b/src/panfrost/compiler/valhall/va_insert_flow.c @@ -115,9 +115,16 @@ bi_ld_vary_writes_hidden_register(const bi_instr *I) static bool bi_is_memory_access(const bi_instr *I) { - /* On the attribute unit but functionally a general memory load */ - if (I->op == BI_OPCODE_LD_ATTR_TEX) + /* Some instructions on the attribute unit are functionally + a general memory load */ + switch (I->op) { + case BI_OPCODE_LD_ATTR_TEX: + case BI_OPCODE_LD_TEX: + case BI_OPCODE_LD_TEX_IMM: return true; + default: + break; + } /* UBOs are read-only so there are no ordering constriants */ if (I->seg == BI_SEG_UBO) diff --git a/src/panfrost/lib/genxml/v10.xml b/src/panfrost/lib/genxml/v10.xml index 249aaff7850..6d5cb5e244a 100644 --- a/src/panfrost/lib/genxml/v10.xml +++ b/src/panfrost/lib/genxml/v10.xml @@ -969,7 +969,7 @@ - + diff --git a/src/panfrost/lib/genxml/v6.xml b/src/panfrost/lib/genxml/v6.xml index 9d042c4db93..86622677991 100644 --- a/src/panfrost/lib/genxml/v6.xml +++ b/src/panfrost/lib/genxml/v6.xml @@ -632,7 +632,7 @@ - + diff --git a/src/panfrost/lib/genxml/v7.xml b/src/panfrost/lib/genxml/v7.xml index 7e0b794ec85..da560d2733a 100644 --- a/src/panfrost/lib/genxml/v7.xml +++ b/src/panfrost/lib/genxml/v7.xml @@ -696,7 +696,7 @@ - + diff --git a/src/panfrost/lib/genxml/v9.xml b/src/panfrost/lib/genxml/v9.xml index c08d49e2025..961f38badfa 100644 --- a/src/panfrost/lib/genxml/v9.xml +++ b/src/panfrost/lib/genxml/v9.xml @@ -623,7 +623,7 @@ - + diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c index 2864b3195bc..631bc1e6cbc 100644 --- a/src/panfrost/midgard/midgard_compile.c +++ b/src/panfrost/midgard/midgard_compile.c @@ -1263,12 +1263,32 @@ emit_varying_read(compiler_context *ctx, unsigned dest, unsigned offset, ins.load_store.arg_reg = REGISTER_LDST_ZERO; ins.load_store.index_format = midgard_index_address_u32; - /* For flat shading, we always use .u32 and require 32-bit mode. For - * smooth shading, we use the appropriate floating-point type. + /* For flat shading, for GPUs supporting auto32, we always use .u32 and + * require 32-bit mode. For smooth shading, we use the appropriate + * floating-point type. * * This could be optimized, but it makes it easy to check correctness. */ - if (flat) { + if (ctx->quirks & MIDGARD_NO_AUTO32) { + switch (type) { + case nir_type_uint32: + case nir_type_bool32: + ins.op = midgard_op_ld_vary_32u; + break; + case nir_type_int32: + ins.op = midgard_op_ld_vary_32i; + break; + case nir_type_float32: + ins.op = midgard_op_ld_vary_32; + break; + case nir_type_float16: + ins.op = midgard_op_ld_vary_16; + break; + default: + unreachable("Attempted to load unknown type"); + break; + } + } else if (flat) { assert(nir_alu_type_get_type_size(type) == 32); ins.op = midgard_op_ld_vary_32u; } else { @@ -2896,6 +2916,7 @@ midgard_compile_shader_nir(nir_shader *nir, ctx->ssa_constants = _mesa_hash_table_u64_create(ctx); /* Collect varyings after lowering I/O */ + info->quirk_no_auto32 = (ctx->quirks & MIDGARD_NO_AUTO32); pan_nir_collect_varyings(nir, info); /* Optimisation passes */ diff --git a/src/panfrost/midgard/midgard_quirks.h b/src/panfrost/midgard/midgard_quirks.h index 3003dbdf7c2..fd7f797e04b 100644 --- a/src/panfrost/midgard/midgard_quirks.h +++ b/src/panfrost/midgard/midgard_quirks.h @@ -66,11 +66,19 @@ #define MIDGARD_NO_OOO (1 << 5) +/* Disable auto32 type (apparently broken on T60x). */ + +#define MIDGARD_NO_AUTO32 (1 << 6) + static inline unsigned midgard_get_quirks(unsigned gpu_id) { switch (gpu_id) { case 0x600: + return MIDGARD_OLD_BLEND | MIDGARD_BROKEN_BLEND_LOADS | + MIDGARD_BROKEN_LOD | MIDGARD_NO_UPPER_ALU | MIDGARD_NO_OOO | + MIDGARD_NO_AUTO32; + case 0x620: return MIDGARD_OLD_BLEND | MIDGARD_BROKEN_BLEND_LOADS | MIDGARD_BROKEN_LOD | MIDGARD_NO_UPPER_ALU | MIDGARD_NO_OOO; diff --git a/src/panfrost/util/pan_collect_varyings.c b/src/panfrost/util/pan_collect_varyings.c index b5cc72c51ab..b69e255290a 100644 --- a/src/panfrost/util/pan_collect_varyings.c +++ b/src/panfrost/util/pan_collect_varyings.c @@ -67,10 +67,17 @@ struct slot_info { unsigned index; }; +struct walk_varyings_data { + struct pan_shader_info *info; + struct slot_info *slots; +}; + static bool walk_varyings(UNUSED nir_builder *b, nir_instr *instr, void *data) { - struct slot_info *slots = data; + struct walk_varyings_data *wv_data = data; + struct pan_shader_info *info = wv_data->info; + struct slot_info *slots = wv_data->slots; if (instr->type != nir_instr_type_intrinsic) return false; @@ -113,8 +120,9 @@ walk_varyings(UNUSED nir_builder *b, nir_instr *instr, void *data) * only to determine the type, and the GL linker uses the type from the * fragment shader instead. */ - bool flat = (intr->intrinsic != nir_intrinsic_load_interpolated_input); - nir_alu_type type = flat ? nir_type_uint : nir_type_float; + bool flat = intr->intrinsic != nir_intrinsic_load_interpolated_input; + bool auto32 = !info->quirk_no_auto32; + nir_alu_type type = (flat && auto32) ? nir_type_uint : nir_type_float; /* Demote interpolated float varyings to fp16 where possible. We do not * demote flat varyings, including integer varyings, due to various @@ -161,7 +169,8 @@ pan_nir_collect_varyings(nir_shader *s, struct pan_shader_info *info) return; struct slot_info slots[64] = {0}; - nir_shader_instructions_pass(s, walk_varyings, nir_metadata_all, slots); + struct walk_varyings_data wv_data = {info, slots}; + nir_shader_instructions_pass(s, walk_varyings, nir_metadata_all, &wv_data); struct pan_shader_varying *varyings = (s->info.stage == MESA_SHADER_VERTEX) ? info->varyings.output diff --git a/src/panfrost/util/pan_ir.h b/src/panfrost/util/pan_ir.h index 5551fc7526a..46d1a530a3e 100644 --- a/src/panfrost/util/pan_ir.h +++ b/src/panfrost/util/pan_ir.h @@ -307,6 +307,9 @@ struct pan_shader_info { uint32_t ubo_mask; + /* Quirk for GPUs that does not support auto32 types. */ + bool quirk_no_auto32; + union { struct bifrost_shader_info bifrost; struct midgard_shader_info midgard; diff --git a/src/util/00-radv-defaults.conf b/src/util/00-radv-defaults.conf index 3fa2d074ff5..648484edcc5 100644 --- a/src/util/00-radv-defaults.conf +++ b/src/util/00-radv-defaults.conf @@ -208,5 +208,9 @@ Application bugs worked around in this file: + + + diff --git a/src/util/bitset.h b/src/util/bitset.h index cffbb73ecce..d5abb6c1f7c 100644 --- a/src/util/bitset.h +++ b/src/util/bitset.h @@ -209,7 +209,8 @@ __bitset_shl(BITSET_WORD *x, unsigned amount, unsigned n) */ #define BITSET_TEST_RANGE_INSIDE_WORD(x, b, e, mask) \ (BITSET_BITWORD(b) == BITSET_BITWORD(e) ? \ - (((x)[BITSET_BITWORD(b)] & BITSET_RANGE(b, e)) == mask) : \ + (((x)[BITSET_BITWORD(b)] & BITSET_RANGE(b, e)) == \ + (((BITSET_WORD)mask) << (b % BITSET_WORDBITS))) : \ (assert (!"BITSET_TEST_RANGE: bit range crosses word boundary"), 0)) #define BITSET_SET_RANGE_INSIDE_WORD(x, b, e) \ (BITSET_BITWORD(b) == BITSET_BITWORD(e) ? \ diff --git a/src/vulkan/runtime/vk_pipeline.c b/src/vulkan/runtime/vk_pipeline.c index 50a87e13a3c..8a6bf431446 100644 --- a/src/vulkan/runtime/vk_pipeline.c +++ b/src/vulkan/runtime/vk_pipeline.c @@ -49,6 +49,15 @@ vk_pipeline_shader_stage_is_null(const VkPipelineShaderStageCreateInfo *info) return true; } +bool +vk_pipeline_shader_stage_has_identifier(const VkPipelineShaderStageCreateInfo *info) +{ + const VkPipelineShaderStageModuleIdentifierCreateInfoEXT *id_info = + vk_find_struct_const(info->pNext, PIPELINE_SHADER_STAGE_MODULE_IDENTIFIER_CREATE_INFO_EXT); + + return id_info && id_info->identifierSize != 0; +} + static nir_shader * get_builtin_nir(const VkPipelineShaderStageCreateInfo *info) { diff --git a/src/vulkan/runtime/vk_pipeline.h b/src/vulkan/runtime/vk_pipeline.h index 1ca32a1428e..94d3a77b41e 100644 --- a/src/vulkan/runtime/vk_pipeline.h +++ b/src/vulkan/runtime/vk_pipeline.h @@ -53,6 +53,9 @@ typedef struct VkPipelineShaderStageNirCreateInfoMESA { bool vk_pipeline_shader_stage_is_null(const VkPipelineShaderStageCreateInfo *info); +bool +vk_pipeline_shader_stage_has_identifier(const VkPipelineShaderStageCreateInfo *info); + VkResult vk_pipeline_shader_stage_to_nir(struct vk_device *device, const VkPipelineShaderStageCreateInfo *info, diff --git a/src/vulkan/wsi/wsi_common_drm.c b/src/vulkan/wsi/wsi_common_drm.c index d82f9d5f1e1..fdf218a7fab 100644 --- a/src/vulkan/wsi/wsi_common_drm.c +++ b/src/vulkan/wsi/wsi_common_drm.c @@ -532,7 +532,7 @@ wsi_create_native_image_mem(const struct wsi_swapchain *chain, for (uint32_t p = 0; p < image->num_planes; p++) { const VkImageSubresource image_subresource = { - .aspectMask = VK_IMAGE_ASPECT_PLANE_0_BIT << p, + .aspectMask = VK_IMAGE_ASPECT_MEMORY_PLANE_0_BIT_EXT << p, .mipLevel = 0, .arrayLayer = 0, }; diff --git a/subprojects/packagefiles/proc-macro2/meson.build b/subprojects/packagefiles/proc-macro2/meson.build index b39d76e80c8..be2b272d375 100644 --- a/subprojects/packagefiles/proc-macro2/meson.build +++ b/subprojects/packagefiles/proc-macro2/meson.build @@ -41,6 +41,15 @@ endif if rc.version().version_compare('< 1.57') rust_args += ['--cfg', 'no_is_available'] endif +if rc.version().version_compare('< 1.66') + rust_args += ['--cfg', 'no_source_text'] +endif +if rc.version().version_compare('< 1.79') + rust_args += [ + '--cfg', 'no_literal_byte_character', + '--cfg', 'no_literal_c_string', + ] +endif u_ind = subproject('unicode-ident').get_variable('lib') diff --git a/subprojects/perfetto.wrap b/subprojects/perfetto.wrap index 8e86d842501..e92c50b6664 100644 --- a/subprojects/perfetto.wrap +++ b/subprojects/perfetto.wrap @@ -2,4 +2,4 @@ directory = perfetto url = https://android.googlesource.com/platform/external/perfetto -revision = v29.0 +revision = v45.0