From 263f8ff3f48156bbcb7fbc8f32613bb0662aa94f Mon Sep 17 00:00:00 2001 From: Sae86 Date: Mon, 9 Oct 2023 15:18:31 -0700 Subject: [PATCH] Add module that generates test IDs for return codes Signed-off-by: Sae86 --- chipsec/modules/common/remap.py | 2 +- chipsec/modules/tools/cpu/sinkhole.py | 2 +- chipsec/modules/tools/generate_test_id.py | 66 +++++++++++++++++++ chipsec/modules/tools/secureboot/te.py | 2 +- chipsec/modules/tools/smm/rogue_mmio_bar.py | 2 +- chipsec/modules/tools/smm/smm_ptr.py | 2 +- chipsec/modules/tools/vmm/hv/hypercallfuzz.py | 2 +- chipsec/modules/tools/vmm/hv/synth_dev.py | 2 +- chipsec/modules/tools/vmm/hv/synth_kbd.py | 2 +- chipsec/modules/tools/vmm/hv/vmbusfuzz.py | 2 +- chipsec/modules/tools/vmm/iofuzz.py | 2 +- chipsec/modules/tools/vmm/msr_fuzz.py | 2 +- chipsec/modules/tools/vmm/pcie_fuzz.py | 2 +- .../modules/tools/vmm/pcie_overlap_fuzz.py | 2 +- .../tools/vmm/vbox/vbox_crash_apicbase.py | 2 +- chipsec/modules/tools/vmm/venom.py | 2 +- .../modules/tools/vmm/xen/hypercallfuzz.py | 2 +- chipsec/modules/tools/vmm/xen/xsa188.py | 2 +- chipsec/modules/tools/wsmt.py | 2 +- 19 files changed, 84 insertions(+), 18 deletions(-) create mode 100644 chipsec/modules/tools/generate_test_id.py diff --git a/chipsec/modules/common/remap.py b/chipsec/modules/common/remap.py index 96b7754f1a..2926d22e03 100644 --- a/chipsec/modules/common/remap.py +++ b/chipsec/modules/common/remap.py @@ -59,7 +59,7 @@ class remap(BaseModule): def __init__(self): BaseModule.__init__(self) - self.rc_res = ModuleResult(1, 'https://chipsec.github.io/modules/chipsec.modules.common.remap.html') + self.rc_res = ModuleResult(0x43aa254, 'https://chipsec.github.io/modules/chipsec.modules.common.remap.html') def is_supported(self) -> bool: if self.cs.is_core(): diff --git a/chipsec/modules/tools/cpu/sinkhole.py b/chipsec/modules/tools/cpu/sinkhole.py index b1510e6f6a..e224b5988b 100644 --- a/chipsec/modules/tools/cpu/sinkhole.py +++ b/chipsec/modules/tools/cpu/sinkhole.py @@ -55,7 +55,7 @@ class sinkhole(BaseModule): def __init__(self): BaseModule.__init__(self) - self.rc_res = ModuleResult(2, 'https://chipsec.github.io/modules/chipsec.modules.tools.cpu.sinkhole.html') + self.rc_res = ModuleResult(0x230312a, 'https://chipsec.github.io/modules/chipsec.modules.tools.cpu.sinkhole.html') def is_supported(self): if not (self.cs.os_helper.is_windows() or self.cs.os_helper.is_linux()): diff --git a/chipsec/modules/tools/generate_test_id.py b/chipsec/modules/tools/generate_test_id.py new file mode 100644 index 0000000000..c34197722f --- /dev/null +++ b/chipsec/modules/tools/generate_test_id.py @@ -0,0 +1,66 @@ +# CHIPSEC: Platform Security Assessment Framework +# Copyright (c) 2023, Intel Corporation +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; Version 2. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +# +# Contact information: +# chipsec@intel.com +# + +""" +Generate a test ID using hashlib from the test's file name (no file extension). +Hash is truncated to 28 bits. + +Usage: + ``chipsec_main -m common.tools.generate_test_id -a `` + +Examples: + >>> chipsec_main.py -m common.tools.generate_test_id -a remap + >>> chipsec_main.py -m common.tools.generate_test_id -a s3bootscript + >>> chipsec_main.py -m common.tools.generate_test_id -a bios_ts +""" + +from chipsec.module_common import BaseModule, ModuleResult +from typing import List +import hashlib + +class generate_test_id(BaseModule): + def __init__(self): + BaseModule.__init__(self) + self.rc_res = ModuleResult(0xd711589, 'https://chipsec.github.io/modules/chipsec.modules.tools.generate_test_id.html') + + def usage(self): + self.logger.log(__doc__.replace('`', '')) + return + + def is_supported(self) -> bool: + return True + + def generate_id(self, test_name: str) -> int: + return hashlib.sha256(test_name.encode('ascii')).hexdigest()[:7] + + def run(self, module_argv: List[str]) -> int: + self.logger.start_test("Generate test ID") + + if len(module_argv) == 1: + module_name = module_argv[0] + self.logger.log_good(f'Test ID for {module_name} is 0x{self.generate_id(module_name)}\n') + self.rc_res.setStatusBit(self.rc_res.status.SUCCESS) + self.res = self.rc_res.getReturnCode(ModuleResult.INFORMATION) + else: + self.rc_res.setStatusBit(self.rc_res.status.UNSUPPORTED_OPTION) + self.res = self.rc_res.getReturnCode(ModuleResult.WARNING) + self.usage() + + return self.res \ No newline at end of file diff --git a/chipsec/modules/tools/secureboot/te.py b/chipsec/modules/tools/secureboot/te.py index 5ce0c36fea..79b1a1ca39 100644 --- a/chipsec/modules/tools/secureboot/te.py +++ b/chipsec/modules/tools/secureboot/te.py @@ -493,7 +493,7 @@ class te(BaseModule): def __init__(self): BaseModule.__init__(self) - self.rc_res = ModuleResult(3, 'https://chipsec.github.io/modules/chipsec.modules.tools.secureboot.te.html') + self.rc_res = ModuleResult(0x2d6c9a9, 'https://chipsec.github.io/modules/chipsec.modules.tools.secureboot.te.html') def is_supported(self): #win8 = self.cs.helper.is_win8_or_greater() diff --git a/chipsec/modules/tools/smm/rogue_mmio_bar.py b/chipsec/modules/tools/smm/rogue_mmio_bar.py index 11ef6e5986..ae684d0dd4 100644 --- a/chipsec/modules/tools/smm/rogue_mmio_bar.py +++ b/chipsec/modules/tools/smm/rogue_mmio_bar.py @@ -70,7 +70,7 @@ class rogue_mmio_bar(BaseModule): def __init__(self): BaseModule.__init__(self) self._interrupts = Interrupts(self.cs) - self.rc_res = ModuleResult(4, 'https://chipsec.github.io/modules/chipsec.modules.tools.smm.rogue_mmio_bar.html') + self.rc_res = ModuleResult(0x293f9e8, 'https://chipsec.github.io/modules/chipsec.modules.tools.smm.rogue_mmio_bar.html') # SMI code to be written to I/O port 0xB2 self.smic_start = 0x00 diff --git a/chipsec/modules/tools/smm/smm_ptr.py b/chipsec/modules/tools/smm/smm_ptr.py index 6639ab9458..66311f7e47 100644 --- a/chipsec/modules/tools/smm/smm_ptr.py +++ b/chipsec/modules/tools/smm/smm_ptr.py @@ -188,7 +188,7 @@ def __init__(self): self.test_ptr_in_buffer = False self.fill_byte = _MEM_FILL_VALUE self.fill_size = _MEM_FILL_SIZE - self.rc_res = ModuleResult(5, 'https://chipsec.github.io/modules/chipsec.modules.tools.smm.smm_ptr.html') + self.rc_res = ModuleResult(0xf8457d4, 'https://chipsec.github.io/modules/chipsec.modules.tools.smm.smm_ptr.html') def is_supported(self): return True diff --git a/chipsec/modules/tools/vmm/hv/hypercallfuzz.py b/chipsec/modules/tools/vmm/hv/hypercallfuzz.py index 075dfe591e..f32015ebbc 100644 --- a/chipsec/modules/tools/vmm/hv/hypercallfuzz.py +++ b/chipsec/modules/tools/vmm/hv/hypercallfuzz.py @@ -48,7 +48,7 @@ class HypercallFuzz(BaseModule): def __init__(self): BaseModule().__init__() - self.rc_res = ModuleResult(10, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.hypercallfuzz.html') + self.rc_res = ModuleResult(0x6dc9bb0, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.hypercallfuzz.html') def usage(self): print(' Usage:') diff --git a/chipsec/modules/tools/vmm/hv/synth_dev.py b/chipsec/modules/tools/vmm/hv/synth_dev.py index 2afcf28ccd..8e15f6f1cd 100644 --- a/chipsec/modules/tools/vmm/hv/synth_dev.py +++ b/chipsec/modules/tools/vmm/hv/synth_dev.py @@ -96,7 +96,7 @@ def print_statistics(self): class synth_dev(BaseModule): def __init__(self): BaseModule.__init__(self) - self.rc_res = ModuleResult(11, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.synth_dev.html') + self.rc_res = ModuleResult(0x6221b7e, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.synth_dev.html') def usage(self): print(' Usage:') diff --git a/chipsec/modules/tools/vmm/hv/synth_kbd.py b/chipsec/modules/tools/vmm/hv/synth_kbd.py index 9e219e228b..ca71371bea 100644 --- a/chipsec/modules/tools/vmm/hv/synth_kbd.py +++ b/chipsec/modules/tools/vmm/hv/synth_kbd.py @@ -72,7 +72,7 @@ def ringbuffer_read(self): class synth_kbd(BaseModule): def __init__(self): BaseModule.__init__(self) - self.rc_res = ModuleResult(12, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.synth_kbd.html') + self.rc_res = ModuleResult(0x0d28d62, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.synth_kbd.html') def usage(self): print(' Usage:') diff --git a/chipsec/modules/tools/vmm/hv/vmbusfuzz.py b/chipsec/modules/tools/vmm/hv/vmbusfuzz.py index 4f1cdaf1b2..a21269e881 100644 --- a/chipsec/modules/tools/vmm/hv/vmbusfuzz.py +++ b/chipsec/modules/tools/vmm/hv/vmbusfuzz.py @@ -65,7 +65,7 @@ def __init__(self): self.fuzzing = False self.fuzzing_rules = {} self.current_message = 0 - self.rc_res = ModuleResult(13, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.vmbusfuzz.html') + self.rc_res = ModuleResult(0x17f285c, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.vmbusfuzz.html') ## # hv_post_msg - Fuzzing a message to be sent diff --git a/chipsec/modules/tools/vmm/iofuzz.py b/chipsec/modules/tools/vmm/iofuzz.py index b7dc154118..47caa0c926 100644 --- a/chipsec/modules/tools/vmm/iofuzz.py +++ b/chipsec/modules/tools/vmm/iofuzz.py @@ -79,7 +79,7 @@ class iofuzz(BaseModule): def __init__(self): BaseModule().__init__() - self.rc_res = ModuleResult(20, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.iofuzz.html') + self.rc_res = ModuleResult(0x485df2e, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.iofuzz.html') def fuzz_ports(self, iterations, write_count, random_order=False): diff --git a/chipsec/modules/tools/vmm/msr_fuzz.py b/chipsec/modules/tools/vmm/msr_fuzz.py index 2c4fc41919..5ab61d7609 100644 --- a/chipsec/modules/tools/vmm/msr_fuzz.py +++ b/chipsec/modules/tools/vmm/msr_fuzz.py @@ -80,7 +80,7 @@ class msr_fuzz (BaseModule): def __init__(self): BaseModule().__init__() - self.rc_res = ModuleResult(21, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.msr_fuzz.html') + self.rc_res = ModuleResult(0x2e31482, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.msr_fuzz.html') def fuzz_MSRs(self, msr_addr_start, random_order=False): msr_addr_range = 0x10000 diff --git a/chipsec/modules/tools/vmm/pcie_fuzz.py b/chipsec/modules/tools/vmm/pcie_fuzz.py index 86bfa7b544..17d6d10bad 100644 --- a/chipsec/modules/tools/vmm/pcie_fuzz.py +++ b/chipsec/modules/tools/vmm/pcie_fuzz.py @@ -78,7 +78,7 @@ class pcie_fuzz(BaseModule): def __init__(self): BaseModule().__init__() - self.rc_res = ModuleResult(22, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.pcie_fuzz.html') + self.rc_res = ModuleResult(0x61c1431, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.pcie_fuzz.html') def fuzz_io_bar(self, bar, size=0x100): port_off = 0 diff --git a/chipsec/modules/tools/vmm/pcie_overlap_fuzz.py b/chipsec/modules/tools/vmm/pcie_overlap_fuzz.py index 4b560f5c78..cf81fba0df 100644 --- a/chipsec/modules/tools/vmm/pcie_overlap_fuzz.py +++ b/chipsec/modules/tools/vmm/pcie_overlap_fuzz.py @@ -67,7 +67,7 @@ class pcie_overlap_fuzz(BaseModule): def __init__(self): BaseModule().__init__() - self.rc_res = ModuleResult(23, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.pcie_overlap_fuzz.html') + self.rc_res = ModuleResult(0x19702b2, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.pcie_overlap_fuzz.html') def overlap_mmio_range(self, bus1, dev1, fun1, is64bit1, off1, bus2, dev2, fun2, is64bit2, off2, direction): base_lo1 = self.cs.pci.read_dword(bus1, dev1, fun1, off1) diff --git a/chipsec/modules/tools/vmm/vbox/vbox_crash_apicbase.py b/chipsec/modules/tools/vmm/vbox/vbox_crash_apicbase.py index 43e2d46cb3..b9ecbd895a 100644 --- a/chipsec/modules/tools/vmm/vbox/vbox_crash_apicbase.py +++ b/chipsec/modules/tools/vmm/vbox/vbox_crash_apicbase.py @@ -49,7 +49,7 @@ class vbox_crash_apicbase(BaseModule): def __init__(self): BaseModule().__init__() - self.rc_res = ModuleResult(14, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.vbox.vbox_crash_apicbase.html') + self.rc_res = ModuleResult(0x14428af, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.vbox.vbox_crash_apicbase.html') def run(self, module_argv): self.logger.start_test("Host OS Crash due to IA32_APIC_BASE (Oracle VirtualBox CVE-2015-0377)") diff --git a/chipsec/modules/tools/vmm/venom.py b/chipsec/modules/tools/vmm/venom.py index b89020ae1f..b3f7d1be11 100644 --- a/chipsec/modules/tools/vmm/venom.py +++ b/chipsec/modules/tools/vmm/venom.py @@ -61,7 +61,7 @@ class venom (BaseModule): def __init__(self): BaseModule().__init__() - self.rc_res = ModuleResult(24, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.venom.html') + self.rc_res = ModuleResult(0x6e48a35, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.venom.html') def venom_impl(self): self.cs.io.write_port_byte(FDC_PORT_DATA_FIFO, FD_CMD) diff --git a/chipsec/modules/tools/vmm/xen/hypercallfuzz.py b/chipsec/modules/tools/vmm/xen/hypercallfuzz.py index 477c647adc..cf0071f3dc 100644 --- a/chipsec/modules/tools/vmm/xen/hypercallfuzz.py +++ b/chipsec/modules/tools/vmm/xen/hypercallfuzz.py @@ -58,7 +58,7 @@ class HypercallFuzz(BaseModule): def __init__(self): BaseModule().__init__() - self.rc_res = ModuleResult(15, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.xen.hypercallfuzz.html') + self.rc_res = ModuleResult(0x9e42fe3, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.xen.hypercallfuzz.html') def usage(self): self.logger.log(self.__doc__.replace('`', '')) diff --git a/chipsec/modules/tools/vmm/xen/xsa188.py b/chipsec/modules/tools/vmm/xen/xsa188.py index 2a7acc3a51..77873150bb 100644 --- a/chipsec/modules/tools/vmm/xen/xsa188.py +++ b/chipsec/modules/tools/vmm/xen/xsa188.py @@ -53,7 +53,7 @@ class xsa188(BaseModule): def __init__(self): BaseModule().__init__() - self.rc_res = ModuleResult(16, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.xen.xsa188.html') + self.rc_res = ModuleResult(0x13a3575, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.xen.xsa188.html') def run(self, module_argv): self.logger.start_test('Xen XSA-188 PoC check') diff --git a/chipsec/modules/tools/wsmt.py b/chipsec/modules/tools/wsmt.py index 3bc2505e09..2fa624f2e3 100644 --- a/chipsec/modules/tools/wsmt.py +++ b/chipsec/modules/tools/wsmt.py @@ -45,7 +45,7 @@ class wsmt(BaseModule): def __init__(self): BaseModule.__init__(self) self._acpi = ACPI(self.cs) - self.rc_res = ModuleResult(25, 'https://chipsec.github.io/modules/chipsec.modules.tools.wsmt.html') + self.rc_res = ModuleResult(0x6ae0748, 'https://chipsec.github.io/modules/chipsec.modules.tools.wsmt.html') def is_supported(self): return True