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Dev #36

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rodrigomelo9
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rodrigomelo9 and others added 30 commits May 15, 2022 20:38
@rodrigomelo9
Updated README.md and modified version (0.3.0-dev)
3d9b185
@rodrigomelo9
resources: submodule added
c18b44b
@rodrigomelo9
test: added mocks (for vendors tools)
1e8a546
@rodrigomelo9
ci: fixed an 'exit status 2' issue
06c31d4
@rodrigomelo9
ci: added python 3.10
b896134
@rodrigomelo9
ci: added schedule based on cron
fda3a82
@rodrigomelo9
fpga: renamed add_path as add_vlog_include
dbfc133
@rodrigomelo9
fpga: added add_vlog_define and set_vhdl_arch in project.py (not impl…
579f275 
…emented)
@rodrigomelo9
fpga: renamed set_param as add_param
6699cd9
@rodrigomelo9
fpga: renamed 'imp' as 'par'
d1bd35c
@rodrigomelo9
Updated shields in README.md
bbdc605
@rodrigomelo9
fpga: renamed 'init' as 'meta'
fe8bcbc
@lmcapacho @rodrigomelo9
fix: ModuleNotFoundError: No module named 'fpga.helpers'
8777ee8
@rodrigomelo9
Improved existing mocks
7f49fdf
@rodrigomelo9
Merge branch 'rewrite' of github.com:PyFPGA/pyfpga into rewrite
31e33d1
@rodrigomelo9
Added a new WIP Project class under the pyfpga directory
4cc3513
@rodrigomelo9
ci: updated, modified to analyze pyfpga instead of fpga
a9a25b1
@rodrigomelo9
ci: renamed doc as docs, disabled docs and test
4b037ae
@rodrigomelo9
ci: fixed lint action
8288159
@rodrigomelo9
ci: updated Makefile and used for the lint action
7347667
@rodrigomelo9
Modified project to employ enumerations
4d845b6
@rodrigomelo9
Added docs with the skeleton generated by sphinx-quickstart
049af6b
@rodrigomelo9
ci: updated docs
2f67bde
@rodrigomelo9
Moved content from doc/images into docs/images and docs/_static
35534eb
@rodrigomelo9
Moved doc contento to docs/wip
fe57927
@rodrigomelo9
docs: added intro (empty) and api (automodule)
0717dc1
@rodrigomelo9
ci: updated/enabled docs
33bfdcc
@rodrigomelo9
Removed unused config files
ece35b0
@rodrigomelo9
ci: updated docs and lint to be similar
c2957c0
@rodrigomelo9
docs: fixed to find pyfpga.project
3d29a99
@rodrigomelo9
diamondc: removed unused import
fbf80e0
@rodrigomelo9
Simplified how to clean docs
884fda8
@rodrigomelo9
ci: modified when to trigger the docs actions
7851b97
@rodrigomelo9
openflow: re-added VHDL support (WIP)
c7e5369
@rodrigomelo9
openflow: add generics support
01991d7
@rodrigomelo9
openflow: properly re-added VHDL support
2864ced 
Closes #51
@rodrigomelo9
docs: add a hint about file processing order
aa29487
@rodrigomelo9
Merge pull request #53 from PyFPGA/openflow-vhdl
5aecfde 
Openflow: re-add VHDL support
@rodrigomelo9
docs: added a diagram about Openflow
9a2df31
@rodrigomelo9
ci: modified to trigger docs when the branch is main or dev
29ed35a
@rodrigomelo9
ci: add windows tests
9aa363f
@rodrigomelo9
ci: add to run regress.sh
6dc528a
@rodrigomelo9
ci: modified when to trigger the docs actions
48af8b2
@rodrigomelo9
ci: modified to run ubuntu and windows tests using the same job
fcd51f6
@rodrigomelo9
Add the --notool option, to avoid errors when tools are not available
1a0ff91
@rodrigomelo9
ci: fix issue specifyng the Python version
8c061c1
@rodrigomelo9
Merge pull request #55 from PyFPGA/ci-win
e3fadf9 
CI: add to verify on Windows
@rodrigomelo9
tests: checking that paths are posix-like
e313901
@rodrigomelo9
ci: moved to run regress from test.yml to the Makefile
d94057e
@rodrigomelo9
prj2bit: improve ERROR messages
d6b773b
@rodrigomelo9
Add constraints for the mpfs-disco-kit board
5c5c4f9
@rodrigomelo9
Fix support for PolarFireSoC devices
25e683c
@rodrigomelo9
Improve PART format parsing (ise, libero and openflow)
a90c1f4
@rodrigomelo9
Initial support for Libero programming
167fbeb
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4 participants
@rodrigomelo9 @lmcapacho @m42uko @gts-bzi