diff --git a/arch/arm/src/imxrt/hardware/imxrt_adc.h b/arch/arm/src/imxrt/hardware/imxrt_adc.h index 35e62db8b9f1e..4858b46a2f903 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_adc.h +++ b/arch/arm/src/imxrt/hardware/imxrt_adc.h @@ -32,5 +32,4 @@ #include "imxrt_adc_ver1.h" #endif - #endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_ADC_H */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_flexspi.h b/arch/arm/src/imxrt/hardware/imxrt_flexspi.h index 593c3c55eec12..9e43712d68027 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_flexspi.h +++ b/arch/arm/src/imxrt/hardware/imxrt_flexspi.h @@ -102,7 +102,6 @@ struct flexspi_type_s #define IMXRT_FLEXSPI2_AHBBUFREGIONSTART3 (IMXRT_FLEXSPI2C_BASE + IMXRT_FLEXSPI_AHBBUFREGIONSTART3_OFFSET) #define IMXRT_FLEXSPI2_AHBBUFREGIONEND3 (IMXRT_FLEXSPI2C_BASE + IMXRT_FLEXSPI_AHBBUFREGIONEND3_OFFSET) - /* MCR0 - Module Control Register 0 */ #define FLEXSPI_MCR0_SWRESET_MASK (0x1u) diff --git a/arch/arm/src/imxrt/hardware/imxrt_ocotp.h b/arch/arm/src/imxrt/hardware/imxrt_ocotp.h index f45a7de62c0fe..de9665302c2e4 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_ocotp.h +++ b/arch/arm/src/imxrt/hardware/imxrt_ocotp.h @@ -279,12 +279,12 @@ /* 64 Bit unique id consisting of: * LOT_NO_ENC[42:0] 42 bits LOT ID * IMXRT_OCOTP_UNIQUE_ID_MSB[31:0] IMXRT_OCOTP_UNIQUE_ID_LSB[10:0] - * WAFER_NO[4:0] 5 bits The wafer number of the wafer on which the device was fabricated - * IMXRT_OCOTP_UNIQUE_ID_LSB[15:11] - * DIE-YCORDINATE[7:0] 8 bits The Y-coordinate of the die location on the wafer - * IMXRT_OCOTP_UNIQUE_ID_LSB[23:16] - * DIE-XCORDINATE[7:0] 8 bits The X-coordinate of the die location on the wafer - * IMXRT_OCOTP_UNIQUE_ID_LSB[31:24] + * WAFER_NO[4:0] 5 bits The wafer number of the wafer on which the device + * was fabricated IMXRT_OCOTP_UNIQUE_ID_LSB[15:11] + * DIE-YCORDINATE[7:0] 8 bits The Y-coordinate of the die location + * on the wafer IMXRT_OCOTP_UNIQUE_ID_LSB[23:16] + * DIE-XCORDINATE[7:0] 8 bits The X-coordinate of the die location + * on the wafer IMXRT_OCOTP_UNIQUE_ID_LSB[31:24] */ #define IMXRT_OCOTP_UNIQUE_ID_MSB (IMXRT_OCOTP_CFG0) /* Most Significant Bytes of 64 bit UUID */ #define IMXRT_OCOTP_UNIQUE_ID_LSB (IMXRT_OCOTP_CFG1) /* Least Significant Bytes of 64 bit UUID */ diff --git a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ccm.h b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ccm.h index 855eebbeb63cd..cb8ff2ad5a752 100644 --- a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ccm.h +++ b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ccm.h @@ -257,7 +257,8 @@ #define CCM_CG_CTRL_RSTDIV_SHIFT (16) /* Bits 16-23: Clock group global restart count (RSTDIV) */ #define CCM_CG_CTRL_RSTDIV_MASK (0xff << CCM_CG_CTRL_RSTDIV_SHIFT) # define CCM_CG_CTRL_RSTDIV(n) (((n)-1) << CCM_CG_CTRL_RSTDIV_SHIFT) /* Divide selected clock by n */ -#define CCM_CG_CTRL_OFF (1 << 24) /* Bit 24: Shutdown all clocks in clock group (OFF) */ +#define CCM_CG_CTRL_OFF (1 << 24) /* Bit 24: Shutdown all clocks in clock group (OFF) */ + /* Bits 25-31: Reserved */ /* Clock group working status (CLOCK_GROUPn_STATUS0, n=0..1) */ diff --git a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ocotp.h b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ocotp.h index 754daa337215f..63e14e4958c4d 100644 --- a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ocotp.h +++ b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ocotp.h @@ -79,8 +79,8 @@ /* 64 Bit unique id consisting of: * LOT_NO_ENC[42:0] 42 bits LOT ID * IMXRT_OCOTP_UNIQUE_ID_MSB[31:0] IMXRT_OCOTP_UNIQUE_ID_LSB[10:0] - * WAFER_NO[4:0] 5 bits The wafer number of the wafer on which the device was fabricated - * IMXRT_OCOTP_UNIQUE_ID_LSB[15:11] + * WAFER_NO[4:0] 5 bits The wafer number of the wafer on which the device + * was fabricated IMXRT_OCOTP_UNIQUE_ID_LSB[15:11] * DIE-YCORDINATE[7:0] 8 bits The Y-coordinate of the die location on the wafer * IMXRT_OCOTP_UNIQUE_ID_LSB[23:16] * DIE-XCORDINATE[7:0] 8 bits The X-coordinate of the die location on the wafer diff --git a/arch/arm/src/imxrt/imxrt102x_gpio.c b/arch/arm/src/imxrt/imxrt102x_gpio.c index 949780da6a212..d0d5ae825b18c 100644 --- a/arch/arm/src/imxrt/imxrt102x_gpio.c +++ b/arch/arm/src/imxrt/imxrt102x_gpio.c @@ -187,3 +187,7 @@ static const uint8_t * const g_gpio_padmux[IMXRT_GPIO_NPORTS + 1] = g_gpio5_padmux, /* GPIO5 */ NULL /* End of list */ }; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/imxrt/imxrt105x_gpio.c b/arch/arm/src/imxrt/imxrt105x_gpio.c index f1f9c9d86f477..f9e600fde755e 100644 --- a/arch/arm/src/imxrt/imxrt105x_gpio.c +++ b/arch/arm/src/imxrt/imxrt105x_gpio.c @@ -226,3 +226,7 @@ static const uint8_t * const g_gpio_padmux[IMXRT_GPIO_NPORTS + 1] = g_gpio5_padmux, /* GPIO5 */ NULL /* End of list */ }; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ \ No newline at end of file diff --git a/arch/arm/src/imxrt/imxrt106x_gpio.c b/arch/arm/src/imxrt/imxrt106x_gpio.c index 0c993833bac07..c66ce8437d990 100644 --- a/arch/arm/src/imxrt/imxrt106x_gpio.c +++ b/arch/arm/src/imxrt/imxrt106x_gpio.c @@ -239,3 +239,7 @@ static const uint8_t * const g_gpio_padmux[IMXRT_GPIO_NPORTS + 1] = g_gpio4_padmux, /* GPIO9 */ NULL /* End of list */ }; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/imxrt/imxrt117x_gpio.c b/arch/arm/src/imxrt/imxrt117x_gpio.c index a6d0c6a4d81a0..2dfac8da8edeb 100644 --- a/arch/arm/src/imxrt/imxrt117x_gpio.c +++ b/arch/arm/src/imxrt/imxrt117x_gpio.c @@ -546,3 +546,7 @@ static const uint8_t * const g_gpio_padmux[IMXRT_GPIO_NPORTS + 1] = g_gpio13_padmux, /* GPIO13 */ NULL /* End of list */ }; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ \ No newline at end of file diff --git a/arch/arm/src/imxrt/imxrt117x_mpuinit.c b/arch/arm/src/imxrt/imxrt117x_mpuinit.c index 2dfd166a106bd..2f5a9117ebacd 100644 --- a/arch/arm/src/imxrt/imxrt117x_mpuinit.c +++ b/arch/arm/src/imxrt/imxrt117x_mpuinit.c @@ -52,7 +52,9 @@ putreg32(regval, MPU_RASR); mpu_configure_region(IMXRT_SEMC0_BASE, 512 * 1024 * 1024, + /* Instruction access Enabled */ + MPU_RASR_AP_RWRW | /* P:RW U:RW */ MPU_RASR_TEX_DEV /* Device */ /* Not Cacheable */ @@ -62,7 +64,9 @@ ); mpu_configure_region(IMXRT_FLEXSPI2_CIPHER_BASE, 512 * 1024 * 1024, + /* Instruction access Enabled */ + MPU_RASR_AP_RWRW | /* P:RW U:RW */ MPU_RASR_TEX_DEV /* Device */ /* Not Cacheable */ @@ -72,7 +76,9 @@ ); mpu_configure_region(IMXRT_ITCM_BASE, 1 * 1024 * 1024 * 1024, + /* Instruction access Enabled */ + MPU_RASR_AP_RWRW | /* P:RW U:RW */ MPU_RASR_TEX_DEV /* Device */ /* Not Cacheable */ @@ -82,7 +88,9 @@ ); mpu_configure_region(IMXRT_ITCM_BASE, 256 * 1024, + /* Instruction access Enabled */ + MPU_RASR_AP_RWRW | /* P:RW U:RW */ MPU_RASR_TEX_NOR /* Normal */ /* Not Cacheable */ @@ -92,7 +100,9 @@ ); mpu_configure_region(IMXRT_DTCM_BASE, 256 * 1024, + /* Instruction access Enabled */ + MPU_RASR_AP_RWRW | /* P:RW U:RW */ MPU_RASR_TEX_NOR /* Normal */ /* Not Cacheable */ @@ -102,7 +112,9 @@ ); mpu_configure_region(IMXRT_OCRAM_M4_BASE, 1 * 1024 * 1024, + /* Instruction access Enabled */ + MPU_RASR_AP_RWRW | /* P:RW U:RW */ MPU_RASR_TEX_SO | /* Strongly Ordered */ RASR_C_VALUE | /* Cacheable DCACHE ? 0 : 1 */ @@ -112,7 +124,9 @@ ); mpu_configure_region(IMXRT_OCRAM_M4_BASE + (1 * 1024 * 1024), 512 * 1024, + /* Instruction access Enabled */ + MPU_RASR_AP_RWRW | /* P:RW U:RW */ MPU_RASR_TEX_SO | /* Strongly Ordered */ RASR_C_VALUE | /* Cacheable DCACHE ? 0 : 1 */ @@ -122,7 +136,9 @@ ); mpu_configure_region(IMXRT_FLEXSPI1_CIPHER_BASE, 16 * 1024 * 1024, + /* Instruction access Enabled */ + MPU_RASR_AP_RORO | /* P:R0 U:R0 */ MPU_RASR_TEX_SO | /* Strongly Ordered */ MPU_RASR_C | /* Cacheable */ @@ -132,7 +148,9 @@ ); mpu_configure_region(IMXRT_AIPS1_BASE, 16 * 1024 * 1024, + /* Instruction access Enabled */ + MPU_RASR_AP_RWRW | /* P:RW U:RW */ MPU_RASR_TEX_DEV /* Device */ /* Not Cacheable */ @@ -142,7 +160,9 @@ ); mpu_configure_region(IMXRT_SIM_DISP_BASE, 2 * 1024 * 1024, + /* Instruction access Enabled */ + MPU_RASR_AP_RWRW | /* P:RW U:RW */ MPU_RASR_TEX_DEV /* Device */ /* Not Cacheable */ @@ -152,7 +172,9 @@ ); mpu_configure_region(IMXRT_SIM_M7_BASE, 1 * 1024 * 1024, + /* Instruction access Enabled */ + MPU_RASR_AP_RWRW | /* P:RW U:RW */ MPU_RASR_TEX_DEV /* Device */ /* Not Cacheable */ @@ -162,7 +184,9 @@ ); mpu_configure_region(IMXRT_GPU2D_BASE, 2 * 1024 * 1024, + /* Instruction access Enabled */ + MPU_RASR_AP_RWRW | /* P:RW U:RW */ MPU_RASR_TEX_DEV /* Device */ /* Not Cacheable */ @@ -172,7 +196,9 @@ ); mpu_configure_region(IMXRT_AIPS_M7_BASE, 1 * 1024 * 1024, + /* Instruction access Enabled */ + MPU_RASR_AP_RWRW | /* P:RW U:RW */ MPU_RASR_TEX_DEV /* Device */ /* Not Cacheable */ @@ -180,3 +206,7 @@ /* Not Shareable */ /* No Subregion disable */ ); + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/imxrt/imxrt_adc_ver1.c b/arch/arm/src/imxrt/imxrt_adc_ver1.c index 6f09462644c2a..d3a935235a9c2 100644 --- a/arch/arm/src/imxrt/imxrt_adc_ver1.c +++ b/arch/arm/src/imxrt/imxrt_adc_ver1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/imxrt/imxrt_adc_var1.c + * arch/arm/src/imxrt/imxrt_adc_ver1.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/arm/src/imxrt/imxrt_clockconfig_ver2.c b/arch/arm/src/imxrt/imxrt_clockconfig_ver2.c index 9ab1061a0142f..7ac1ce51b61d8 100644 --- a/arch/arm/src/imxrt/imxrt_clockconfig_ver2.c +++ b/arch/arm/src/imxrt/imxrt_clockconfig_ver2.c @@ -127,8 +127,9 @@ static void imxrt_oscsetup(void) putreg32(reg, IMXRT_CCM_CR_CTRL(8)); /* FlexRAM AXI CLK ROOT */ - putreg32(CCM_CG_CTRL_RSTDIV(1) | CCM_CG_CTRL_DIV0(1), IMXRT_CCM_CG_CTRL(0)); + putreg32(CCM_CG_CTRL_RSTDIV(1) | CCM_CG_CTRL_DIV0(1), + IMXRT_CCM_CG_CTRL(0)); } /**************************************************************************** diff --git a/arch/arm/src/imxrt/imxrt_enet.c b/arch/arm/src/imxrt/imxrt_enet.c index a64525f7bb2fc..df8a72489c835 100644 --- a/arch/arm/src/imxrt/imxrt_enet.c +++ b/arch/arm/src/imxrt/imxrt_enet.c @@ -200,8 +200,7 @@ # error "Need at least one RX buffer" #endif -/* - * From ref manual TDSR/RDSR description +/* From ref manual TDSR/RDSR description * For optimal performance the pointer should be 512-bit aligned, that is, * evenly divisible by 64. */ @@ -739,6 +738,7 @@ static int imxrt_transmit(struct imxrt_driver_s *priv) #ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH /* Make sure that descriptors are flushed */ + ARM_DSB(); #else up_clean_dcache((uintptr_t)txdesc, @@ -1424,6 +1424,7 @@ static int imxrt_ifup_action(struct net_driver_s *dev, bool resetphy) #ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH /* Make sure that descriptors are flushed */ + ARM_DSB(); #endif diff --git a/arch/arm/src/imxrt/imxrt_iomuxc_ver2.c b/arch/arm/src/imxrt/imxrt_iomuxc_ver2.c index 7804916c1f66a..b7463620648fe 100644 --- a/arch/arm/src/imxrt/imxrt_iomuxc_ver2.c +++ b/arch/arm/src/imxrt/imxrt_iomuxc_ver2.c @@ -528,7 +528,7 @@ int imxrt_iomux_configure(uintptr_t padctl, iomux_pinset_t ioset) } else if (padctl <= IMXRT_PADCTL_GPIO_DISP_B1_11) { - /* GPIO_DISP_B1 *********************************************************/ + /* GPIO_DISP_B1 *******************************************************/ /* Select drive strength */ @@ -631,7 +631,6 @@ int imxrt_iomux_configure(uintptr_t padctl, iomux_pinset_t ioset) else { regval &= ~(PADCTL_DISP_B2_ODE); - } } else if (padctl <= IMXRT_PADCTL_GPIO_LPSR_15)