diff --git a/apps/xu5_st1-fmc_x4sfp.app.ini b/apps/xu5_st1-fmc_x4sfp.app.ini new file mode 100644 index 000000000..8ac266007 --- /dev/null +++ b/apps/xu5_st1-fmc_x4sfp.app.ini @@ -0,0 +1,33 @@ +[.] +description: + Standard set of PandABox blocks with: + - FMC x4SFP + - PandA synchroniser on all MGTs +target: xu5_st1 +options: !pcap_std_dev +includes: common_soft_blocks.include.ini + +[FMC_X4SFP] +module: fmc_x4sfp + +[SFP1_SYNC] +module: sfp_panda_sync +ini: sfp_panda_sync_us.block.ini +site: fmc_mgt 1 + +[SFP2_SYNC] +module: sfp_panda_sync +ini: sfp_panda_sync_us.block.ini +site: fmc_mgt 2 + +[SFP3_SYNC] +module: sfp_panda_sync +ini: sfp_panda_sync_us.block.ini +site: fmc_mgt 3 + +[SFP4_SYNC] +module: sfp_panda_sync +ini: sfp_panda_sync_us.block.ini +site: fmc_mgt 4 + + diff --git a/common/hdl/defines/interface_types.vhd b/common/hdl/defines/interface_types.vhd index 427e631b4..477772691 100644 --- a/common/hdl/defines/interface_types.vhd +++ b/common/hdl/defines/interface_types.vhd @@ -14,6 +14,12 @@ package interface_types is FMC_CLK0_M2C_N : std_logic; FMC_CLK1_M2C_P : std_logic; FMC_CLK1_M2C_N : std_logic; + FMC_I2C_SDA_in : std_logic; + FMC_I2C_SDA_out : std_logic; + FMC_I2C_SDA_tri : std_logic; + FMC_I2C_SCL_in : std_logic; + FMC_I2C_SCL_out : std_logic; + FMC_I2C_SCL_tri : std_logic; end record FMC_interface; view FMC_Module of FMC_interface is @@ -24,6 +30,13 @@ package interface_types is FMC_CLK0_M2C_N : inout; FMC_CLK1_M2C_P : in; FMC_CLK1_M2C_N : in; + FMC_I2C_SDA_in : out; + FMC_I2C_SDA_out : in; + FMC_I2C_SDA_tri : in; + FMC_I2C_SCL_in : out; + FMC_I2C_SCL_out : in; + FMC_I2C_SCL_tri : in; + end view FMC_Module; constant FMC_init : FMC_interface; @@ -92,7 +105,13 @@ package body interface_types is FMC_CLK0_M2C_P => 'Z', FMC_CLK0_M2C_N => 'Z', FMC_CLK1_M2C_P => '0', - FMC_CLK1_M2C_N => '0'); + FMC_CLK1_M2C_N => '0', + FMC_I2C_SDA_in => '0', + FMC_I2C_SDA_out => '0', + FMC_I2C_SDA_tri => '1', + FMC_I2C_SCL_in => '0', + FMC_I2C_SCL_out => '0', + FMC_I2C_SCL_tri => '1'); constant MGT_init : MGT_interface := ( SFP_LOS => '0', GTREFCLK => '0', diff --git a/modules/fmc_x4sfp/const/fmc_x4sfp.xdc b/modules/fmc_x4sfp/const/fmc_x4sfp.xdc new file mode 100644 index 000000000..15cba07fc --- /dev/null +++ b/modules/fmc_x4sfp/const/fmc_x4sfp.xdc @@ -0,0 +1,6 @@ +# ------------------------------------------------------------------- +# FMC Clock Timing Constraints +# ------------------------------------------------------------------- +create_clock -period 6.400 [get_ports FMC_CLK0_M2C_P[0]] +create_clock -period 6.400 [get_ports FMC_CLK1_M2C_P[0]] + diff --git a/modules/fmc_x4sfp/const/fmc_x4sfp_impl.xdc b/modules/fmc_x4sfp/const/fmc_x4sfp_impl.xdc new file mode 100644 index 000000000..8a050ccbd --- /dev/null +++ b/modules/fmc_x4sfp/const/fmc_x4sfp_impl.xdc @@ -0,0 +1,12 @@ +# ------------------------------------------------------------------- +# Define asynchronous clocks +# ------------------------------------------------------------------- +set_clock_groups -asynchronous -group FMC_CLK0_M2C_P[0] +set_clock_groups -asynchronous -group FMC_CLK1_M2C_P[0] + +# ------------------------------------------------------------------- +# Override Differential Pairs' IOSTANDARD +# ------------------------------------------------------------------- +set_property IOSTANDARD LVDS [get_ports FMC_CLK0_M2C_P[0]] +set_property IOSTANDARD LVDS [get_ports FMC_CLK1_M2C_P[0]] + diff --git a/modules/fmc_x4sfp/fmc_x4sfp.block.ini b/modules/fmc_x4sfp/fmc_x4sfp.block.ini index 0d5d49c42..6e9e5c677 100644 --- a/modules/fmc_x4sfp/fmc_x4sfp.block.ini +++ b/modules/fmc_x4sfp/fmc_x4sfp.block.ini @@ -3,6 +3,7 @@ description: HPC-FMC card with 4 SFP+ ports entity: fmc_x4sfp type: io interfaces: FMC +constraints: const/fmc_x4sfp.xdc const/fmc_x4sfp_impl.xdc extra_interface: fmc_mgt: mgt 4 [FMC_PRSNT] @@ -12,3 +13,20 @@ description: FMC present 1: FMC Connected 2: FMC_PRSNT not supported +[FMC_I2C_MUX] +description: MUX selector for FMC I2C +type: param enum +0: SFP1 +1: SFP2 +2: SFP3 +3: SFP4 +4: Si570 + +[FMC_CLK0] +type: read +description: FMC CLK0 clock freq (if supported) + +[FMC_CLK1] +type: read +description: FMC CLK1 clock freq (if supported) + diff --git a/modules/fmc_x4sfp/hdl/fmc_x4sfp_wrapper.vhd b/modules/fmc_x4sfp/hdl/fmc_x4sfp_wrapper.vhd index 34f8e4e37..d156e1c1b 100644 --- a/modules/fmc_x4sfp/hdl/fmc_x4sfp_wrapper.vhd +++ b/modules/fmc_x4sfp/hdl/fmc_x4sfp_wrapper.vhd @@ -1,5 +1,6 @@ library ieee; use ieee.std_logic_1164.all; +use ieee.numeric_std.all; use work.support.all; use work.top_defines.all; @@ -29,7 +30,17 @@ end fmc_x4sfp_wrapper; architecture rtl of fmc_x4sfp_wrapper is +constant NUM_I2C_CHANS : natural := 5; + signal FMC_PRSNT_DW : std_logic_vector(31 downto 0); +signal FMC_I2C_MUX_VEC : std_logic_vector(31 downto 0); +signal FMC_I2C_MUX : integer range 0 to NUM_I2C_CHANS-1; +signal FMC_CLK0_M2C : std_logic; +signal FMC_CLK1_M2C : std_logic; +signal FREQ_VAL : std32_array(1 downto 0); +signal test_clocks : std_logic_vector(1 downto 0); +signal FMC_SDA_DEMUX : std_logic_vector(NUM_I2C_CHANS-1 downto 0); +signal FMC_SCL_DEMUX : std_logic_vector(NUM_I2C_CHANS-1 downto 0); begin @@ -37,6 +48,89 @@ begin -- FMC CSR Interface --------------------------------------------------------------------------- FMC_PRSNT_DW <= ZEROS(30) & FMC.FMC_PRSNT; +FMC_I2C_MUX <= to_integer(unsigned(FMC_I2C_MUX_VEC)); + +-- Mux/Demux the SFP I2C for the HiTechGlobal FMC (HTG-FMC-x4-SFP) +-- Note that SFP numbering is reversed wrt to the FMC DP numbering +-- S0 SDA/SCL on LA00_N_CC/LA00_P_CC --- DP3 +-- S1 SDA/SCL on LA01_N_CC/LA01_P_CC --- DP2 +-- S2 SDA/SCL on LA02_N/LA02_P --- DP1 +-- S3 SDA/SCL on LA04_N/LA04_P --- DP0 +-- OSC SDA/SCL on LA05_N/LA05_P +-- OSC_EN on LA03_N and CLK_SEL on LA03_P +-- Note CLK_SEL needs to be set to '0' as incorrectly pulled high on card + +FMC.FMC_LA_P(3) <= '0'; -- CLK_SEL +FMC.FMC_LA_N(3) <= '1'; -- OSC_EN + +FMC.FMC_LA_N(0) <= FMC_SDA_DEMUX(3); +FMC.FMC_LA_P(0) <= FMC_SCL_DEMUX(3); +FMC.FMC_LA_N(1) <= FMC_SDA_DEMUX(2); +FMC.FMC_LA_P(1) <= FMC_SCL_DEMUX(2); +FMC.FMC_LA_N(2) <= FMC_SDA_DEMUX(1); +FMC.FMC_LA_P(2) <= FMC_SCL_DEMUX(1); +FMC.FMC_LA_N(4) <= FMC_SDA_DEMUX(0); +FMC.FMC_LA_P(4) <= FMC_SCL_DEMUX(0); +FMC.FMC_LA_N(5) <= FMC_SDA_DEMUX(4); +FMC.FMC_LA_P(5) <= FMC_SCL_DEMUX(4); + +-- Mux/Demux for FMC I2C + +FMC.FMC_I2C_SDA_in <= FMC_SDA_DEMUX(FMC_I2C_MUX) when + FMC_I2C_MUX < NUM_I2C_CHANS else FMC_SDA_DEMUX(NUM_I2C_CHANS-1); +FMC.FMC_I2C_SCL_in <= FMC_SCL_DEMUX(FMC_I2C_MUX) when + FMC_I2C_MUX < NUM_I2C_CHANS else FMC_SCL_DEMUX(NUM_I2C_CHANS-1); + +FMC_DEMUX_GEN: for chan in 0 to NUM_I2C_CHANS-1 generate + FMC_SDA_DEMUX(chan) <= '0' when + FMC_I2C_MUX = chan and FMC.FMC_I2C_SDA_tri = '0' and FMC.FMC_I2C_SDA_out = '0' + else 'Z'; + FMC_SCL_DEMUX(chan) <= '0' when + FMC_I2C_MUX = chan and FMC.FMC_I2C_SCL_tri = '0' and FMC.FMC_I2C_SCL_out = '0' + else 'Z'; +end generate; + + +--------------------------------------------------------------------------- +-- FMC Mezzanine Clocks +--------------------------------------------------------------------------- +IBUFGDS_CLK0 : IBUFGDS +generic map ( + DIFF_TERM => TRUE, + IOSTANDARD => "LVDS" +) +port map ( + O => FMC_CLK0_M2C, + I => FMC.FMC_CLK0_M2C_P, + IB => FMC.FMC_CLK0_M2C_N +); + +IBUFGDS_CLK1 : IBUFGDS +generic map ( + DIFF_TERM => TRUE, + IOSTANDARD => "LVDS" +) +port map ( + O => FMC_CLK1_M2C, + I => FMC.FMC_CLK1_M2C_P, + IB => FMC.FMC_CLK1_M2C_N +); + +--------------------------------------------------------------------------- +-- FMC Clocks Frequency Counter +--------------------------------------------------------------------------- + +test_clocks(0) <= FMC_CLK0_M2C; +test_clocks(1) <= FMC_CLK1_M2C; + +freq_counter_inst : entity work.freq_counter +generic map ( NUM => 2) +port map ( + refclk => clk_i, + reset => reset_i, + test_clocks => test_clocks, + freq_out => FREQ_VAL +); fmc_x4sfp_inst : entity work.fmc_x4sfp_ctrl port map( @@ -46,6 +140,9 @@ port map( pos_bus_i => pos_bus_i, -- Block Parameters FMC_PRSNT => FMC_PRSNT_DW, + FMC_I2C_MUX => FMC_I2C_MUX_VEC, + FMC_CLK0 => FREQ_VAL(0), + FMC_CLK1 => FREQ_VAL(1), -- Memory Bus Interface read_strobe_i => read_strobe_i, read_address_i => read_address_i(BLK_AW-1 downto 0), @@ -58,3 +155,4 @@ port map( write_ack_o => write_ack_o ); end rtl; + diff --git a/modules/sfp_panda_sync/hdl/sfp_panda_sync_wrapper.vhd b/modules/sfp_panda_sync/hdl/sfp_panda_sync_wrapper.vhd index d26c437c7..ac81a4d7a 100644 --- a/modules/sfp_panda_sync/hdl/sfp_panda_sync_wrapper.vhd +++ b/modules/sfp_panda_sync/hdl/sfp_panda_sync_wrapper.vhd @@ -78,6 +78,7 @@ signal POSOUT4 : std_logic_vector(31 downto 0); signal BITOUT : std_logic_vector(7 downto 0); signal LINKUP : std_logic_vector(31 downto 0); signal SYNC_RESET : std_logic; +signal MGT_RESET : std_logic; signal TXN : std_logic; signal TXP : std_logic; signal health : std_logic_vector(31 downto 0); @@ -197,6 +198,7 @@ sfp_panda_sync_mgt_interface_inst : entity work.sfp_panda_sync_mgt_interface port map( GTREFCLK_i => MGT.GTREFCLK, SYNC_RESET_i => SYNC_RESET, + MGT_RESET_i => MGT_RESET, sysclk_i => clk_i, rxp_i => MGT.RXP_IN, rxn_i => MGT.RXN_IN, @@ -235,6 +237,8 @@ sfp_panda_sync_ctrl_inst : entity work.sfp_panda_sync_ctrl IN_SYNC_RESET_wstb => SYNC_RESET, IN_HEALTH => health, IN_ERR_CNT => err_cnt_smpld, + OUT_MGT_RESET => open, + OUT_MGT_RESET_wstb => MGT_RESET, OUT_BIT1_from_bus => BITOUT1, OUT_BIT2_from_bus => BITOUT2, OUT_BIT3_from_bus => BITOUT3, diff --git a/modules/sfp_panda_sync/hdl_zynq/sfp_panda_sync_mgt_interface.vhd b/modules/sfp_panda_sync/hdl_zynq/sfp_panda_sync_mgt_interface.vhd index cad826df3..6fa07c91e 100644 --- a/modules/sfp_panda_sync/hdl_zynq/sfp_panda_sync_mgt_interface.vhd +++ b/modules/sfp_panda_sync/hdl_zynq/sfp_panda_sync_mgt_interface.vhd @@ -13,6 +13,7 @@ entity sfp_panda_sync_mgt_interface is port (GTREFCLK_i : in std_logic; SYNC_RESET_i : in std_logic; + MGT_RESET_i : in std_logic; sysclk_i : in std_logic; rxp_i : in std_logic; rxn_i : in std_logic; @@ -53,7 +54,8 @@ signal GT0_RX_FSM_RESET_DONE_sync : std_logic; signal gt0_txresetdone_sync : std_logic; signal gt0_rxresetdone_sync : std_logic; signal init_rst : std_logic; -signal mgt_rst : std_logic; +signal mgt_soft_rst : std_logic; +signal mgt_hard_rst : std_logic; -- PICXO signals @@ -140,7 +142,8 @@ begin end if; end process; -mgt_rst <= SYNC_RESET_i or init_rst; +mgt_soft_rst <= SYNC_RESET_i or init_rst; +mgt_hard_rst <= MGT_RESET_i or init_rst; -- ####################################################################################### -- -- clks @@ -155,8 +158,8 @@ mgt_rst <= SYNC_RESET_i or init_rst; sfp_panda_sync_i : entity work.sfp_panda_sync port map( SYSCLK_IN => GTREFCLK_i, - SOFT_RESET_TX_IN => init_rst, - SOFT_RESET_RX_IN => mgt_rst, + SOFT_RESET_TX_IN => mgt_hard_rst, + SOFT_RESET_RX_IN => mgt_soft_rst, DONT_RESET_ON_DATA_ERROR_IN => '0', GT0_TX_FSM_RESET_DONE_OUT => GT0_TX_FSM_RESET_DONE, GT0_RX_FSM_RESET_DONE_OUT => GT0_RX_FSM_RESET_DONE, diff --git a/modules/sfp_panda_sync/hdl_zynqmp/sfp_panda_sync_mgt_interface.vhd b/modules/sfp_panda_sync/hdl_zynqmp/sfp_panda_sync_mgt_interface.vhd index 8002e8e7c..1d09bfc43 100644 --- a/modules/sfp_panda_sync/hdl_zynqmp/sfp_panda_sync_mgt_interface.vhd +++ b/modules/sfp_panda_sync/hdl_zynqmp/sfp_panda_sync_mgt_interface.vhd @@ -12,6 +12,7 @@ entity sfp_panda_sync_mgt_interface is port ( GTREFCLK_i : in std_logic; SYNC_RESET_i : in std_logic; + MGT_RESET_i : in std_logic; sysclk_i : in std_logic; rxp_i : in std_logic; rxn_i : in std_logic; @@ -99,7 +100,8 @@ signal RX_PMA_RESET_DONE_OUT_sync : std_logic; signal gtwiz_reset_rx_done_out_sync : std_logic; signal gtwiz_reset_tx_done_out_sync : std_logic; signal init_rst : std_logic; -signal mgt_rst : std_logic; +signal mgt_soft_rst : std_logic; +signal mgt_hard_rst : std_logic; signal rxctrl0_int : STD_LOGIC_VECTOR(15 DOWNTO 0); signal rxctrl1_int : STD_LOGIC_VECTOR(15 DOWNTO 0); @@ -171,7 +173,8 @@ begin end if; end process; -mgt_rst <= SYNC_RESET_i or init_rst; +mgt_soft_rst <= SYNC_RESET_i or init_rst; +mgt_hard_rst <= MGT_RESET_i or init_rst; --====================================================================== -- CORE INSTANCE @@ -191,11 +194,11 @@ sfp_panda_sync_us_i : sfp_panda_sync_us gtwiz_userclk_rx_usrclk2_out => open, gtwiz_userclk_rx_active_out => open, gtwiz_reset_clk_freerun_in(0) => sysclk_i, - gtwiz_reset_all_in(0) => init_rst, + gtwiz_reset_all_in(0) => mgt_hard_rst, gtwiz_reset_tx_pll_and_datapath_in(0) => '0', gtwiz_reset_tx_datapath_in(0) => '0', gtwiz_reset_rx_pll_and_datapath_in(0) => '0', - gtwiz_reset_rx_datapath_in(0) => mgt_rst, + gtwiz_reset_rx_datapath_in(0) => mgt_soft_rst, gtwiz_reset_rx_cdr_stable_out => open, gtwiz_reset_tx_done_out(0) => gtwiz_reset_tx_done_out, gtwiz_reset_rx_done_out(0) => gtwiz_reset_rx_done_out, diff --git a/modules/sfp_panda_sync/sfp_panda_sync.block.ini b/modules/sfp_panda_sync/sfp_panda_sync.block.ini index fb8115116..2287ca162 100644 --- a/modules/sfp_panda_sync/sfp_panda_sync.block.ini +++ b/modules/sfp_panda_sync/sfp_panda_sync.block.ini @@ -77,6 +77,10 @@ description: Error status type: read uint description: Number of not-in-table or disparity errors +[OUT.MGT_RESET] +type: write action +description: MGT hard reset + [OUT.BIT1] type: bit_mux description: SFP panda sync bit 1 output diff --git a/modules/sfp_panda_sync/sfp_panda_sync_us.block.ini b/modules/sfp_panda_sync/sfp_panda_sync_us.block.ini index d169f09f9..c763818e8 100644 --- a/modules/sfp_panda_sync/sfp_panda_sync_us.block.ini +++ b/modules/sfp_panda_sync/sfp_panda_sync_us.block.ini @@ -77,6 +77,10 @@ description: Error status type: read uint description: Number of not-in-table or disparity errors +[OUT.MGT_RESET] +type: write action +description: MGT hard reset + [OUT.BIT1] type: bit_mux description: SFP panda sync bit 1 output diff --git a/modules/us_system/hdl/us_system_top.vhd b/modules/us_system/hdl/us_system_top.vhd index 303de9f07..c30acaaff 100644 --- a/modules/us_system/hdl/us_system_top.vhd +++ b/modules/us_system/hdl/us_system_top.vhd @@ -10,6 +10,7 @@ generic (NUM : natural := 1); port ( -- Clock and Reset clk_i : in std_logic; + sys_i2c_mux_o : out std_logic; -- Memory Bus Interface read_strobe_i : in std_logic; read_address_i : in std_logic_vector(PAGE_AW-1 downto 0); @@ -24,14 +25,20 @@ port ( end us_system_top; architecture rtl of us_system_top is + +signal sys_i2c_mux : std_logic_vector(31 downto 0); + begin +sys_i2c_mux_o <= sys_i2c_mux(0); + us_system_ctrl_inst : entity work.us_system_ctrl port map( clk_i => clk_i, reset_i => '0', bit_bus_i => (others => '0'), pos_bus_i => (others => (others => '0')), + SYS_I2C_MUX => sys_i2c_mux, -- Memory Bus Interface read_strobe_i => read_strobe_i, read_address_i => read_address_i(BLK_AW-1 downto 0), diff --git a/modules/us_system/us_system.block.ini b/modules/us_system/us_system.block.ini index 5de3e50bb..bc8034a63 100644 --- a/modules/us_system/us_system.block.ini +++ b/modules/us_system/us_system.block.ini @@ -3,6 +3,12 @@ description: System Block for Zynq UltraScale+ series entity: us_system extension: +[SYS_I2C_MUX] +description: MUX selector for FPGA I2C (if applicable) +type: param enum +0: Top-level FPGA pins +1: FMC + [TEMP_PS] description: On-board CPU temperature type: read scalar diff --git a/targets/xu5_st1/bd/panda_ps.tcl b/targets/xu5_st1/bd/panda_ps.tcl index 646348ff4..10b3db523 100644 --- a/targets/xu5_st1/bd/panda_ps.tcl +++ b/targets/xu5_st1/bd/panda_ps.tcl @@ -269,6 +269,8 @@ proc create_root_design { parentCell } { CONFIG.WUSER_WIDTH {0} \ ] $S_AXI_HP1 + set IIC_FPGA [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 IIC_FPGA ] + # Create ports set FCLK_CLK0 [ create_bd_port -dir O -type clk FCLK_CLK0 ] @@ -798,7 +800,7 @@ MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#MDIO 0 CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100.000000} \ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \ @@ -1017,7 +1019,8 @@ MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#MDIO 0 CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 10 .. 11} \ CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \ - CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C1__PERIPHERAL__IO {EMIO} \ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ @@ -1154,7 +1157,7 @@ SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsyste \ CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \ CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \ - CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;0|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;0|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;0|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;1|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\ + CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;0|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;0|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;1|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\ Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\ \ CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \ @@ -1302,6 +1305,7 @@ Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD05000 connect_bd_intf_net -intf_net S_AXI_HP1_1 [get_bd_intf_ports S_AXI_HP1] [get_bd_intf_pins smartconnect_1/S01_AXI] connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI] connect_bd_intf_net -intf_net smartconnect_1_M00_AXI [get_bd_intf_pins smartconnect_1/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD] + connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_IIC_1 [get_bd_intf_ports IIC_FPGA] [get_bd_intf_pins zynq_ultra_ps_e_0/IIC_1] connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins smartconnect_0/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD] # Create port connections diff --git a/targets/xu5_st1/const/xu5_st1-pins_impl.xdc b/targets/xu5_st1/const/xu5_st1-pins_impl.xdc index 0a6cc4667..d9409e8d7 100644 --- a/targets/xu5_st1/const/xu5_st1-pins_impl.xdc +++ b/targets/xu5_st1/const/xu5_st1-pins_impl.xdc @@ -87,6 +87,10 @@ set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18 } [get_ports {FMC_CLK set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS18 } [get_ports {FMC_CLK1_M2C_N[0]}] set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18 } [get_ports {FMC_CLK1_M2C_P[0]}] +# I2C FPGA +set_property -dict {PACKAGE_PIN AG10 IOSTANDARD LVCMOS18 } [get_ports {I2C_SCL_FPGA}] +set_property -dict {PACKAGE_PIN AH10 IOSTANDARD LVCMOS18 } [get_ports {I2C_SDA_FPGA}] + # MGT Reference Clocks set_property PACKAGE_PIN Y5 [get_ports GTXCLK0_N] set_property PACKAGE_PIN Y6 [get_ports GTXCLK0_P] diff --git a/targets/xu5_st1/hdl/xu5_st1_top.vhd b/targets/xu5_st1/hdl/xu5_st1_top.vhd index f1d2a5510..969fcb399 100644 --- a/targets/xu5_st1/hdl/xu5_st1_top.vhd +++ b/targets/xu5_st1/hdl/xu5_st1_top.vhd @@ -53,7 +53,10 @@ port ( FMC_CLK0_M2C_N : inout std_logic_vector(NUM_FMC-1 downto 0) := (others => 'Z'); FMC_CLK1_M2C_P : in std_logic_vector(NUM_FMC-1 downto 0); - FMC_CLK1_M2C_N : in std_logic_vector(NUM_FMC-1 downto 0) + FMC_CLK1_M2C_N : in std_logic_vector(NUM_FMC-1 downto 0); + -- I2C FPGA + I2C_SCL_FPGA : inout std_logic; + I2C_SDA_FPGA : inout std_logic ); end xu5_st1_top; @@ -145,6 +148,14 @@ signal write_address : std_logic_vector(PAGE_AW-1 downto 0); signal write_data : std_logic_vector(31 downto 0); signal write_ack : std_logic_vector(MOD_COUNT-1 downto 0) := (others => '1'); +-- I2C FPGA +signal IIC_FPGA_sda_in : std_logic; +signal IIC_FPGA_sda_out : std_logic; +signal IIC_FPGA_sda_tri : std_logic; +signal IIC_FPGA_scl_in : std_logic; +signal IIC_FPGA_scl_out : std_logic; +signal IIC_FPGA_scl_tri : std_logic; +signal SYS_I2C_MUX : std_logic; -- Top Level Signals signal bit_bus : bit_bus_t := (others => '0'); @@ -231,6 +242,13 @@ port map ( PL_CLK => FCLK_CLK0, FCLK_RESET0_N => FCLK_RESET0_N, + IIC_FPGA_scl_i => IIC_FPGA_scl_in, + IIC_FPGA_scl_o => IIC_FPGA_scl_out, + IIC_FPGA_scl_t => IIC_FPGA_scl_tri, + IIC_FPGA_sda_i => IIC_FPGA_sda_in, + IIC_FPGA_sda_o => IIC_FPGA_sda_out, + IIC_FPGA_sda_t => IIC_FPGA_sda_tri, + IRQ_F2P => IRQ_F2P, M00_AXI_araddr => M00_AXI_araddr, @@ -543,7 +561,8 @@ port map( us_system_top_inst : entity work.us_system_top port map ( - clk_i => FCLK_CLK0, + clk_i => FCLK_CLK0, + sys_i2c_mux_o => SYS_I2C_MUX, read_strobe_i => read_strobe(US_SYSTEM_CS), read_address_i => read_address, read_data_o => read_data(US_SYSTEM_CS), @@ -555,5 +574,17 @@ port map ( write_ack_o => write_ack(US_SYSTEM_CS) ); +-- Mux/Demux for FPGA I2C +IIC_FPGA_sda_in <= I2C_SDA_FPGA when SYS_I2C_MUX = '0' else FMC.FMC_ARR(0).FMC_I2C_SDA_in; +IIC_FPGA_scl_in <= I2C_SCL_FPGA when SYS_I2C_MUX = '0' else FMC.FMC_ARR(0).FMC_I2C_SCL_in; + +I2C_SDA_FPGA <= '0' when (SYS_I2C_MUX = '0' and IIC_FPGA_sda_tri = '0' and IIC_FPGA_sda_out = '0') else 'Z'; +I2C_SCL_FPGA <= '0' when (SYS_I2C_MUX = '0' and IIC_FPGA_scl_tri = '0' and IIC_FPGA_scl_out = '0') else 'Z'; + +FMC.FMC_ARR(0).FMC_I2C_SDA_out <= IIC_FPGA_sda_out; +FMC.FMC_ARR(0).FMC_I2C_SDA_tri <= IIC_FPGA_sda_tri when SYS_I2C_MUX = '1' else '1'; +FMC.FMC_ARR(0).FMC_I2C_SCL_out <= IIC_FPGA_scl_out; +FMC.FMC_ARR(0).FMC_I2C_SCL_tri <= IIC_FPGA_scl_tri when SYS_I2C_MUX = '1' else '1'; + end rtl;