From b8a3fdda27d261e3ebb1f302017bea2bc4286cc5 Mon Sep 17 00:00:00 2001
From: Ben Levinsky <ben.levinsky@amd.com>
Date: Tue, 30 May 2023 06:54:35 -0700
Subject: [PATCH] examples: generic: zynqmp_amp_demo: enable Demo configuration
 vars to be dynamic

Allow Shared memory, TTC and IPI values to be set dynamically. This will enable
the demos to be run on different platforms.

Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
---
 .../generic/zynqmp_r5/zynqmp_amp_demo/common.h       | 12 +++++++++++-
 .../generic/zynqmp_r5/zynqmp_amp_demo/sys_init.c     | 10 ++++++++++
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/examples/system/generic/zynqmp_r5/zynqmp_amp_demo/common.h b/examples/system/generic/zynqmp_r5/zynqmp_amp_demo/common.h
index ece552c1..eded622d 100644
--- a/examples/system/generic/zynqmp_r5/zynqmp_amp_demo/common.h
+++ b/examples/system/generic/zynqmp_r5/zynqmp_amp_demo/common.h
@@ -26,9 +26,18 @@
 
 /* Devices names */
 #define BUS_NAME        "generic"
+
+#ifndef IPI_DEV_NAME
 #define IPI_DEV_NAME    "ff310000.ipi"
+#endif
+
+#ifndef SHM_DEV_NAME
 #define SHM_DEV_NAME    "3ed80000.shm"
+#endif
+
+#ifndef TTC_DEV_NAME
 #define TTC_DEV_NAME    "ff110000.ttc"
+#endif
 
 /* IPI registers offset */
 #define IPI_TRIG_OFFSET 0x0  /* IPI trigger reg offset */
@@ -38,8 +47,9 @@
 #define IPI_IER_OFFSET  0x18 /* IPI interrupt enable reg offset */
 #define IPI_IDR_OFFSET  0x1C /* IPI interrupt disable reg offset */
 
+#ifndef IPI_MASK
 #define IPI_MASK        0x1000000 /* IPI mask for kick from APU.
-				     We use PL0 IPI in this demo. */
+#endif				     We use PL0 IPI in this demo. */
 
 /* TTC counter offsets */
 #define XTTCPS_CLK_CNTRL_OFFSET 0x0  /* TTC counter clock control reg offset */
diff --git a/examples/system/generic/zynqmp_r5/zynqmp_amp_demo/sys_init.c b/examples/system/generic/zynqmp_r5/zynqmp_amp_demo/sys_init.c
index 0915ebdc..c2107575 100644
--- a/examples/system/generic/zynqmp_r5/zynqmp_amp_demo/sys_init.c
+++ b/examples/system/generic/zynqmp_r5/zynqmp_amp_demo/sys_init.c
@@ -29,11 +29,21 @@
 
 #define INTC_DEVICE_ID		XPAR_SCUGIC_0_DEVICE_ID
 
+#ifndef IPI_IRQ_VECT_ID
 #define IPI_IRQ_VECT_ID         65
+#endif
 
+#ifndef SHM_BASE_ADDR
 #define SHM_BASE_ADDR   0x3ED80000
+#endif
+
+#ifndef TTC0_BASE_ADDR
 #define TTC0_BASE_ADDR  0xFF110000
+#endif
+
+#ifndef IPI_BASE_ADDR
 #define IPI_BASE_ADDR   0xFF310000
+#endif
 
 /* Default generic I/O region page shift */
 /* Each I/O region can contain multiple pages.