Merge Axi_r/wDatapump, StructReader/Write, ArrayItemGetter and other bus frame logic

[Nic30]

The problem is that the DMA logic for bus interfaces is fragmented over multiple components which do something similar, but in a different way. There is a problem is also support for out-of-order which complicates the things.
Because of this we need a single implementation of read and write component (separately) which will be easily configurable.

Expected functionality:

(from Axi_r/wDatapump)

• If data is larger than max frame on target bus split it on multiple frames on bus but act as a single frame on driver side

(from StructReader/Writer)

• describe the data using data type + transaction template (not just max frame len) because we need this for alignment analysis and frame split analysis
• this means we should be also able to describe dense data structures (padding)

(from ArrayItemGetter, AddrDataHs_to_Axi)

• if data is smaller than bus word, roundup the address and construct the part selection logic for data word

(from StructReader/Writer and ArrayItemGetter)

• ability to specify also the alignment of the start of the data
• ability to automatically generate padding to best fit for data smaller and larger than the bus word

(from RamAsHs)

• support for latency synchronized buses like BRAM port or some versions of Avalon-MM

It is also expected that the implementation will be just some kind of manager which will generate required logic (that means that this will not be an independent component.) The reason for this is to allow conditional modification of local memory resources in current component without need for generating a complex IO of bus connector.