VHDL/Verilog to schematic

[pidgeon777]

Hello, how could I use your schematic viewer to visualize diagrams of VHDL/Verilog hierarchical entities starting from source files?

Thank you and congratulations on your project.

[Nic30]

Hello,

quick answer:
You need to convert VHDL/Verilog to the suitable JSON.

Long answer:
In order to do that you need to parse VHDL/Verilog and perform the complete analysis off the modules etc. I understand that this is like an essential feature. I do have parser partially prepared https://github.com/Nic30/hdlConvertor and I am working on it https://drive.google.com/file/d/1zyegLIf7VaBRyb-ED5vgOMmHzW4SRZLp/view (the hwtGraph library is the library I am using to generate input JSON) however I am just a single man and this project is not directly related to my PhD thesis.

But there is an another problem with the raw VHDL/Verilog:

• how you recognize the interfaces from VHDL/Verilog (Axi4, Axi4-stream, Avalon,...).
  • you can use regular expressions to match the names of the interfaces however the things gets complicated very quickly
  • if you do not extract large interfaces (like Axi4, Avalon-mm) the circuit will be very large and ugly...

[pidgeon777]

Thanks, yours seems to be a really interesting and ambitious project.

I understand that there might be difficulties when parsing the interfaces, but maybe that for simpler projects (hierarchical entities with subcomponents and packages) there would be more chance to obtain some nice schematics?

Anyway, pardon me, if I understood correctly it wouldn't be possible at the moment to do the above because actually only the parser is implemented, right?

Thank you again.

[Nic30]

The gui can display anything. The parsers which can parse the full informations about the connections from the hdl does exists. However there is not a final piece of the sw which converts the parsed data to json for this library.

As I mentioned It will be finished in cca 2 months. However if you thinking about implementing the convertor your self I can help (it should take like 1-2 days). The format is relatively easy and more advanced features which I described ablove are indeed optional. However the format is described only by the classes in the code and there is actually no wiki about it.

[pidgeon777]

However the format is described only by the classes in the code and there is actually no wiki about it.

Could you please explain more about this, please? For example, what do you exactly mean with classes?

As I mentioned It will be finished in cca 2 months. However if you thinking about implementing the convertor your self I can help (it should take like 1-2 days).

Well, that is exactly what I wanted to do, it would be great if you could help.

To do some testing, I found this project which could do the job for us:

https://opencores.org/projects/sap

It consists of a simple implementation of a 8-bit uP, all in VHDL, testbench included. I think that displaying a hierarchical and possibly expandable schematic of that project would be good enough, to begin with.

If you don't have a OpenCores account I could upload the project archive for you, just let me know.

[Nic30]

For example, what do you exactly mean with classes?

https://github.com/Nic30/hwtGraph/tree/master/hwtGraph/elk/containers

The hdlConvertor library in this branch can parse the hdl languages. However now it parse body only of verilog modules and the body of vhdl architectures will be parsed end of this week.

For input arbiter.v it provides python dictionary which is basically json arbiter.zip

Now it is required to convert this json format to format for the d3-hwschematic.

The output of the hdlConvertor is maybe to verbose I mean maybe it will be required to minifi it somehow in future.

The output of the hdlCovertor is currently described by toJson() methods of the hdlObjects classes.

The shape of the node is currently resolved by it's name. If the renderer recognizes the name of the component https://github.com/Nic30/d3-hwschematic/blob/master/src/node_renderers/muxNode.js#L26 the renderer is used to draw a node.

https://opencores.org/projects/sap

Good, it is also the question how we deal with non synthesisable code constructs. And how correct warning/error messages should look like.

Also if you find something lets say too complicated just let me know about this so I can remove/rewrite/document this thing.