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Output Queues
Output Queues
v1.0.0
IP core (HW)
hw/lib/std/output_queues_v1_0_0/
AXI4-Stream
AXI-Lite
S_AXIS: Slave AXI4-Stream bus, Variable width
M_AXIS_0: Master AXI4-Stream bus, Variable width
M_AXIS_1: Master AXI4-Stream bus, Variable width
M_AXIS_2: Master AXI4-Stream bus, Variable width
M_AXIS_3: Master AXI4-Stream bus, Variable width
M_AXIS_4: Master AXI4-Stream bus, Variable width
S_AXI: Slave AXI4-Lite
C_M_AXIS_DATA_WIDTH: Data width of the master AXI4-Stream data bus.
C_S_AXIS_DATA_WIDTH: Data width of the slave AXI4-Stream data bus.
C_M_AXIS_TUSER_WIDTH: Data width of the master TUSER bus.
C_S_AXIS_TUSER_WIDTH: Data width of the slave TUSER bus.
This module uses register infrastructure Ver 1.00, please refer to here for more details.
0x0 : ID - Block ID
0x4 : VERSION - Block Version
0x8 : FLIP - Returns the negative value of a written register
0xC: DEBUG - Debug register, returns the written value plus a preconfigured value
0x10 : PKTIN - Total number of incoming packets
0x14: PKTOUT - Total number of outgoing packets
0x18+0x1C*i: PKTSTOREDPORTi - Port i, stored Packets
0x1C+0x1C*i: BYTESSTOREDPORTi - Port i, stored bytes
0x20+0x1C*i: PKTREMOVEDPORTi - Port i, removed (sent to port) packets
0x24+0x1C*i: BYTESREMOVEDPORTi - Port i, removed (sent to port) bytes
0x28+0x1C*i: PKTDROPPEDPORTi- Port i, dropped packets
0x2C+0x1C*i: BYTESDROPPEDPORTi- Port i, dropped bytes
0x30+0x1C*i: PKTINQUEUEPORTi - Port i, packets in queue
This block implements BRAM-based output queues. It stores per-port (4x SFP+ and 1x PCIe) the outgoing packets and hands over the per-port packets to the relevant 10G interface.
The output queues have been implemented with no back pressure. Possible drops to the pipeline can happen either to the interfaces core or to the output queues. With implemented back pressure to this core, drops should happen only to the interfaces.