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vivado.log
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vivado.log
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#-----------------------------------------------------------
# Vivado v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Mon May 27 07:26:12 2024
# Process ID: 3304
# Current directory: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent27020 D:\SUSTech\02Sophomore\DigitalDesign\CS214-Project-CPU-debug\CS214-Project-CPU.xpr
# Log file: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/vivado.log
# Journal file: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug\vivado.jou
#-----------------------------------------------------------
start_gui
open_project D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.xpr
INFO: [Project 1-313] Project file moved from '/home/ubuntu/Jaredan/CS214/Project/verilog/project_3' since last save.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2017.4/data/ip'.
update_compile_order -fileset sources_1
set_property -dict [list CONFIG.CLKOUT3_USED {true} CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {10.000} CONFIG.MMCM_DIVCLK_DIVIDE {10} CONFIG.MMCM_CLKOUT2_DIVIDE {60} CONFIG.NUM_OUT_CLKS {3} CONFIG.CLKOUT3_JITTER {884.240} CONFIG.CLKOUT3_PHASE_ERROR {871.302}] [get_ips clk_wiz]
generate_target all [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'clk_wiz'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'clk_wiz'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'clk_wiz'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'clk_wiz'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'clk_wiz'...
catch { config_ip_cache -export [get_ips -all clk_wiz] }
export_ip_user_files -of_objects [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci] -no_script -sync -force -quiet
reset_run clk_wiz_synth_1
launch_runs -jobs 12 clk_wiz_synth_1
[Mon May 27 07:33:35 2024] Launched clk_wiz_synth_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/clk_wiz_synth_1/runme.log
export_simulation -of_objects [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci] -directory D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/sim_scripts -ip_user_files_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files -ipstatic_source_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/modelsim} {questa=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/questa} {riviera=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/riviera} {activehdl=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
set_property ip_repo_paths {{D:/SUSTech/02Sophomore/03 Spring Semester/CS214 计算机组成原理（H）/Labs/Lab 12/SEU_CSE_507_user_uart_bmpg_1.3}} [current_project]
update_ip_catalog
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/SUSTech/02Sophomore/03 Spring Semester/CS214 计算机组成原理（H）/Labs/Lab 12/SEU_CSE_507_user_uart_bmpg_1.3'.
create_ip -name uart_bmpg -vendor SEU_CSE_507 -library user -version 1.3 -module_name uart_bmpg_0 -dir d:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip
generate_target {instantiation_template} [get_files d:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/uart_bmpg_0/uart_bmpg_0.xci]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'uart_bmpg_0'...
generate_target all [get_files d:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/uart_bmpg_0/uart_bmpg_0.xci]
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'uart_bmpg_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'uart_bmpg_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'uart_bmpg_0'...
catch { config_ip_cache -export [get_ips -all uart_bmpg_0] }
export_ip_user_files -of_objects [get_files d:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/uart_bmpg_0/uart_bmpg_0.xci] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] d:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/uart_bmpg_0/uart_bmpg_0.xci]
launch_runs -jobs 12 uart_bmpg_0_synth_1
[Mon May 27 07:38:50 2024] Launched uart_bmpg_0_synth_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/uart_bmpg_0_synth_1/runme.log
export_simulation -of_objects [get_files d:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/uart_bmpg_0/uart_bmpg_0.xci] -directory D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/sim_scripts -ip_user_files_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files -ipstatic_source_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/modelsim} {questa=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/questa} {riviera=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/riviera} {activehdl=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified checkbox.Providing a default widget
WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified checkbox.Providing a default widget
set_property -dict [list CONFIG.Enable_A {Always_Enabled}] [get_ips instr_mem]
generate_target all [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/instr_mem_1/instr_mem.xci]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'instr_mem'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'instr_mem'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'instr_mem'...
INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'instr_mem'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'instr_mem'...
catch { config_ip_cache -export [get_ips -all instr_mem] }
export_ip_user_files -of_objects [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/instr_mem_1/instr_mem.xci] -no_script -sync -force -quiet
reset_run instr_mem_synth_1
launch_runs -jobs 12 instr_mem_synth_1
[Mon May 27 08:03:29 2024] Launched instr_mem_synth_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/instr_mem_synth_1/runme.log
export_simulation -of_objects [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/instr_mem_1/instr_mem.xci] -directory D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/sim_scripts -ip_user_files_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files -ipstatic_source_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/modelsim} {questa=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/questa} {riviera=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/riviera} {activehdl=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified checkbox.Providing a default widget
WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified checkbox.Providing a default widget
WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified checkbox.Providing a default widget
WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified checkbox.Providing a default widget
set_property -dict [list CONFIG.Enable_A {Always_Enabled}] [get_ips dmem_uram]
generate_target all [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/dmem_uram_1/dmem_uram.xci]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'dmem_uram'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'dmem_uram'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'dmem_uram'...
INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'dmem_uram'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'dmem_uram'...
catch { config_ip_cache -export [get_ips -all dmem_uram] }
export_ip_user_files -of_objects [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/dmem_uram_1/dmem_uram.xci] -no_script -sync -force -quiet
reset_run dmem_uram_synth_1
launch_runs -jobs 12 dmem_uram_synth_1
[Mon May 27 08:19:27 2024] Launched dmem_uram_synth_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/dmem_uram_synth_1/runme.log
export_simulation -of_objects [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/dmem_uram_1/dmem_uram.xci] -directory D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/sim_scripts -ip_user_files_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files -ipstatic_source_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/modelsim} {questa=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/questa} {riviera=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/riviera} {activehdl=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 12
[Mon May 27 08:41:53 2024] Launched synth_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/synth_1/runme.log
[Mon May 27 08:41:53 2024] Launched impl_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/runme.log
WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified checkbox.Providing a default widget
WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified checkbox.Providing a default widget
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:
****** Xilinx hw_server v2017.4
**** Build date : Dec 15 2017-21:08:27
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/1234-tulA
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
current_hw_device [get_hw_devices xc7a35t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
close_hw
close_hw: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1829.195 ; gain = 0.301
set_property -dict [list CONFIG.RESET_TYPE {ACTIVE_HIGH} CONFIG.RESET_PORT {reset}] [get_ips clk_wiz]
generate_target all [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'clk_wiz'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'clk_wiz'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'clk_wiz'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'clk_wiz'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'clk_wiz'...
catch { config_ip_cache -export [get_ips -all clk_wiz] }
export_ip_user_files -of_objects [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci] -no_script -sync -force -quiet
reset_run clk_wiz_synth_1
launch_runs -jobs 12 clk_wiz_synth_1
[Mon May 27 08:51:40 2024] Launched clk_wiz_synth_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/clk_wiz_synth_1/runme.log
export_simulation -of_objects [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci] -directory D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/sim_scripts -ip_user_files_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files -ipstatic_source_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/modelsim} {questa=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/questa} {riviera=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/riviera} {activehdl=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 12
[Mon May 27 08:54:39 2024] Launched synth_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/synth_1/runme.log
[Mon May 27 08:54:39 2024] Launched impl_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/runme.log
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:
****** Xilinx hw_server v2017.4
**** Build date : Dec 15 2017-21:08:27
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/1234-tulA
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
current_hw_device [get_hw_devices xc7a35t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
close_hw
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 12
[Mon May 27 09:01:58 2024] Launched synth_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/synth_1/runme.log
[Mon May 27 09:01:58 2024] Launched impl_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/runme.log
WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified checkbox.Providing a default widget
WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified checkbox.Providing a default widget
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:
****** Xilinx hw_server v2017.4
**** Build date : Dec 15 2017-21:08:27
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/1234-tulA
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
current_hw_device [get_hw_devices xc7a35t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 12
[Mon May 27 09:06:44 2024] Launched synth_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/synth_1/runme.log
[Mon May 27 09:06:44 2024] Launched impl_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 12
[Mon May 27 09:12:02 2024] Launched synth_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/synth_1/runme.log
[Mon May 27 09:12:02 2024] Launched impl_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 12
[Mon May 27 09:24:02 2024] Launched synth_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/synth_1/runme.log
[Mon May 27 09:24:02 2024] Launched impl_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
close_hw
close_hw: Time (s): cpu = 00:00:05 ; elapsed = 00:00:18 . Memory (MB): peak = 2007.898 ; gain = 0.000
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 12
[Mon May 27 09:32:25 2024] Launched synth_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/synth_1/runme.log
[Mon May 27 09:32:25 2024] Launched impl_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/runme.log
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 12
[Mon May 27 09:35:05 2024] Launched synth_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/synth_1/runme.log
[Mon May 27 09:35:05 2024] Launched impl_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/runme.log
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:
****** Xilinx hw_server v2017.4
**** Build date : Dec 15 2017-21:08:27
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/1234-tulA
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
current_hw_device [get_hw_devices xc7a35t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
close_hw
close_hw: Time (s): cpu = 00:00:05 ; elapsed = 00:00:20 . Memory (MB): peak = 2037.422 ; gain = 0.000
set_property -dict [list CONFIG.RESET_TYPE {ACTIVE_LOW} CONFIG.RESET_PORT {resetn}] [get_ips clk_wiz]
generate_target all [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'clk_wiz'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'clk_wiz'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'clk_wiz'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'clk_wiz'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'clk_wiz'...
catch { config_ip_cache -export [get_ips -all clk_wiz] }
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP clk_wiz, cache-ID = b55d4da0ef75e7e4; cache size = 23.449 MB.
catch { [ delete_ip_run [get_ips -all clk_wiz] ] }
INFO: [Project 1-386] Moving file 'D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci' from fileset 'clk_wiz' to fileset 'sources_1'.
export_ip_user_files -of_objects [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci]
INFO: [Vivado 12-3453] The given sub-design is up-to-date, no action was taken. If a run is still desired, use the '-force' option for the file:'D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci'
export_simulation -of_objects [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci] -directory D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/sim_scripts -ip_user_files_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files -ipstatic_source_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/modelsim} {questa=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/questa} {riviera=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/riviera} {activehdl=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
update_compile_order -fileset sources_1
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 12
INFO: [Vivado 12-4149] The synthesis checkpoint for IP 'D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci' is already up-to-date
[Mon May 27 10:04:24 2024] Launched synth_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/synth_1/runme.log
[Mon May 27 10:04:24 2024] Launched impl_1...
Run output will be captured here: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/runme.log
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:
****** Xilinx hw_server v2017.4
**** Build date : Dec 15 2017-21:08:27
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/1234-tulA
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
current_hw_device [get_hw_devices xc7a35t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
close_hw_target {localhost:3121/xilinx_tcf/Xilinx/1234-tulA}
INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Xilinx/1234-tulA
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/1234-tulA
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
close_hw_target {localhost:3121/xilinx_tcf/Xilinx/1234-tulA}
INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Xilinx/1234-tulA
close_hw
close_hw: Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 2145.402 ; gain = 0.000