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rtsx_chip.c
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rtsx_chip.c
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/* Driver for Realtek PCI-Express card reader
*
* Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2, or (at your option) any
* later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*
* Author:
* Wei WANG ([email protected])
* Micky Ching ([email protected])
*/
#include <linux/blkdev.h>
#include <linux/kthread.h>
#include <linux/sched.h>
#include <linux/workqueue.h>
#include <linux/vmalloc.h>
#include "rtsx.h"
#include "sd.h"
#include "xd.h"
#include "ms.h"
static void rtsx_calibration(struct rtsx_chip *chip)
{
rtsx_write_phy_register(chip, 0x1B, 0x135E);
wait_timeout(10);
rtsx_write_phy_register(chip, 0x00, 0x0280);
rtsx_write_phy_register(chip, 0x01, 0x7112);
rtsx_write_phy_register(chip, 0x01, 0x7110);
rtsx_write_phy_register(chip, 0x01, 0x7112);
rtsx_write_phy_register(chip, 0x01, 0x7113);
rtsx_write_phy_register(chip, 0x00, 0x0288);
}
void rtsx_enable_card_int(struct rtsx_chip *chip)
{
u32 reg = rtsx_readl(chip, RTSX_BIER);
int i;
for (i = 0; i <= chip->max_lun; i++) {
if (chip->lun2card[i] & XD_CARD)
reg |= XD_INT_EN;
if (chip->lun2card[i] & SD_CARD)
reg |= SD_INT_EN;
if (chip->lun2card[i] & MS_CARD)
reg |= MS_INT_EN;
}
if (chip->hw_bypass_sd)
reg &= ~((u32)SD_INT_EN);
rtsx_writel(chip, RTSX_BIER, reg);
}
void rtsx_enable_bus_int(struct rtsx_chip *chip)
{
u32 reg = 0;
#ifndef DISABLE_CARD_INT
int i;
#endif
reg = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN;
#ifndef DISABLE_CARD_INT
for (i = 0; i <= chip->max_lun; i++) {
dev_dbg(rtsx_dev(chip), "lun2card[%d] = 0x%02x\n",
i, chip->lun2card[i]);
if (chip->lun2card[i] & XD_CARD)
reg |= XD_INT_EN;
if (chip->lun2card[i] & SD_CARD)
reg |= SD_INT_EN;
if (chip->lun2card[i] & MS_CARD)
reg |= MS_INT_EN;
}
if (chip->hw_bypass_sd)
reg &= ~((u32)SD_INT_EN);
#endif
if (chip->ic_version >= IC_VER_C)
reg |= DELINK_INT_EN;
#ifdef SUPPORT_OCP
reg |= OC_INT_EN;
#endif
if (!chip->adma_mode)
reg |= DATA_DONE_INT_EN;
/* Enable Bus Interrupt */
rtsx_writel(chip, RTSX_BIER, reg);
dev_dbg(rtsx_dev(chip), "RTSX_BIER: 0x%08x\n", reg);
}
void rtsx_disable_bus_int(struct rtsx_chip *chip)
{
rtsx_writel(chip, RTSX_BIER, 0);
}
static int rtsx_pre_handle_sdio_old(struct rtsx_chip *chip)
{
int retval;
if (chip->ignore_sd && CHK_SDIO_EXIST(chip)) {
if (chip->asic_code) {
retval = rtsx_write_register(chip, CARD_PULL_CTL5,
0xFF,
MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
if (retval) {
rtsx_trace(chip);
return retval;
}
} else {
retval = rtsx_write_register(chip, FPGA_PULL_CTL,
0xFF,
FPGA_SD_PULL_CTL_EN);
if (retval) {
rtsx_trace(chip);
return retval;
}
}
retval = rtsx_write_register(chip, CARD_SHARE_MODE, 0xFF,
CARD_SHARE_48_SD);
if (retval) {
rtsx_trace(chip);
return retval;
}
/* Enable SDIO internal clock */
retval = rtsx_write_register(chip, 0xFF2C, 0x01, 0x01);
if (retval) {
rtsx_trace(chip);
return retval;
}
retval = rtsx_write_register(chip, SDIO_CTRL, 0xFF,
SDIO_BUS_CTRL | SDIO_CD_CTRL);
if (retval) {
rtsx_trace(chip);
return retval;
}
chip->sd_int = 1;
chip->sd_io = 1;
} else {
chip->need_reset |= SD_CARD;
}
return STATUS_SUCCESS;
}
#ifdef HW_AUTO_SWITCH_SD_BUS
static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip)
{
u8 tmp;
bool sw_bypass_sd = false;
int retval;
if (chip->driver_first_load) {
retval = rtsx_read_register(chip, 0xFE70, &tmp);
if (retval) {
rtsx_trace(chip);
return retval;
}
if (tmp & 0x10)
sw_bypass_sd = true;
} else {
if (chip->sdio_in_charge)
sw_bypass_sd = true;
}
dev_dbg(rtsx_dev(chip), "chip->sdio_in_charge = %d\n",
chip->sdio_in_charge);
dev_dbg(rtsx_dev(chip), "chip->driver_first_load = %d\n",
chip->driver_first_load);
dev_dbg(rtsx_dev(chip), "sw_bypass_sd = %d\n",
sw_bypass_sd);
if (sw_bypass_sd) {
u8 cd_toggle_mask = 0;
retval = rtsx_read_register(chip, TLPTISTAT, &tmp);
if (retval) {
rtsx_trace(chip);
return retval;
}
cd_toggle_mask = 0x10;
if (tmp & cd_toggle_mask) {
/* Disable sdio_bus_auto_switch */
retval = rtsx_write_register(chip, 0xFE70,
0x10, 0x00);
if (retval) {
rtsx_trace(chip);
return retval;
}
retval = rtsx_write_register(chip, TLPTISTAT, 0xFF,
tmp);
if (retval) {
rtsx_trace(chip);
return retval;
}
chip->need_reset |= SD_CARD;
} else {
dev_dbg(rtsx_dev(chip), "Chip inserted with SDIO!\n");
if (chip->asic_code) {
retval = sd_pull_ctl_enable(chip);
if (retval != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
} else {
retval = rtsx_write_register(chip,
FPGA_PULL_CTL,
FPGA_SD_PULL_CTL_BIT | 0x20,
0);
if (retval) {
rtsx_trace(chip);
return retval;
}
}
retval = card_share_mode(chip, SD_CARD);
if (retval != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
/* Enable sdio_bus_auto_switch */
retval = rtsx_write_register(chip, 0xFE70,
0x10, 0x10);
if (retval) {
rtsx_trace(chip);
return retval;
}
chip->chip_insert_with_sdio = 1;
chip->sd_io = 1;
}
} else {
retval = rtsx_write_register(chip, TLPTISTAT, 0x10, 0x10);
if (retval) {
rtsx_trace(chip);
return retval;
}
chip->need_reset |= SD_CARD;
}
return STATUS_SUCCESS;
}
#endif
static int rtsx_reset_aspm(struct rtsx_chip *chip)
{
int ret;
if (chip->dynamic_aspm) {
if (!CHK_SDIO_EXIST(chip) || !CHECK_PID(chip, 0x5288))
return STATUS_SUCCESS;
ret = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF,
chip->aspm_l0s_l1_en);
if (ret != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
return STATUS_SUCCESS;
}
if (CHECK_PID(chip, 0x5208)) {
ret = rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF, 0x3F);
if (ret) {
rtsx_trace(chip);
return ret;
}
}
ret = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en);
if (ret != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
chip->aspm_level[0] = chip->aspm_l0s_l1_en;
if (CHK_SDIO_EXIST(chip)) {
chip->aspm_level[1] = chip->aspm_l0s_l1_en;
ret = rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
0xC0, 0xFF, chip->aspm_l0s_l1_en);
if (ret != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
}
chip->aspm_enabled = 1;
return STATUS_SUCCESS;
}
static int rtsx_enable_pcie_intr(struct rtsx_chip *chip)
{
int ret;
if (!chip->asic_code || !CHECK_PID(chip, 0x5208)) {
rtsx_enable_bus_int(chip);
return STATUS_SUCCESS;
}
if (chip->phy_debug_mode) {
ret = rtsx_write_register(chip, CDRESUMECTL, 0x77, 0);
if (ret) {
rtsx_trace(chip);
return ret;
}
rtsx_disable_bus_int(chip);
} else {
rtsx_enable_bus_int(chip);
}
if (chip->ic_version >= IC_VER_D) {
u16 reg;
ret = rtsx_read_phy_register(chip, 0x00, ®);
if (ret != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
reg &= 0xFE7F;
reg |= 0x80;
ret = rtsx_write_phy_register(chip, 0x00, reg);
if (ret != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
ret = rtsx_read_phy_register(chip, 0x1C, ®);
if (ret != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
reg &= 0xFFF7;
ret = rtsx_write_phy_register(chip, 0x1C, reg);
if (ret != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
}
if (chip->driver_first_load && (chip->ic_version < IC_VER_C))
rtsx_calibration(chip);
return STATUS_SUCCESS;
}
int rtsx_reset_chip(struct rtsx_chip *chip)
{
int retval;
rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr);
rtsx_disable_aspm(chip);
retval = rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 0x00);
if (retval) {
rtsx_trace(chip);
return retval;
}
/* Disable card clock */
retval = rtsx_write_register(chip, CARD_CLK_EN, 0x1E, 0);
if (retval) {
rtsx_trace(chip);
return retval;
}
#ifdef SUPPORT_OCP
/* SSC power on, OCD power on */
if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, 0);
if (retval) {
rtsx_trace(chip);
return retval;
}
} else {
retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN,
MS_OC_POWER_DOWN);
if (retval) {
rtsx_trace(chip);
return retval;
}
}
retval = rtsx_write_register(chip, OCPPARA1, OCP_TIME_MASK,
OCP_TIME_800);
if (retval) {
rtsx_trace(chip);
return retval;
}
retval = rtsx_write_register(chip, OCPPARA2, OCP_THD_MASK,
OCP_THD_244_946);
if (retval) {
rtsx_trace(chip);
return retval;
}
retval = rtsx_write_register(chip, OCPCTL, 0xFF,
CARD_OC_INT_EN | CARD_DETECT_EN);
if (retval) {
rtsx_trace(chip);
return retval;
}
#else
/* OC power down */
retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN,
OC_POWER_DOWN);
if (retval) {
rtsx_trace(chip);
return retval;
}
#endif
if (!CHECK_PID(chip, 0x5288)) {
retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0xFF, 0x03);
if (retval) {
rtsx_trace(chip);
return retval;
}
}
/* Turn off LED */
retval = rtsx_write_register(chip, CARD_GPIO, 0xFF, 0x03);
if (retval) {
rtsx_trace(chip);
return retval;
}
/* Reset delink mode */
retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0);
if (retval) {
rtsx_trace(chip);
return retval;
}
/* Card driving select */
retval = rtsx_write_register(chip, CARD_DRIVE_SEL, 0xFF,
chip->card_drive_sel);
if (retval) {
rtsx_trace(chip);
return retval;
}
#ifdef LED_AUTO_BLINK
retval = rtsx_write_register(chip, CARD_AUTO_BLINK, 0xFF,
LED_BLINK_SPEED | BLINK_EN | LED_GPIO0);
if (retval) {
rtsx_trace(chip);
return retval;
}
#endif
if (chip->asic_code) {
/* Enable SSC Clock */
retval = rtsx_write_register(chip, SSC_CTL1, 0xFF,
SSC_8X_EN | SSC_SEL_4M);
if (retval) {
rtsx_trace(chip);
return retval;
}
retval = rtsx_write_register(chip, SSC_CTL2, 0xFF, 0x12);
if (retval) {
rtsx_trace(chip);
return retval;
}
}
/*
* Disable cd_pwr_save (u_force_rst_core_en=0, u_cd_rst_core_en=0)
* 0xFE5B
* bit[1] u_cd_rst_core_en rst_value = 0
* bit[2] u_force_rst_core_en rst_value = 0
* bit[5] u_mac_phy_rst_n_dbg rst_value = 1
* bit[4] u_non_sticky_rst_n_dbg rst_value = 0
*/
retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x16, 0x10);
if (retval) {
rtsx_trace(chip);
return retval;
}
/* Enable ASPM */
if (chip->aspm_l0s_l1_en) {
retval = rtsx_reset_aspm(chip);
if (retval != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
} else {
if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
retval = rtsx_write_phy_register(chip, 0x07, 0x0129);
if (retval != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
}
retval = rtsx_write_config_byte(chip, LCTLR,
chip->aspm_l0s_l1_en);
if (retval != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
}
retval = rtsx_write_config_byte(chip, 0x81, 1);
if (retval != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
if (CHK_SDIO_EXIST(chip)) {
retval = rtsx_write_cfg_dw(chip,
CHECK_PID(chip, 0x5288) ? 2 : 1,
0xC0, 0xFF00, 0x0100);
if (retval != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
}
if (CHECK_PID(chip, 0x5288) && !CHK_SDIO_EXIST(chip)) {
retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF, 0x0103);
if (retval != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
retval = rtsx_write_cfg_dw(chip, 2, 0x84, 0xFF, 0x03);
if (retval != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
}
retval = rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT,
LINK_RDY_INT);
if (retval) {
rtsx_trace(chip);
return retval;
}
retval = rtsx_write_register(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80);
if (retval) {
rtsx_trace(chip);
return retval;
}
retval = rtsx_enable_pcie_intr(chip);
if (retval != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
chip->need_reset = 0;
chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
if (chip->hw_bypass_sd)
goto nextcard;
dev_dbg(rtsx_dev(chip), "In %s, chip->int_reg = 0x%x\n", __func__,
chip->int_reg);
if (chip->int_reg & SD_EXIST) {
#ifdef HW_AUTO_SWITCH_SD_BUS
if (CHECK_PID(chip, 0x5208) && (chip->ic_version < IC_VER_C))
retval = rtsx_pre_handle_sdio_old(chip);
else
retval = rtsx_pre_handle_sdio_new(chip);
dev_dbg(rtsx_dev(chip), "chip->need_reset = 0x%x (rtsx_reset_chip)\n",
(unsigned int)(chip->need_reset));
#else /* HW_AUTO_SWITCH_SD_BUS */
retval = rtsx_pre_handle_sdio_old(chip);
#endif /* HW_AUTO_SWITCH_SD_BUS */
if (retval != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
} else {
chip->sd_io = 0;
retval = rtsx_write_register(chip, SDIO_CTRL,
SDIO_BUS_CTRL | SDIO_CD_CTRL, 0);
if (retval) {
rtsx_trace(chip);
return retval;
}
}
nextcard:
if (chip->int_reg & XD_EXIST)
chip->need_reset |= XD_CARD;
if (chip->int_reg & MS_EXIST)
chip->need_reset |= MS_CARD;
if (chip->int_reg & CARD_EXIST) {
retval = rtsx_write_register(chip, SSC_CTL1, SSC_RSTB,
SSC_RSTB);
if (retval) {
rtsx_trace(chip);
return retval;
}
}
dev_dbg(rtsx_dev(chip), "In %s, chip->need_reset = 0x%x\n", __func__,
(unsigned int)(chip->need_reset));
retval = rtsx_write_register(chip, RCCTL, 0x01, 0x00);
if (retval) {
rtsx_trace(chip);
return retval;
}
if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) {
/* Turn off main power when entering S3/S4 state */
retval = rtsx_write_register(chip, MAIN_PWR_OFF_CTL, 0x03,
0x03);
if (retval) {
rtsx_trace(chip);
return retval;
}
}
if (chip->remote_wakeup_en && !chip->auto_delink_en) {
retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x07);
if (retval) {
rtsx_trace(chip);
return retval;
}
if (chip->aux_pwr_exist) {
retval = rtsx_write_register(chip, PME_FORCE_CTL,
0xFF, 0x33);
if (retval) {
rtsx_trace(chip);
return retval;
}
}
} else {
retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x04);
if (retval) {
rtsx_trace(chip);
return retval;
}
retval = rtsx_write_register(chip, PME_FORCE_CTL, 0xFF, 0x30);
if (retval) {
rtsx_trace(chip);
return retval;
}
}
if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
retval = rtsx_write_register(chip, PETXCFG, 0x1C, 0x14);
if (retval) {
rtsx_trace(chip);
return retval;
}
}
if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
retval = rtsx_clr_phy_reg_bit(chip, 0x1C, 2);
if (retval != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
}
if (chip->ft2_fast_mode) {
retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF,
MS_PARTIAL_POWER_ON | SD_PARTIAL_POWER_ON);
if (retval) {
rtsx_trace(chip);
return retval;
}
udelay(chip->pmos_pwr_on_interval);
retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF,
MS_POWER_ON | SD_POWER_ON);
if (retval) {
rtsx_trace(chip);
return retval;
}
wait_timeout(200);
}
/* Reset card */
rtsx_reset_detected_cards(chip, 0);
chip->driver_first_load = 0;
return STATUS_SUCCESS;
}
static inline int check_sd_speed_prior(u32 sd_speed_prior)
{
bool fake_para = false;
int i;
for (i = 0; i < 4; i++) {
u8 tmp = (u8)(sd_speed_prior >> (i*8));
if ((tmp < 0x01) || (tmp > 0x04)) {
fake_para = true;
break;
}
}
return !fake_para;
}
static inline int check_sd_current_prior(u32 sd_current_prior)
{
bool fake_para = false;
int i;
for (i = 0; i < 4; i++) {
u8 tmp = (u8)(sd_current_prior >> (i*8));
if (tmp > 0x03) {
fake_para = true;
break;
}
}
return !fake_para;
}
static int rts_bpp_init(struct rtsx_chip *chip)
{
int retval;
u8 val = 0, max_func;
u32 lval = 0;
retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03);
if (retval) {
rtsx_trace(chip);
return retval;
}
retval = rtsx_read_register(chip, CLK_SEL, &val);
if (retval) {
rtsx_trace(chip);
return retval;
}
chip->asic_code = val == 0 ? 1 : 0;
chip->ic_version = 0;
chip->phy_debug_mode = 0;
retval = rtsx_read_register(chip, PDINFO, &val);
if (retval) {
rtsx_trace(chip);
return retval;
}
dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0;
retval = rtsx_read_register(chip, CARD_SHARE_MODE, &val);
if (retval) {
rtsx_trace(chip);
return retval;
}
dev_dbg(rtsx_dev(chip), "CARD_SHARE_MODE: 0x%x\n", val);
chip->baro_pkg = val & 0x04 ? QFN : LQFP;
retval = rtsx_read_register(chip, 0xFE5A, &val);
if (retval) {
rtsx_trace(chip);
return retval;
}
chip->hw_bypass_sd = val & 0x10 ? 1 : 0;
retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval);
if (retval != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
max_func = (u8)((lval >> 29) & 0x07);
dev_dbg(rtsx_dev(chip), "Max function number: %d\n", max_func);
if (max_func == 0x02)
SET_SDIO_EXIST(chip);
else
CLR_SDIO_EXIST(chip);
if (chip->use_hw_setting) {
retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val);
if (retval) {
rtsx_trace(chip);
return retval;
}
chip->auto_delink_en = val & 0x80 ? 1 : 0;
if (CHECK_BARO_PKG(chip, LQFP))
chip->lun_mode = SD_MS_1LUN;
else
chip->lun_mode = DEFAULT_SINGLE;
}
return STATUS_SUCCESS;
}
int rtsx_init_chip(struct rtsx_chip *chip)
{
struct sd_info *sd_card = &chip->sd_card;
struct xd_info *xd_card = &chip->xd_card;
struct ms_info *ms_card = &chip->ms_card;
int retval;
unsigned int i;
dev_dbg(rtsx_dev(chip), "Vendor ID: 0x%04x, Product ID: 0x%04x\n",
chip->vendor_id, chip->product_id);
chip->ic_version = 0;
#ifdef _MSG_TRACE
chip->msg_idx = 0;
#endif
memset(xd_card, 0, sizeof(struct xd_info));
memset(sd_card, 0, sizeof(struct sd_info));
memset(ms_card, 0, sizeof(struct ms_info));
chip->xd_reset_counter = 0;
chip->sd_reset_counter = 0;
chip->ms_reset_counter = 0;
chip->xd_show_cnt = MAX_SHOW_CNT;
chip->sd_show_cnt = MAX_SHOW_CNT;
chip->ms_show_cnt = MAX_SHOW_CNT;
chip->sd_io = 0;
chip->auto_delink_cnt = 0;
chip->auto_delink_allowed = 1;
rtsx_set_stat(chip, RTSX_STAT_INIT);
chip->aspm_enabled = 0;
chip->chip_insert_with_sdio = 0;
chip->sdio_aspm = 0;
chip->sdio_idle = 0;
chip->sdio_counter = 0;
chip->cur_card = 0;
chip->phy_debug_mode = 0;
chip->sdio_func_exist = 0;
memset(chip->sdio_raw_data, 0, 12);
for (i = 0; i < MAX_ALLOWED_LUN_CNT; i++) {
set_sense_type(chip, i, SENSE_TYPE_NO_SENSE);
chip->rw_fail_cnt[i] = 0;
}
if (!check_sd_speed_prior(chip->sd_speed_prior))
chip->sd_speed_prior = 0x01040203;
dev_dbg(rtsx_dev(chip), "sd_speed_prior = 0x%08x\n",
chip->sd_speed_prior);
if (!check_sd_current_prior(chip->sd_current_prior))
chip->sd_current_prior = 0x00010203;
dev_dbg(rtsx_dev(chip), "sd_current_prior = 0x%08x\n",
chip->sd_current_prior);
if ((chip->sd_ddr_tx_phase > 31) || (chip->sd_ddr_tx_phase < 0))
chip->sd_ddr_tx_phase = 0;
if ((chip->mmc_ddr_tx_phase > 31) || (chip->mmc_ddr_tx_phase < 0))
chip->mmc_ddr_tx_phase = 0;
retval = rtsx_write_register(chip, FPDCTL, SSC_POWER_DOWN, 0);
if (retval) {
rtsx_trace(chip);
return retval;
}
wait_timeout(200);
retval = rtsx_write_register(chip, CLK_DIV, 0x07, 0x07);
if (retval) {
rtsx_trace(chip);
return retval;
}
dev_dbg(rtsx_dev(chip), "chip->use_hw_setting = %d\n",
chip->use_hw_setting);
retval = rts_bpp_init(chip);
if (retval != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
if (chip->ss_en == 2)
chip->ss_en = 0;
dev_dbg(rtsx_dev(chip), "chip->asic_code = %d\n", chip->asic_code);
dev_dbg(rtsx_dev(chip), "chip->ic_version = 0x%x\n", chip->ic_version);
dev_dbg(rtsx_dev(chip), "chip->phy_debug_mode = %d\n",
chip->phy_debug_mode);
dev_dbg(rtsx_dev(chip), "chip->aux_pwr_exist = %d\n",
chip->aux_pwr_exist);
dev_dbg(rtsx_dev(chip), "chip->sdio_func_exist = %d\n",
chip->sdio_func_exist);
dev_dbg(rtsx_dev(chip), "chip->hw_bypass_sd = %d\n",
chip->hw_bypass_sd);
dev_dbg(rtsx_dev(chip), "chip->aspm_l0s_l1_en = %d\n",
chip->aspm_l0s_l1_en);
dev_dbg(rtsx_dev(chip), "chip->lun_mode = %d\n", chip->lun_mode);
dev_dbg(rtsx_dev(chip), "chip->auto_delink_en = %d\n",
chip->auto_delink_en);
dev_dbg(rtsx_dev(chip), "chip->ss_en = %d\n", chip->ss_en);
dev_dbg(rtsx_dev(chip), "chip->baro_pkg = %d\n", chip->baro_pkg);
if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
chip->card2lun[SD_CARD] = 0;
chip->card2lun[MS_CARD] = 1;
chip->card2lun[XD_CARD] = 0xFF;
chip->lun2card[0] = SD_CARD;
chip->lun2card[1] = MS_CARD;
chip->max_lun = 1;
SET_SDIO_IGNORED(chip);
} else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) {
chip->card2lun[SD_CARD] = 0;
chip->card2lun[MS_CARD] = 0;
chip->card2lun[XD_CARD] = 0xFF;
chip->lun2card[0] = SD_CARD | MS_CARD;
chip->max_lun = 0;
} else {
chip->card2lun[XD_CARD] = 0;
chip->card2lun[SD_CARD] = 0;
chip->card2lun[MS_CARD] = 0;
chip->lun2card[0] = XD_CARD | SD_CARD | MS_CARD;
chip->max_lun = 0;
}
retval = rtsx_reset_chip(chip);
if (retval != STATUS_SUCCESS) {
rtsx_trace(chip);
return STATUS_FAIL;
}
return STATUS_SUCCESS;
}
void rtsx_release_chip(struct rtsx_chip *chip)
{
xd_free_l2p_tbl(chip);
ms_free_l2p_tbl(chip);
chip->card_exist = 0;
chip->card_ready = 0;
}
#if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
static inline void rtsx_blink_led(struct rtsx_chip *chip)
{
if (chip->card_exist && chip->blink_led) {
if (chip->led_toggle_counter < LED_TOGGLE_INTERVAL) {
chip->led_toggle_counter++;
} else {
chip->led_toggle_counter = 0;
toggle_gpio(chip, LED_GPIO);
}
}
}
#endif
static void rtsx_monitor_aspm_config(struct rtsx_chip *chip)
{
bool reg_changed, maybe_support_aspm;
u32 tmp = 0;
u8 reg0 = 0, reg1 = 0;
maybe_support_aspm = false;
reg_changed = false;
rtsx_read_config_byte(chip, LCTLR, ®0);
if (chip->aspm_level[0] != reg0) {
reg_changed = true;
chip->aspm_level[0] = reg0;
}
if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
rtsx_read_cfg_dw(chip, 1, 0xC0, &tmp);
reg1 = (u8)tmp;
if (chip->aspm_level[1] != reg1) {
reg_changed = true;