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vga_hw.tcl~
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vga_hw.tcl~
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# TCL File Generated by Component Editor 13.0sp1
# Wed Sep 11 16:32:19 AMT 2019
# DO NOT MODIFY
#
# vga "vga" v1.0
# 2019.09.11.16:32:19
#
#
#
# request TCL package from ACDS 13.1
#
package require -exact qsys 13.1
#
# module vga
#
set_module_property DESCRIPTION ""
set_module_property NAME vga
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME vga
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL vga_monitor
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file vga_monitor.v VERILOG PATH VgaCommunication/vga_monitor.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point conduit_end
#
add_interface conduit_end conduit end
set_interface_property conduit_end associatedClock ""
set_interface_property conduit_end associatedReset ""
set_interface_property conduit_end ENABLED true
set_interface_property conduit_end EXPORT_OF ""
set_interface_property conduit_end PORT_NAME_MAP ""
set_interface_property conduit_end SVD_ADDRESS_GROUP ""
add_interface_port conduit_end HSync hsync Output 1
add_interface_port conduit_end VSync vsync Output 1
add_interface_port conduit_end R r Output 4
add_interface_port conduit_end G g Output 4
add_interface_port conduit_end B b Output 4
add_interface_port conduit_end button_game button_game Input 1
add_interface_port conduit_end score_p1 score_p1 Output 3
add_interface_port conduit_end score_p2 score_p2 Output 3
add_interface_port conduit_end up_left_bar up_left Input 1
add_interface_port conduit_end up_right_bar up_right Input 1
add_interface_port conduit_end down_left_bar down_left Input 1
add_interface_port conduit_end down_right_bar down_right Input 1
#
# connection point clock_sink
#
add_interface clock_sink clock end
set_interface_property clock_sink clockRate 0
set_interface_property clock_sink ENABLED true
set_interface_property clock_sink EXPORT_OF ""
set_interface_property clock_sink PORT_NAME_MAP ""
set_interface_property clock_sink SVD_ADDRESS_GROUP ""
add_interface_port clock_sink Clock clk Input 1