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sc_computer.map.rpt
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sc_computer.map.rpt
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Analysis & Synthesis report for sc_computer
Wed Jun 06 16:46:59 2018
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis RAM Summary
9. Analysis & Synthesis IP Cores Summary
10. User-Specified and Inferred Latches
11. Registers Removed During Synthesis
12. General Register Statistics
13. Inverted Register Statistics
14. Multiplexer Restructuring Statistics (Restructuring Performed)
15. Source assignments for sc_instmem:imem|lpm_rom_irom:irom|altsyncram:altsyncram_component|altsyncram_e8j1:auto_generated
16. Source assignments for sc_datamem_io:dmem|lpm_ram_dq_dram:dram|altsyncram:altsyncram_component|altsyncram_rmm1:auto_generated
17. Parameter Settings for User Entity Instance: sc_instmem:imem|lpm_rom_irom:irom|altsyncram:altsyncram_component
18. Parameter Settings for User Entity Instance: sc_datamem_io:dmem|lpm_ram_dq_dram:dram|altsyncram:altsyncram_component
19. Parameter Settings for Inferred Entity Instance: sc_display:show|lpm_divide:Div0
20. altsyncram Parameter Settings by Entity Instance
21. Port Connectivity Checks: "sc_display:show|sevenseg:display_2_low"
22. Port Connectivity Checks: "sc_display:show|sevenseg:display_2_high"
23. Port Connectivity Checks: "sc_display:show|sevenseg:display_1_low"
24. Port Connectivity Checks: "sc_display:show|sevenseg:display_1_high"
25. Port Connectivity Checks: "sc_display:show|sevenseg:display_0_low"
26. Port Connectivity Checks: "sc_display:show|sevenseg:display_0_high"
27. Port Connectivity Checks: "sc_datamem_io:dmem"
28. Port Connectivity Checks: "sc_instmem:imem"
29. Port Connectivity Checks: "sc_cpu:cpu|mux4x32:nextpc"
30. Port Connectivity Checks: "sc_cpu:cpu|mux2x32:alu_a"
31. Elapsed Time Per Partition
32. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+---------------------------------+--------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Jun 06 16:46:59 2018 ;
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; sc_computer ;
; Top-level Entity Name ; sc_computer ;
; Family ; Cyclone V ;
; Logic utilization (in ALMs) ; N/A ;
; Total registers ; 1148 ;
; Total pins ; 149 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 3,072 ;
; Total DSP Blocks ; 0 ;
; Total HSSI RX PCSs ; 0 ;
; Total HSSI PMA RX Deserializers ; 0 ;
; Total HSSI TX PCSs ; 0 ;
; Total HSSI TX Channels ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+---------------------------------+--------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Device ; 5CSEMA5F31C6 ; ;
; Top-level entity name ; sc_computer ; sc_computer ;
; Family name ; Cyclone V ; Cyclone IV GX ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; On ; On ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 3 ; 3 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
; Synthesis Seed ; 1 ; 1 ;
; Automatic Parallel Synthesis ; On ; On ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processors 2-4 ; < 0.1% ;
+----------------------------+-------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+----------------------------------------+------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+----------------------------------------+------------------------------------------------------------------+---------+
; source/io_output_reg.v ; yes ; User Verilog HDL File ; D:/shiyan/other/sc_computer_student/source/io_output_reg.v ; ;
; source/io_input_reg.v ; yes ; User Verilog HDL File ; D:/shiyan/other/sc_computer_student/source/io_input_reg.v ; ;
; source/sc_datamen_io.v ; yes ; User Verilog HDL File ; D:/shiyan/other/sc_computer_student/source/sc_datamen_io.v ; ;
; source/lpm_ram_dq_dram.v ; yes ; User Wizard-Generated File ; D:/shiyan/other/sc_computer_student/source/lpm_ram_dq_dram.v ; ;
; source/lpm_rom_irom.v ; yes ; User Wizard-Generated File ; D:/shiyan/other/sc_computer_student/source/lpm_rom_irom.v ; ;
; source/mux2x5.v ; yes ; User Verilog HDL File ; D:/shiyan/other/sc_computer_student/source/mux2x5.v ; ;
; source/mux2x32.v ; yes ; User Verilog HDL File ; D:/shiyan/other/sc_computer_student/source/mux2x32.v ; ;
; source/mux4x32.v ; yes ; User Verilog HDL File ; D:/shiyan/other/sc_computer_student/source/mux4x32.v ; ;
; source/dff32.v ; yes ; User Verilog HDL File ; D:/shiyan/other/sc_computer_student/source/dff32.v ; ;
; source/alu.v ; yes ; User Verilog HDL File ; D:/shiyan/other/sc_computer_student/source/alu.v ; ;
; source/regfile.v ; yes ; User Verilog HDL File ; D:/shiyan/other/sc_computer_student/source/regfile.v ; ;
; source/sc_cu.v ; yes ; User Verilog HDL File ; D:/shiyan/other/sc_computer_student/source/sc_cu.v ; ;
; source/sc_instmen.v ; yes ; User Verilog HDL File ; D:/shiyan/other/sc_computer_student/source/sc_instmen.v ; ;
; source/sc_cpu.v ; yes ; User Verilog HDL File ; D:/shiyan/other/sc_computer_student/source/sc_cpu.v ; ;
; source/sc_computer.v ; yes ; User Verilog HDL File ; D:/shiyan/other/sc_computer_student/source/sc_computer.v ; ;
; source/sevenseg.v ; yes ; User Verilog HDL File ; D:/shiyan/other/sc_computer_student/source/sevenseg.v ; ;
; source/sc_display.v ; yes ; User Verilog HDL File ; D:/shiyan/other/sc_computer_student/source/sc_display.v ; ;
; altsyncram.tdf ; yes ; Megafunction ; d:/quartus/quartus/libraries/megafunctions/altsyncram.tdf ; ;
; stratix_ram_block.inc ; yes ; Megafunction ; d:/quartus/quartus/libraries/megafunctions/stratix_ram_block.inc ; ;
; lpm_mux.inc ; yes ; Megafunction ; d:/quartus/quartus/libraries/megafunctions/lpm_mux.inc ; ;
; lpm_decode.inc ; yes ; Megafunction ; d:/quartus/quartus/libraries/megafunctions/lpm_decode.inc ; ;
; aglobal131.inc ; yes ; Megafunction ; d:/quartus/quartus/libraries/megafunctions/aglobal131.inc ; ;
; a_rdenreg.inc ; yes ; Megafunction ; d:/quartus/quartus/libraries/megafunctions/a_rdenreg.inc ; ;
; altrom.inc ; yes ; Megafunction ; d:/quartus/quartus/libraries/megafunctions/altrom.inc ; ;
; altram.inc ; yes ; Megafunction ; d:/quartus/quartus/libraries/megafunctions/altram.inc ; ;
; altdpram.inc ; yes ; Megafunction ; d:/quartus/quartus/libraries/megafunctions/altdpram.inc ; ;
; db/altsyncram_e8j1.tdf ; yes ; Auto-Generated Megafunction ; D:/shiyan/other/sc_computer_student/db/altsyncram_e8j1.tdf ; ;
; source/sc_add_instmem.mif ; yes ; Auto-Found Memory Initialization File ; D:/shiyan/other/sc_computer_student/source/sc_add_instmem.mif ; ;
; db/altsyncram_rmm1.tdf ; yes ; Auto-Generated Megafunction ; D:/shiyan/other/sc_computer_student/db/altsyncram_rmm1.tdf ; ;
; source/sc_add_datamem.mif ; yes ; Auto-Found Memory Initialization File ; D:/shiyan/other/sc_computer_student/source/sc_add_datamem.mif ; ;
; lpm_divide.tdf ; yes ; Megafunction ; d:/quartus/quartus/libraries/megafunctions/lpm_divide.tdf ; ;
; abs_divider.inc ; yes ; Megafunction ; d:/quartus/quartus/libraries/megafunctions/abs_divider.inc ; ;
; sign_div_unsign.inc ; yes ; Megafunction ; d:/quartus/quartus/libraries/megafunctions/sign_div_unsign.inc ; ;
; db/lpm_divide_ibm.tdf ; yes ; Auto-Generated Megafunction ; D:/shiyan/other/sc_computer_student/db/lpm_divide_ibm.tdf ; ;
; db/sign_div_unsign_olh.tdf ; yes ; Auto-Generated Megafunction ; D:/shiyan/other/sc_computer_student/db/sign_div_unsign_olh.tdf ; ;
; db/alt_u_div_mve.tdf ; yes ; Auto-Generated Megafunction ; D:/shiyan/other/sc_computer_student/db/alt_u_div_mve.tdf ; ;
+----------------------------------+-----------------+----------------------------------------+------------------------------------------------------------------+---------+
+------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+--------------+
; Resource ; Usage ;
+---------------------------------------------+--------------+
; Estimate of Logic utilization (ALMs needed) ; 1472 ;
; ; ;
; Combinational ALUT usage for logic ; 1890 ;
; -- 7 input functions ; 54 ;
; -- 6 input functions ; 883 ;
; -- 5 input functions ; 221 ;
; -- 4 input functions ; 153 ;
; -- <=3 input functions ; 579 ;
; ; ;
; Dedicated logic registers ; 1148 ;
; ; ;
; I/O pins ; 149 ;
; Total MLAB memory bits ; 0 ;
; Total block memory bits ; 3072 ;
; Total DSP Blocks ; 0 ;
; Maximum fan-out node ; resetn~input ;
; Maximum fan-out ; 1120 ;
; Total fan-out ; 14153 ;
; Average fan-out ; 4.16 ;
+---------------------------------------------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+------------------------------------------------------------------------------------------------------------------------------+--------------+
; |sc_computer ; 1890 (0) ; 1148 (0) ; 3072 ; 0 ; 149 ; 0 ; |sc_computer ; work ;
; |generate_clock:clock_50M| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|generate_clock:clock_50M ; work ;
; |sc_cpu:cpu| ; 1502 (65) ; 1024 (0) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|sc_cpu:cpu ; work ;
; |alu:al_unit| ; 480 (480) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|sc_cpu:cpu|alu:al_unit ; work ;
; |dff32:ip| ; 29 (29) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|sc_cpu:cpu|dff32:ip ; work ;
; |mux2x32:alu_a| ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|sc_cpu:cpu|mux2x32:alu_a ; work ;
; |mux2x32:alu_b| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|sc_cpu:cpu|mux2x32:alu_b ; work ;
; |mux2x32:link| ; 35 (35) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|sc_cpu:cpu|mux2x32:link ; work ;
; |mux4x32:nextpc| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|sc_cpu:cpu|mux4x32:nextpc ; work ;
; |regfile:rf| ; 776 (776) ; 992 (992) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|sc_cpu:cpu|regfile:rf ; work ;
; |sc_cu:cu| ; 35 (35) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|sc_cpu:cpu|sc_cu:cu ; work ;
; |sc_datamem_io:dmem| ; 16 (2) ; 105 (0) ; 1024 ; 0 ; 0 ; 0 ; |sc_computer|sc_datamem_io:dmem ; work ;
; |io_input_reg:io_input_regx2| ; 10 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|sc_datamem_io:dmem|io_input_reg:io_input_regx2 ; work ;
; |io_input_mux:io_imput_mux2x32| ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|sc_datamem_io:dmem|io_input_reg:io_input_regx2|io_input_mux:io_imput_mux2x32 ; work ;
; |io_output_reg:io_output_regx2| ; 4 (4) ; 96 (96) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|sc_datamem_io:dmem|io_output_reg:io_output_regx2 ; work ;
; |lpm_ram_dq_dram:dram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |sc_computer|sc_datamem_io:dmem|lpm_ram_dq_dram:dram ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |sc_computer|sc_datamem_io:dmem|lpm_ram_dq_dram:dram|altsyncram:altsyncram_component ; work ;
; |altsyncram_rmm1:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |sc_computer|sc_datamem_io:dmem|lpm_ram_dq_dram:dram|altsyncram:altsyncram_component|altsyncram_rmm1:auto_generated ; work ;
; |sc_display:show| ; 370 (29) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|sc_display:show ; work ;
; |lpm_divide:Div0| ; 313 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|sc_display:show|lpm_divide:Div0 ; work ;
; |lpm_divide_ibm:auto_generated| ; 313 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|sc_display:show|lpm_divide:Div0|lpm_divide_ibm:auto_generated ; work ;
; |sign_div_unsign_olh:divider| ; 313 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|sc_display:show|lpm_divide:Div0|lpm_divide_ibm:auto_generated|sign_div_unsign_olh:divider ; work ;
; |alt_u_div_mve:divider| ; 313 (313) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|sc_display:show|lpm_divide:Div0|lpm_divide_ibm:auto_generated|sign_div_unsign_olh:divider|alt_u_div_mve:divider ; work ;
; |sevenseg:display_0_low| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|sc_display:show|sevenseg:display_0_low ; work ;
; |sevenseg:display_1_low| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|sc_display:show|sevenseg:display_1_low ; work ;
; |sevenseg:display_2_high| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|sc_display:show|sevenseg:display_2_high ; work ;
; |sevenseg:display_2_low| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |sc_computer|sc_display:show|sevenseg:display_2_low ; work ;
; |sc_instmem:imem| ; 1 (1) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; |sc_computer|sc_instmem:imem ; work ;
; |lpm_rom_irom:irom| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; |sc_computer|sc_instmem:imem|lpm_rom_irom:irom ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; |sc_computer|sc_instmem:imem|lpm_rom_irom:irom|altsyncram:altsyncram_component ; work ;
; |altsyncram_e8j1:auto_generated| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; |sc_computer|sc_instmem:imem|lpm_rom_irom:irom|altsyncram:altsyncram_component|altsyncram_e8j1:auto_generated ; work ;
+----------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+-------------------------------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+------+------------------------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+-------------------------------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+------+------------------------------+
; sc_datamem_io:dmem|lpm_ram_dq_dram:dram|altsyncram:altsyncram_component|altsyncram_rmm1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 32 ; 32 ; -- ; -- ; 1024 ; ../source/sc_add_datamem.mif ;
; sc_instmem:imem|lpm_rom_irom:irom|altsyncram:altsyncram_component|altsyncram_e8j1:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 64 ; 32 ; -- ; -- ; 2048 ; ../source/sc_add_instmem.mif ;
+-------------------------------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+------+------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------+--------------+---------+--------------+--------------+------------------------------------------------------+--------------------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
+--------+--------------+---------+--------------+--------------+------------------------------------------------------+--------------------------------------------------------------+
; Altera ; LPM_RAM_DQ ; N/A ; N/A ; N/A ; |sc_computer|sc_datamem_io:dmem|lpm_ram_dq_dram:dram ; D:/shiyan/other/sc_computer_student/source/lpm_ram_dq_dram.v ;
; Altera ; LPM_ROM ; N/A ; N/A ; N/A ; |sc_computer|sc_instmem:imem|lpm_rom_irom:irom ; D:/shiyan/other/sc_computer_student/source/lpm_rom_irom.v ;
+--------+--------------+---------+--------------+--------------+------------------------------------------------------+--------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+-----------------------------------------------------------------------------------+--------------------------------------------------------------------------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+-----------------------------------------------------------------------------------+--------------------------------------------------------------------------------------+------------------------+
; sc_datamem_io:dmem|io_input_reg:io_input_regx2|io_input_mux:io_imput_mux2x32|y[0] ; sc_datamem_io:dmem|io_input_reg:io_input_regx2|io_input_mux:io_imput_mux2x32|WideOr0 ; yes ;
; sc_datamem_io:dmem|io_input_reg:io_input_regx2|io_input_mux:io_imput_mux2x32|y[1] ; sc_datamem_io:dmem|io_input_reg:io_input_regx2|io_input_mux:io_imput_mux2x32|WideOr0 ; yes ;
; sc_datamem_io:dmem|io_input_reg:io_input_regx2|io_input_mux:io_imput_mux2x32|y[2] ; sc_datamem_io:dmem|io_input_reg:io_input_regx2|io_input_mux:io_imput_mux2x32|WideOr0 ; yes ;
; sc_datamem_io:dmem|io_input_reg:io_input_regx2|io_input_mux:io_imput_mux2x32|y[3] ; sc_datamem_io:dmem|io_input_reg:io_input_regx2|io_input_mux:io_imput_mux2x32|WideOr0 ; yes ;
; Number of user-specified and inferred latches = 4 ; ; ;
+-----------------------------------------------------------------------------------+--------------------------------------------------------------------------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+--------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------------------------------+----------------------------------------+
; sc_display:show|num2[1..3] ; Stuck at GND due to stuck port data_in ;
; sc_display:show|num0[1..3] ; Stuck at GND due to stuck port data_in ;
; sc_datamem_io:dmem|io_input_reg:io_input_regx2|in_reg2[1..31] ; Stuck at GND due to stuck port data_in ;
; sc_datamem_io:dmem|io_input_reg:io_input_regx2|in_reg1[4..31] ; Stuck at GND due to stuck port data_in ;
; sc_datamem_io:dmem|io_input_reg:io_input_regx2|in_reg0[4..31] ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 93 ; ;
+---------------------------------------------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 1148 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 1120 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 1090 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------+
; Inverted Register Statistics ;
+-----------------------------------------+---------+
; Inverted Register ; Fan out ;
+-----------------------------------------+---------+
; sc_cpu:cpu|dff32:ip|q[2] ; 2 ;
; sc_cpu:cpu|dff32:ip|q[3] ; 2 ;
; sc_cpu:cpu|dff32:ip|q[4] ; 2 ;
; sc_cpu:cpu|dff32:ip|q[5] ; 2 ;
; sc_cpu:cpu|dff32:ip|q[6] ; 2 ;
; sc_cpu:cpu|dff32:ip|q[7] ; 2 ;
; sc_cpu:cpu|dff32:ip|q[15] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[17] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[16] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[18] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[14] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[13] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[11] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[12] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[10] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[9] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[8] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[29] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[28] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[26] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[25] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[23] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[24] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[19] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[20] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[21] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[22] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[30] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[27] ; 1 ;
; sc_cpu:cpu|dff32:ip|q[31] ; 1 ;
; Total number of inverted registers = 30 ; ;
+-----------------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------------+
; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |sc_computer|sc_cpu:cpu|dff32:ip|q[0] ;
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |sc_computer|sc_cpu:cpu|dff32:ip|q[28] ;
; 4:1 ; 26 bits ; 52 LEs ; 52 LEs ; 0 LEs ; Yes ; |sc_computer|sc_cpu:cpu|dff32:ip|q[24] ;
; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |sc_computer|sc_cpu:cpu|alu:al_unit|ShiftLeft0 ;
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |sc_computer|sc_cpu:cpu|alu:al_unit|ShiftRight0 ;
; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |sc_computer|sc_cpu:cpu|alu:al_unit|ShiftRight0 ;
; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |sc_computer|sc_cpu:cpu|alu:al_unit|ShiftRight1 ;
; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |sc_computer|sc_cpu:cpu|alu:al_unit|ShiftLeft0 ;
; 4:1 ; 28 bits ; 56 LEs ; 56 LEs ; 0 LEs ; No ; |sc_computer|sc_cpu:cpu|mux2x32:link|y[16] ;
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |sc_computer|sc_cpu:cpu|mux2x32:link|y[1] ;
; 32:1 ; 32 bits ; 672 LEs ; 672 LEs ; 0 LEs ; No ; |sc_computer|sc_cpu:cpu|regfile:rf|qb[14] ;
; 32:1 ; 32 bits ; 672 LEs ; 672 LEs ; 0 LEs ; No ; |sc_computer|sc_cpu:cpu|regfile:rf|qa[1] ;
; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |sc_computer|sc_datamem_io:dmem|io_input_reg:io_input_regx2|io_input_mux:io_imput_mux2x32|Selector2 ;
; 19:1 ; 7 bits ; 84 LEs ; 63 LEs ; 21 LEs ; No ; |sc_computer|sc_cpu:cpu|alu:al_unit|Mux17 ;
; 20:1 ; 4 bits ; 52 LEs ; 40 LEs ; 12 LEs ; No ; |sc_computer|sc_cpu:cpu|alu:al_unit|Mux27 ;
; 21:1 ; 3 bits ; 42 LEs ; 30 LEs ; 12 LEs ; No ; |sc_computer|sc_cpu:cpu|alu:al_unit|Mux30 ;
; 17:1 ; 11 bits ; 121 LEs ; 99 LEs ; 22 LEs ; No ; |sc_computer|sc_cpu:cpu|alu:al_unit|Mux14 ;
; 19:1 ; 3 bits ; 36 LEs ; 30 LEs ; 6 LEs ; No ; |sc_computer|sc_cpu:cpu|alu:al_unit|Mux1 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sc_instmem:imem|lpm_rom_irom:irom|altsyncram:altsyncram_component|altsyncram_e8j1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sc_datamem_io:dmem|lpm_ram_dq_dram:dram|altsyncram:altsyncram_component|altsyncram_rmm1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sc_instmem:imem|lpm_rom_irom:irom|altsyncram:altsyncram_component ;
+------------------------------------+------------------------------+--------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+------------------------------+--------------------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 32 ; Signed Integer ;
; WIDTHAD_A ; 6 ; Signed Integer ;
; NUMWORDS_A ; 64 ; Signed Integer ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; M4K ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; ../source/sc_add_instmem.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 256 ; Signed Integer ;
; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
; WIDTH_ECCSTATUS ; 3 ; Untyped ;
; DEVICE_FAMILY ; Cyclone V ; Untyped ;
; CBXI_PARAMETER ; altsyncram_e8j1 ; Untyped ;
+------------------------------------+------------------------------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sc_datamem_io:dmem|lpm_ram_dq_dram:dram|altsyncram:altsyncram_component ;
+------------------------------------+------------------------------+--------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+------------------------------+--------------------------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; SINGLE_PORT ; Untyped ;
; WIDTH_A ; 32 ; Signed Integer ;
; WIDTHAD_A ; 5 ; Signed Integer ;
; NUMWORDS_A ; 32 ; Signed Integer ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; M4K ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; ../source/sc_add_datamem.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
; WIDTH_ECCSTATUS ; 3 ; Untyped ;
; DEVICE_FAMILY ; Cyclone V ; Untyped ;
; CBXI_PARAMETER ; altsyncram_rmm1 ; Untyped ;
+------------------------------------+------------------------------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sc_display:show|lpm_divide:Div0 ;
+------------------------+----------------+----------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+----------------+----------------------------------------+
; LPM_WIDTHN ; 32 ; Untyped ;
; LPM_WIDTHD ; 4 ; Untyped ;
; LPM_NREPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DREPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; CBXI_PARAMETER ; lpm_divide_ibm ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+----------------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance ;
+-------------------------------------------+-------------------------------------------------------------------------+
; Name ; Value ;
+-------------------------------------------+-------------------------------------------------------------------------+
; Number of entity instances ; 2 ;
; Entity Instance ; sc_instmem:imem|lpm_rom_irom:irom|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; ROM ;
; -- WIDTH_A ; 32 ;
; -- NUMWORDS_A ; 64 ;
; -- OUTDATA_REG_A ; UNREGISTERED ;
; -- WIDTH_B ; 1 ;
; -- NUMWORDS_B ; 1 ;
; -- ADDRESS_REG_B ; CLOCK1 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; M4K ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
; Entity Instance ; sc_datamem_io:dmem|lpm_ram_dq_dram:dram|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; SINGLE_PORT ;
; -- WIDTH_A ; 32 ;
; -- NUMWORDS_A ; 32 ;
; -- OUTDATA_REG_A ; UNREGISTERED ;
; -- WIDTH_B ; 1 ;
; -- NUMWORDS_B ; 1 ;
; -- ADDRESS_REG_B ; CLOCK1 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; M4K ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
+-------------------------------------------+-------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sc_display:show|sevenseg:display_2_low" ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; data ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (4 bits) it drives. The 28 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sc_display:show|sevenseg:display_2_high" ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; data ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (4 bits) it drives. The 28 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sc_display:show|sevenseg:display_1_low" ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; data ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (4 bits) it drives. The 28 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sc_display:show|sevenseg:display_1_high" ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; data ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (4 bits) it drives. The 28 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sc_display:show|sevenseg:display_0_low" ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; data ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (4 bits) it drives. The 28 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sc_display:show|sevenseg:display_0_high" ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; data ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (4 bits) it drives. The 28 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sc_datamem_io:dmem" ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
; dmem_clk ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; mem_dataout ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; io_read_data ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "sc_instmem:imem" ;
+----------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+----------+--------+----------+-------------------------------------------------------------------------------------+
; imem_clk ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+----------+--------+----------+-------------------------------------------------------------------------------------+
+-------------------------------------------------------+
; Port Connectivity Checks: "sc_cpu:cpu|mux4x32:nextpc" ;
+----------+-------+----------+-------------------------+
; Port ; Type ; Severity ; Details ;
+----------+-------+----------+-------------------------+
; a3[1..0] ; Input ; Info ; Stuck at GND ;
+----------+-------+----------+-------------------------+
+------------------------------------------------------+
; Port Connectivity Checks: "sc_cpu:cpu|mux2x32:alu_a" ;
+-----------+-------+----------+-----------------------+
; Port ; Type ; Severity ; Details ;
+-----------+-------+----------+-----------------------+
; a1[31..5] ; Input ; Info ; Stuck at GND ;
+-----------+-------+----------+-----------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:11 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Jun 06 16:46:44 2018
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sc_computer -c sc_computer
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file source/io_output_reg.v
Info (12023): Found entity 1: io_output_reg
Info (12021): Found 2 design units, including 2 entities, in source file source/io_input_reg.v
Info (12023): Found entity 1: io_input_reg
Info (12023): Found entity 2: io_input_mux
Info (12021): Found 1 design units, including 1 entities, in source file source/sc_datamen_io.v
Info (12023): Found entity 1: sc_datamem_io
Info (12021): Found 1 design units, including 1 entities, in source file source/lpm_ram_dq_dram.v
Info (12023): Found entity 1: lpm_ram_dq_dram
Info (12021): Found 1 design units, including 1 entities, in source file source/lpm_rom_irom.v
Info (12023): Found entity 1: lpm_rom_irom
Info (12021): Found 1 design units, including 1 entities, in source file source/mux2x5.v
Info (12023): Found entity 1: mux2x5
Info (12021): Found 1 design units, including 1 entities, in source file source/mux2x32.v
Info (12023): Found entity 1: mux2x32
Info (12021): Found 1 design units, including 1 entities, in source file source/mux4x32.v
Info (12023): Found entity 1: mux4x32
Info (12021): Found 1 design units, including 1 entities, in source file source/dff32.v
Info (12023): Found entity 1: dff32
Info (12021): Found 1 design units, including 1 entities, in source file source/alu.v
Info (12023): Found entity 1: alu
Info (12021): Found 1 design units, including 1 entities, in source file source/regfile.v
Info (12023): Found entity 1: regfile
Info (12021): Found 1 design units, including 1 entities, in source file source/sc_cu.v
Info (12023): Found entity 1: sc_cu
Info (12021): Found 1 design units, including 1 entities, in source file source/sc_datamem.v
Info (12023): Found entity 1: sc_datamem
Info (12021): Found 1 design units, including 1 entities, in source file source/sc_instmen.v
Info (12023): Found entity 1: sc_instmem
Info (12021): Found 1 design units, including 1 entities, in source file source/sc_cpu.v
Info (12023): Found entity 1: sc_cpu
Warning (10238): Verilog Module Declaration warning at sc_computer.v(9): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "sc_computer"
Info (12021): Found 2 design units, including 2 entities, in source file source/sc_computer.v
Info (12023): Found entity 1: sc_computer
Info (12023): Found entity 2: generate_clock
Info (12021): Found 1 design units, including 1 entities, in source file source/sevenseg.v
Info (12023): Found entity 1: sevenseg
Info (12021): Found 1 design units, including 1 entities, in source file source/sc_display.v
Info (12023): Found entity 1: sc_display
Warning (10236): Verilog HDL Implicit Net warning at sc_datamen_io.v(20): created implicit net for "write_datamem_enable"
Warning (10236): Verilog HDL Implicit Net warning at sc_datamen_io.v(21): created implicit net for "write_io_output_reg_enable"
Warning (10227): Verilog HDL Port Declaration warning at sevenseg.v(5): data type declaration for "ledsegments" declares packed dimensions but the port declaration declaration does not
Info (10499): HDL info at sevenseg.v(4): see declaration for object "ledsegments"
Info (12127): Elaborating entity "sc_computer" for the top level hierarchy
Info (12128): Elaborating entity "generate_clock" for hierarchy "generate_clock:clock_50M"
Info (12128): Elaborating entity "sc_cpu" for hierarchy "sc_cpu:cpu"
Info (12128): Elaborating entity "dff32" for hierarchy "sc_cpu:cpu|dff32:ip"
Info (12128): Elaborating entity "sc_cu" for hierarchy "sc_cpu:cpu|sc_cu:cu"
Info (12128): Elaborating entity "mux2x32" for hierarchy "sc_cpu:cpu|mux2x32:alu_b"
Info (12128): Elaborating entity "mux2x5" for hierarchy "sc_cpu:cpu|mux2x5:reg_wn"
Info (12128): Elaborating entity "mux4x32" for hierarchy "sc_cpu:cpu|mux4x32:nextpc"
Info (12128): Elaborating entity "regfile" for hierarchy "sc_cpu:cpu|regfile:rf"
Warning (10240): Verilog HDL Always Construct warning at regfile.v(14): inferring latch(es) for variable "i", which holds its previous value in one or more paths through the always construct
Info (12128): Elaborating entity "alu" for hierarchy "sc_cpu:cpu|alu:al_unit"
Info (12128): Elaborating entity "sc_instmem" for hierarchy "sc_instmem:imem"
Info (12128): Elaborating entity "lpm_rom_irom" for hierarchy "sc_instmem:imem|lpm_rom_irom:irom"
Info (12128): Elaborating entity "altsyncram" for hierarchy "sc_instmem:imem|lpm_rom_irom:irom|altsyncram:altsyncram_component"
Info (12130): Elaborated megafunction instantiation "sc_instmem:imem|lpm_rom_irom:irom|altsyncram:altsyncram_component"
Info (12133): Instantiated megafunction "sc_instmem:imem|lpm_rom_irom:irom|altsyncram:altsyncram_component" with the following parameter:
Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
Info (12134): Parameter "init_file" = "../source/sc_add_instmem.mif"
Info (12134): Parameter "intended_device_family" = "Cyclone II"
Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
Info (12134): Parameter "lpm_type" = "altsyncram"
Info (12134): Parameter "maximum_depth" = "256"
Info (12134): Parameter "numwords_a" = "64"
Info (12134): Parameter "operation_mode" = "ROM"
Info (12134): Parameter "outdata_aclr_a" = "NONE"
Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED"
Info (12134): Parameter "ram_block_type" = "M4K"
Info (12134): Parameter "widthad_a" = "6"
Info (12134): Parameter "width_a" = "32"
Info (12134): Parameter "width_byteena_a" = "1"
Warning (287001): Assertion warning: Device family Cyclone V does not have M4K blocks -- using available memory blocks
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_e8j1.tdf
Info (12023): Found entity 1: altsyncram_e8j1
Info (12128): Elaborating entity "altsyncram_e8j1" for hierarchy "sc_instmem:imem|lpm_rom_irom:irom|altsyncram:altsyncram_component|altsyncram_e8j1:auto_generated"
Info (12128): Elaborating entity "sc_datamem_io" for hierarchy "sc_datamem_io:dmem"
Info (12128): Elaborating entity "lpm_ram_dq_dram" for hierarchy "sc_datamem_io:dmem|lpm_ram_dq_dram:dram"
Info (12128): Elaborating entity "altsyncram" for hierarchy "sc_datamem_io:dmem|lpm_ram_dq_dram:dram|altsyncram:altsyncram_component"
Info (12130): Elaborated megafunction instantiation "sc_datamem_io:dmem|lpm_ram_dq_dram:dram|altsyncram:altsyncram_component"
Info (12133): Instantiated megafunction "sc_datamem_io:dmem|lpm_ram_dq_dram:dram|altsyncram:altsyncram_component" with the following parameter:
Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
Info (12134): Parameter "init_file" = "../source/sc_add_datamem.mif"
Info (12134): Parameter "intended_device_family" = "Cyclone II"
Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
Info (12134): Parameter "lpm_type" = "altsyncram"
Info (12134): Parameter "numwords_a" = "32"
Info (12134): Parameter "operation_mode" = "SINGLE_PORT"
Info (12134): Parameter "outdata_aclr_a" = "NONE"
Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED"
Info (12134): Parameter "power_up_uninitialized" = "FALSE"
Info (12134): Parameter "ram_block_type" = "M4K"
Info (12134): Parameter "widthad_a" = "5"
Info (12134): Parameter "width_a" = "32"
Info (12134): Parameter "width_byteena_a" = "1"
Warning (287001): Assertion warning: Device family Cyclone V does not have M4K blocks -- using available memory blocks
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_rmm1.tdf
Info (12023): Found entity 1: altsyncram_rmm1
Info (12128): Elaborating entity "altsyncram_rmm1" for hierarchy "sc_datamem_io:dmem|lpm_ram_dq_dram:dram|altsyncram:altsyncram_component|altsyncram_rmm1:auto_generated"
Info (12128): Elaborating entity "io_output_reg" for hierarchy "sc_datamem_io:dmem|io_output_reg:io_output_regx2"
Info (12128): Elaborating entity "io_input_reg" for hierarchy "sc_datamem_io:dmem|io_input_reg:io_input_regx2"
Info (12128): Elaborating entity "io_input_mux" for hierarchy "sc_datamem_io:dmem|io_input_reg:io_input_regx2|io_input_mux:io_imput_mux2x32"
Warning (10270): Verilog HDL Case Statement warning at io_input_reg.v(28): incomplete case statement has no default case item
Warning (10240): Verilog HDL Always Construct warning at io_input_reg.v(28): inferring latch(es) for variable "y", which holds its previous value in one or more paths through the always construct
Info (10041): Inferred latch for "y[0]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[1]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[2]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[3]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[4]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[5]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[6]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[7]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[8]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[9]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[10]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[11]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[12]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[13]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[14]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[15]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[16]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[17]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[18]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[19]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[20]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[21]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[22]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[23]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[24]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[25]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[26]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[27]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[28]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[29]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[30]" at io_input_reg.v(28)
Info (10041): Inferred latch for "y[31]" at io_input_reg.v(28)
Info (12128): Elaborating entity "sc_display" for hierarchy "sc_display:show"
Info (12128): Elaborating entity "sevenseg" for hierarchy "sc_display:show|sevenseg:display_0_high"
Info (278001): Inferred 1 megafunctions from design logic
Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "sc_display:show|Div0"
Info (12130): Elaborated megafunction instantiation "sc_display:show|lpm_divide:Div0"
Info (12133): Instantiated megafunction "sc_display:show|lpm_divide:Div0" with the following parameter:
Info (12134): Parameter "LPM_WIDTHN" = "32"
Info (12134): Parameter "LPM_WIDTHD" = "4"
Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_ibm.tdf
Info (12023): Found entity 1: lpm_divide_ibm
Info (12021): Found 1 design units, including 1 entities, in source file db/sign_div_unsign_olh.tdf
Info (12023): Found entity 1: sign_div_unsign_olh
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_mve.tdf
Info (12023): Found entity 1: alt_u_div_mve
Warning (12241): 6 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Warning (13012): Latch sc_datamem_io:dmem|io_input_reg:io_input_regx2|io_input_mux:io_imput_mux2x32|y[0] has unsafe behavior
Warning (13013): Ports D and ENA on the latch are fed by the same signal sc_instmem:imem|lpm_rom_irom:irom|altsyncram:altsyncram_component|altsyncram_e8j1:auto_generated|q_a[4]
Warning (13012): Latch sc_datamem_io:dmem|io_input_reg:io_input_regx2|io_input_mux:io_imput_mux2x32|y[1] has unsafe behavior
Warning (13013): Ports D and ENA on the latch are fed by the same signal sc_instmem:imem|lpm_rom_irom:irom|altsyncram:altsyncram_component|altsyncram_e8j1:auto_generated|q_a[3]
Warning (13012): Latch sc_datamem_io:dmem|io_input_reg:io_input_regx2|io_input_mux:io_imput_mux2x32|y[2] has unsafe behavior
Warning (13013): Ports D and ENA on the latch are fed by the same signal sc_instmem:imem|lpm_rom_irom:irom|altsyncram:altsyncram_component|altsyncram_e8j1:auto_generated|q_a[3]
Warning (13012): Latch sc_datamem_io:dmem|io_input_reg:io_input_regx2|io_input_mux:io_imput_mux2x32|y[3] has unsafe behavior
Warning (13013): Ports D and ENA on the latch are fed by the same signal sc_instmem:imem|lpm_rom_irom:irom|altsyncram:altsyncram_component|altsyncram_e8j1:auto_generated|q_a[3]
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "hex0[1]" is stuck at GND
Warning (13410): Pin "hex0[2]" is stuck at GND
Warning (13410): Pin "hex0[6]" is stuck at VCC
Warning (13410): Pin "hex4[1]" is stuck at GND
Warning (13410): Pin "hex4[2]" is stuck at GND
Warning (13410): Pin "hex4[6]" is stuck at VCC
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 3205 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 11 input pins
Info (21059): Implemented 138 output pins
Info (21061): Implemented 2992 logic cells
Info (21064): Implemented 64 RAM segments
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 25 warnings
Info: Peak virtual memory: 4750 megabytes
Info: Processing ended: Wed Jun 06 16:46:59 2018
Info: Elapsed time: 00:00:15
Info: Total CPU time (on all processors): 00:00:12