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pipelined_computer.qsf
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pipelined_computer.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 16:14:32 June 05, 2018
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# pipelined_computer_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEMA5F31C6
set_global_assignment -name TOP_LEVEL_ENTITY pipelined_computer
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:14:32 JUNE 05, 2018"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE pipeir.v
set_global_assignment -name VERILOG_FILE sevenseg.v
set_global_assignment -name VERILOG_FILE regfile.v
set_global_assignment -name VERILOG_FILE pipepc.v
set_global_assignment -name VERILOG_FILE pipeexe.v
set_global_assignment -name VERILOG_FILE pipedereg.v
set_global_assignment -name VERILOG_FILE mux4x32.v
set_global_assignment -name VERILOG_FILE mux2x32.v
set_global_assignment -name VERILOG_FILE mux2x5.v
set_global_assignment -name VERILOG_FILE lpm_rom_irom.v
set_global_assignment -name VERILOG_FILE lpm_ram_dq_dram.v
set_global_assignment -name VERILOG_FILE io_output_reg.v
set_global_assignment -name VERILOG_FILE io_input_reg.v
set_global_assignment -name VERILOG_FILE io_input_mux.v
set_global_assignment -name VERILOG_FILE dffe32.v
set_global_assignment -name VERILOG_FILE dff32.v
set_global_assignment -name VERILOG_FILE alu.v
set_global_assignment -name VERILOG_FILE pipelined_computer.v
set_global_assignment -name VERILOG_FILE pipeemreg.v
set_global_assignment -name VERILOG_FILE pipemwreg.v
set_global_assignment -name VERILOG_FILE pipemem.v
set_global_assignment -name VERILOG_FILE pipeif.v
set_global_assignment -name VERILOG_FILE pipecu.v
set_global_assignment -name VERILOG_FILE pipeid.v
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_AF14 -to mem_clock
set_location_assignment PIN_AE12 -to resetn
set_location_assignment PIN_AD11 -to in_port0[0]
set_location_assignment PIN_AD12 -to in_port0[1]
set_location_assignment PIN_AE11 -to in_port0[2]
set_location_assignment PIN_AC9 -to in_port0[3]
set_location_assignment PIN_AB12 -to in_port1[0]
set_location_assignment PIN_AC12 -to in_port1[1]
set_location_assignment PIN_AF9 -to in_port1[2]
set_location_assignment PIN_AF10 -to in_port1[3]
set_location_assignment PIN_V25 -to HEX0[0]
set_location_assignment PIN_AA28 -to HEX0[1]
set_location_assignment PIN_Y27 -to HEX0[2]
set_location_assignment PIN_AB27 -to HEX0[3]
set_location_assignment PIN_AB26 -to HEX0[4]
set_location_assignment PIN_AA26 -to HEX0[5]
set_location_assignment PIN_AA25 -to HEX0[6]
set_location_assignment PIN_AA24 -to HEX1[0]
set_location_assignment PIN_Y23 -to HEX1[1]
set_location_assignment PIN_Y24 -to HEX1[2]
set_location_assignment PIN_W22 -to HEX1[3]
set_location_assignment PIN_W24 -to HEX1[4]
set_location_assignment PIN_V23 -to HEX1[5]
set_location_assignment PIN_W25 -to HEX1[6]
set_location_assignment PIN_AJ29 -to HEX2[0]
set_location_assignment PIN_AH29 -to HEX2[1]
set_location_assignment PIN_AH30 -to HEX2[2]
set_location_assignment PIN_AG30 -to HEX2[3]
set_location_assignment PIN_AF29 -to HEX2[4]
set_location_assignment PIN_AF30 -to HEX2[5]
set_location_assignment PIN_AD27 -to HEX2[6]
set_location_assignment PIN_AE26 -to HEX3[0]
set_location_assignment PIN_AE27 -to HEX3[1]
set_location_assignment PIN_AE28 -to HEX3[2]
set_location_assignment PIN_AG27 -to HEX3[3]
set_location_assignment PIN_AF28 -to HEX3[4]
set_location_assignment PIN_AG28 -to HEX3[5]
set_location_assignment PIN_AH28 -to HEX3[6]
set_location_assignment PIN_AB22 -to HEX4[6]
set_location_assignment PIN_AB25 -to HEX4[5]
set_location_assignment PIN_AB28 -to HEX4[4]
set_location_assignment PIN_AC25 -to HEX4[3]
set_location_assignment PIN_AD25 -to HEX4[2]
set_location_assignment PIN_AC27 -to HEX4[1]
set_location_assignment PIN_AD26 -to HEX4[0]
set_location_assignment PIN_AC30 -to HEX5[6]
set_location_assignment PIN_AC29 -to HEX5[5]
set_location_assignment PIN_AD30 -to HEX5[4]
set_location_assignment PIN_AC28 -to HEX5[3]
set_location_assignment PIN_AD29 -to HEX5[2]
set_location_assignment PIN_AE29 -to HEX5[1]
set_location_assignment PIN_AB23 -to HEX5[0]
set_location_assignment PIN_AD10 -to in_port2
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top