diff --git a/verilog/rtl/peripherals/Peripheral_Unit/PeriphControlRegFile.sv b/verilog/rtl/peripherals/Peripheral_Unit/PeriphControlRegFile.sv index 3bbb836..2f820d3 100644 --- a/verilog/rtl/peripherals/Peripheral_Unit/PeriphControlRegFile.sv +++ b/verilog/rtl/peripherals/Peripheral_Unit/PeriphControlRegFile.sv @@ -592,8 +592,8 @@ module PeriphControlRegFile #( end for (g = 0; g < `TIM_INST_NUM; g++) begin assign TIM_CTRL_WR[g] = ((((ADDR & ~STARTING_ADDR) >> ADDR_SCALE) == (TIM_ADDR_OFFSET + `NUM_TIM_REGS * g)) && WRITE)?1:0; - assign TIM_THRESH_H_WR[g] = ((((ADDR & ~STARTING_ADDR) >> ADDR_SCALE) == (TIM_ADDR_OFFSET + `NUM_TIM_REGS * g + 1)) && WRITE)?1:0; - assign TIM_THRESH_L_WR[g] = ((((ADDR & ~STARTING_ADDR) >> ADDR_SCALE) == (TIM_ADDR_OFFSET + `NUM_TIM_REGS * g + 2)) && WRITE)?1:0; + assign TIM_THRESH_L_WR[g] = ((((ADDR & ~STARTING_ADDR) >> ADDR_SCALE) == (TIM_ADDR_OFFSET + `NUM_TIM_REGS * g + 1)) && WRITE)?1:0; + assign TIM_THRESH_H_WR[g] = ((((ADDR & ~STARTING_ADDR) >> ADDR_SCALE) == (TIM_ADDR_OFFSET + `NUM_TIM_REGS * g + 2)) && WRITE)?1:0; end for (g = 0; g < `UART_INST_NUM; g++) begin assign UART_CR_WR[g] = ((((ADDR & ~STARTING_ADDR) >> ADDR_SCALE) == (UART_ADDR_OFFSET + `NUM_UART_REGS * g)) && WRITE)?1:0; @@ -938,17 +938,17 @@ module PeriphControlRegFile #( 36: PWM_MOD_SETPOINT_4 <= DIN; 37: PWM_EN_4 <= DIN; 39: TIM_CTRL_1 <= DIN; - 40: TIM_THRESH_H_1 <= DIN; - 41: TIM_THRESH_L_1 <= DIN; + 40: TIM_THRESH_L_1 <= DIN; + 41: TIM_THRESH_H_1 <= DIN; 45: TIM_CTRL_2 <= DIN; - 46: TIM_THRESH_H_2 <= DIN; - 47: TIM_THRESH_L_2 <= DIN; + 46: TIM_THRESH_L_2 <= DIN; + 47: TIM_THRESH_H_2 <= DIN; 51: TIM_CTRL_3 <= DIN; - 52: TIM_THRESH_H_3 <= DIN; - 53: TIM_THRESH_L_3 <= DIN; + 52: TIM_THRESH_L_3 <= DIN; + 53: TIM_THRESH_H_3 <= DIN; 57: TIM_CTRL_4 <= DIN; - 58: TIM_THRESH_H_4 <= DIN; - 59: TIM_THRESH_L_4 <= DIN; + 58: TIM_THRESH_L_4 <= DIN; + 59: TIM_THRESH_H_4 <= DIN; 63: UART_CR_1 <= DIN; 64: UART_TX_RATE_DIV_1 <= DIN; 65: UART_RX_RATE_DIV_1 <= DIN; @@ -1140,28 +1140,28 @@ module PeriphControlRegFile #( 37: DOUT <= PWM_EN_4; 38: DOUT <= PWM_SR_4; 39: DOUT <= TIM_CTRL_1; - 40: DOUT <= TIM_THRESH_H_1; - 41: DOUT <= TIM_THRESH_L_1; - 42: DOUT <= TIM_OUT_H_1; - 43: DOUT <= TIM_OUT_L_1; + 40: DOUT <= TIM_THRESH_L_1; + 41: DOUT <= TIM_THRESH_H_1; + 42: DOUT <= TIM_OUT_L_1; + 43: DOUT <= TIM_OUT_H_1; 44: DOUT <= {31'b0, TIM_INT_REG[0]}; 45: DOUT <= TIM_CTRL_2; - 46: DOUT <= TIM_THRESH_H_2; - 47: DOUT <= TIM_THRESH_L_2; - 48: DOUT <= TIM_OUT_H_2; - 49: DOUT <= TIM_OUT_L_2; + 46: DOUT <= TIM_THRESH_L_2; + 47: DOUT <= TIM_THRESH_H_2; + 48: DOUT <= TIM_OUT_L_2; + 49: DOUT <= TIM_OUT_H_2; 50: DOUT <= {31'b0, TIM_INT_REG[1]}; 51: DOUT <= TIM_CTRL_3; - 52: DOUT <= TIM_THRESH_H_3; - 53: DOUT <= TIM_THRESH_L_3; - 54: DOUT <= TIM_OUT_H_3; - 55: DOUT <= TIM_OUT_L_3; + 52: DOUT <= TIM_THRESH_L_3; + 53: DOUT <= TIM_THRESH_H_3; + 54: DOUT <= TIM_OUT_L_3; + 55: DOUT <= TIM_OUT_H_3; 56: DOUT <= {31'b0, TIM_INT_REG[2]}; 57: DOUT <= TIM_CTRL_4; - 58: DOUT <= TIM_THRESH_H_4; - 59: DOUT <= TIM_THRESH_L_4; - 60: DOUT <= TIM_OUT_H_4; - 61: DOUT <= TIM_OUT_L_4; + 58: DOUT <= TIM_THRESH_L_4; + 59: DOUT <= TIM_THRESH_H_4; + 60: DOUT <= TIM_OUT_L_4; + 61: DOUT <= TIM_OUT_H_4; 62: DOUT <= {31'b0, TIM_INT_REG[3]}; 63: DOUT <= UART_CR_1; 64: DOUT <= UART_TX_RATE_DIV_1; diff --git a/verilog/rtl/peripherals/Peripheral_Unit/Timer.sv b/verilog/rtl/peripherals/Peripheral_Unit/Timer.sv index 47474be..84f49fd 100644 --- a/verilog/rtl/peripherals/Peripheral_Unit/Timer.sv +++ b/verilog/rtl/peripherals/Peripheral_Unit/Timer.sv @@ -18,7 +18,8 @@ module Timer ( input [31:0] mtimecmp_in_l, output logic [31:0] mtime_h, // Top 32 of 64 bit timer output logic [31:0] mtime_l, // Bottom 32 of 64 bit timer - output logic timer_int + output logic timer_int, + output logic timer_pulse ); logic [63:0] mtime = 0; logic [63:0] mtimecmp = -1; @@ -36,7 +37,8 @@ module Timer ( begin mtime_h = mtime[63:32]; mtime_l = mtime[31:0]; - timer_int = ( mtime == mtimecmp ) ? 1 : 0; + timer_int = ( mtime >= mtimecmp ) ? 1 : 0; + timer_pulse = ( mtime == mtimecmp ) ? 1 : 0; end always_ff @ (posedge CLK) @@ -60,8 +62,6 @@ module Timer ( mtimecmp [63:32] <= mtimecmp_in_h; if (en_r) mtime <= mtime + 1; - if (mtime == mtimecmp) - mtime <= 0; end end diff --git a/verilog/rtl/peripherals/Peripheral_Unit/peripheral_unit.sv b/verilog/rtl/peripherals/Peripheral_Unit/peripheral_unit.sv index 87d76cf..95c9416 100644 --- a/verilog/rtl/peripherals/Peripheral_Unit/peripheral_unit.sv +++ b/verilog/rtl/peripherals/Peripheral_Unit/peripheral_unit.sv @@ -189,6 +189,7 @@ module peripheral_unit ( logic [31:0] TIM_OUT_H [`TIM_INST_NUM - 1: 0]; logic [31:0] TIM_OUT_L [`TIM_INST_NUM - 1: 0]; logic [`TIM_INST_NUM - 1: 0] TIM_INT; + logic [`TIM_INST_NUM - 1: 0] TIM_PULSE; logic [`TIM_INST_NUM - 1: 0] TIM_CTRL_WR; logic [`TIM_INST_NUM - 1: 0] TIM_THRESH_H_WR; logic [`TIM_INST_NUM - 1: 0] TIM_THRESH_L_WR; @@ -207,7 +208,8 @@ module peripheral_unit ( .mtimecmp_in_l(TIM_THRESH_L[tim_gv1]), .mtime_h(TIM_OUT_H[tim_gv1]), .mtime_l(TIM_OUT_L[tim_gv1]), - .timer_int(TIM_INT[tim_gv1])); + .timer_int(TIM_INT[tim_gv1]), + .timer_pulse(TIM_PULSE[tim_gv1])); end endgenerate @@ -740,7 +742,7 @@ module peripheral_unit ( .TIM_THRESH_L_4(TIM_THRESH_L[3]), .TIM_OUT_H_4(TIM_OUT_H[3]), .TIM_OUT_L_4(TIM_OUT_L[3]), - .TIM_INT(TIM_INT), + .TIM_INT(TIM_PULSE), .TIM_CTRL_WR(TIM_CTRL_WR), .TIM_THRESH_H_WR(TIM_THRESH_H_WR), .TIM_THRESH_L_WR(TIM_THRESH_L_WR), diff --git a/verilog/rtl/rtl/soc/modules/sram_wrap.sv b/verilog/rtl/rtl/soc/modules/sram_wrap.sv index 3966793..bd4bdde 100644 --- a/verilog/rtl/rtl/soc/modules/sram_wrap.sv +++ b/verilog/rtl/rtl/soc/modules/sram_wrap.sv @@ -87,8 +87,8 @@ module sram_wrap #( for (int i = 0; i < SRAM_NUM_BLOCKS; i++ ) begin // CS selection - if ( sram_d_req_i && i == {28'b0, sram_d_cs_addr}) cs_data[i] = 1; - if ( sram_i_req_i && i == {28'b0, sram_i_cs_addr}) cs_inst[i] = 1; + if ( sram_d_req_i && i == {29'b0, sram_d_cs_addr}) cs_data[i] = 1; + if ( sram_i_req_i && i == {29'b0, sram_i_cs_addr}) cs_inst[i] = 1; if (cs_data_prev[i] == 1'b1) sram_d_rdata_o = sram_d_read_vec[i]; if (cs_inst_prev[i] == 1'b1) sram_i_rdata_o = sram_i_read_vec[i]; @@ -208,7 +208,7 @@ module sram_wrap #( .addr1 (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]), .dout1 (sram_i_read_vec[5]) ); - + sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram6 ( `ifdef USE_POWER_PINS .vccd1(vccd1), // 1.8V @@ -281,7 +281,6 @@ module sram_wrap #( .dout1 (sram_i_read_vec[9]) ); - `ifdef VERILATOR logic [31:0] _unused; diff --git a/verilog/rtl/user_defines.v b/verilog/rtl/user_defines.v index ed7c4cd..57a3a26 100644 --- a/verilog/rtl/user_defines.v +++ b/verilog/rtl/user_defines.v @@ -57,10 +57,10 @@ `define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_USER_STD_INPUT_PULLUP `define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN `define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_USER_STD_OUTPUT -`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_USER_STD_OUTPUT -`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_OUTPUT -`define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_USER_STD_OUTPUT -`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_USER_STD_OUTPUT +`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL // Configurations of GPIO 14 to 24 are used on caravel but not caravan. `define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_USER_STD_OUTPUT