diff --git a/verilog/rtl/core/rtl/core/modules/alu.sv b/verilog/rtl/core/rtl/core/modules/alu.sv
index b05e280..5f9add3 100644
--- a/verilog/rtl/core/rtl/core/modules/alu.sv
+++ b/verilog/rtl/core/rtl/core/modules/alu.sv
@@ -26,8 +26,8 @@ module alu #(
             XOR:  out_o = a_i ^ b_i;
             SRL:  out_o = a_i >> b_i[4:0];
             SLL:  out_o = a_i << b_i[4:0];
-            SRA:  out_o = signed'(a_i) >>> b_i[4:0];
-            SLT:  out_o = signed'(a_i) < signed'(b_i) ? 32'd1: '0;
+            SRA:  out_o = $signed(a_i) >>> b_i[4:0];
+            SLT:  out_o = $signed(a_i) < $signed(b_i) ? 32'd1: '0;
             SLTU: out_o = a_i < b_i ? 32'd1: '0;
             PASS: out_o = a_i;
             default: out_o = '0; 
diff --git a/verilog/rtl/core/rtl/core/modules/branch_gen.sv b/verilog/rtl/core/rtl/core/modules/branch_gen.sv
index 9d8ac81..ff93e3e 100644
--- a/verilog/rtl/core/rtl/core/modules/branch_gen.sv
+++ b/verilog/rtl/core/rtl/core/modules/branch_gen.sv
@@ -20,7 +20,7 @@ module branch_gen (
     // Base conditionals
     logic eq,lt,ltu;
     assign eq = rs1_data_i == rs2_data_i;
-    assign lt = signed'(rs1_data_i) < signed'(rs2_data_i);
+    assign lt = $signed(rs1_data_i) < $signed(rs2_data_i);
     assign ltu = rs1_data_i < rs2_data_i;
     
     always_comb begin
diff --git a/verilog/rtl/core/rtl/core/modules/immed_gen.sv b/verilog/rtl/core/rtl/core/modules/immed_gen.sv
index d470797..2607cc4 100644
--- a/verilog/rtl/core/rtl/core/modules/immed_gen.sv
+++ b/verilog/rtl/core/rtl/core/modules/immed_gen.sv
@@ -16,16 +16,16 @@ module immed_gen(
     output logic [31:0] u_immed_o,
     output logic [31:0] j_immed_o
 );
-    assign i_immed_o = 32'(signed'(inst_i[31:20]));
+    assign i_immed_o = 32'($signed(inst_i[31:20]));
 
-    assign s_immed_o = 32'(signed'({inst_i[31:25], inst_i[11:7]}));
+    assign s_immed_o = 32'($signed({inst_i[31:25], inst_i[11:7]}));
 
-    assign b_immed_o = 32'(signed'({inst_i[31], inst_i[7], inst_i[30:25], 
+    assign b_immed_o = 32'($signed({inst_i[31], inst_i[7], inst_i[30:25], 
                             inst_i[11:8], 1'b0}));
 
-    assign u_immed_o = 32'(signed'({inst_i[31:12], 12'b0}));
+    assign u_immed_o = 32'($signed({inst_i[31:12], 12'b0}));
 
-    assign j_immed_o = 32'(signed'({inst_i[31], inst_i[19:12], inst_i[20], 
+    assign j_immed_o = 32'($signed({inst_i[31], inst_i[19:12], inst_i[20], 
                             inst_i[30:21], 1'b0}));
 
     ////////////////////
diff --git a/verilog/rtl/core/rtl/core/modules/mem_prep.sv b/verilog/rtl/core/rtl/core/modules/mem_prep.sv
index 3c8585d..70a3d73 100644
--- a/verilog/rtl/core/rtl/core/modules/mem_prep.sv
+++ b/verilog/rtl/core/rtl/core/modules/mem_prep.sv
@@ -27,7 +27,7 @@ module mem_prep (
     logic [31:0] pre_write_data; // Write data as provided by the pipeline
 
     logic [1:0]  req_byte_idx;
-    logic [3:0]  req_strobe;;
+    logic [3:0]  req_strobe;
     logic [31:0] req_write_data; // Processed data for the memory interface request
 
     assign pre_width        = mem_width_i;