From c9fa101290c9c93ec2daa6dca4b7bc7b3a71b297 Mon Sep 17 00:00:00 2001
From: Peter=Herrmann <herrmannp7@gmail.com>
Date: Thu, 19 Oct 2023 17:40:48 -0700
Subject: [PATCH] Sending 12 SRAMs with potential LVS fix

---
 .../macros/sky130_sram_2kbyte_1rw1r_32x512_8.v    |  4 ++--
 openlane/soc/macro.cfg                            | 15 +++++++++++++--
 verilog/rtl/rtl/soc/modules/sram_wrap.sv          |  6 +++---
 3 files changed, 18 insertions(+), 7 deletions(-)

diff --git a/openlane/macros/sky130_sram_2kbyte_1rw1r_32x512_8.v b/openlane/macros/sky130_sram_2kbyte_1rw1r_32x512_8.v
index 87b7650..911b484 100644
--- a/openlane/macros/sky130_sram_2kbyte_1rw1r_32x512_8.v
+++ b/openlane/macros/sky130_sram_2kbyte_1rw1r_32x512_8.v
@@ -21,8 +21,8 @@ module sky130_sram_2kbyte_1rw1r_32x512_8(
   parameter RAM_DEPTH = 1 << ADDR_WIDTH;
   // FIXME: This delay is arbitrary.
   parameter DELAY = 3 ;
-  parameter VERBOSE = 1 ; //Set to 0 to only display warnings
-  parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
+  parameter VERBOSE = 1 ; // LVS checking
+  parameter T_HOLD = 1 ; // LVS checking
 
 `ifdef USE_POWER_PINS
     inout vccd1;
diff --git a/openlane/soc/macro.cfg b/openlane/soc/macro.cfg
index 5024891..2aa423a 100644
--- a/openlane/soc/macro.cfg
+++ b/openlane/soc/macro.cfg
@@ -1,2 +1,13 @@
-sram.sram_blocks\[0\].sram1 1058 2383.47 R0
-sram.sram_blocks\[1\].sram1 1058 516.8 MX
\ No newline at end of file
+sram.sram_blocks\[0\].sram1 566.9 150 R0
+sram.sram_blocks\[1\].sram1 566.9 686.692 MX
+sram.sram_blocks\[2\].sram1 566.9 1223.384 R0
+sram.sram_blocks\[3\].sram1 566.9 1760.076 MX
+sram.sram_blocks\[4\].sram1 566.9 2296.768 R0
+sram.sram_blocks\[5\].sram1 566.9 2833.46 MX
+
+sram.sram_blocks\[6\].sram1 1550 150 MY
+sram.sram_blocks\[7\].sram1 1550 686.692 R180
+sram.sram_blocks\[8\].sram1 1550 1223.384 MY
+sram.sram_blocks\[9\].sram1 1550 1760.076 R180
+sram.sram_blocks\[10\].sram1 1550 2296.768 MY
+sram.sram_blocks\[11\].sram1 1550 2833.46 R180
\ No newline at end of file
diff --git a/verilog/rtl/rtl/soc/modules/sram_wrap.sv b/verilog/rtl/rtl/soc/modules/sram_wrap.sv
index 33956ee..f3c91a1 100644
--- a/verilog/rtl/rtl/soc/modules/sram_wrap.sv
+++ b/verilog/rtl/rtl/soc/modules/sram_wrap.sv
@@ -3,7 +3,7 @@
 
 module sram_wrap #(
     parameter SRAM_BASE_ADDR      = 32'h8000_0000,
-    parameter SRAM_NUM_BLOCKS     = 2,
+    parameter SRAM_NUM_BLOCKS     = 12,
     parameter SRAM_BLOCK_SIZE     = 512,
     parameter SRAM_LOG_BLOCK_SIZE = $clog2(SRAM_BLOCK_SIZE),
     parameter SRAM_END_ADDR       = (SRAM_BASE_ADDR + (SRAM_NUM_BLOCKS * SRAM_BLOCK_SIZE)),
@@ -78,8 +78,8 @@ module sram_wrap #(
         for (int i = 0; i < SRAM_NUM_BLOCKS; i++ )
         begin
             // CS selection
-            if ( sram_d_req_i && i == {31'b0, sram_d_cs_addr}) cs_data[i] = 1;
-            if ( sram_i_req_i && i == {31'b0, sram_i_cs_addr}) cs_inst[i] = 1;
+            if ( sram_d_req_i && i == {28'b0, sram_d_cs_addr}) cs_data[i] = 1;
+            if ( sram_i_req_i && i == {28'b0, sram_i_cs_addr}) cs_inst[i] = 1;
 
             if (cs_data_prev[i] == 1'b1) sram_d_rdata_o = sram_d_read_vec[i];
             if (cs_inst_prev[i] == 1'b1) sram_i_rdata_o = sram_i_read_vec[i];