diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index 02f5bb0..ef16e85 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -4,7 +4,7 @@
     "RUN_LVS": 1,
     "RUN_MAGIC_DRC": 1,
     "YOSYS_REWRITE_VERILOG": 1,
-    "GRT_ALLOW_CONGESTION": 0,
+    "GRT_ALLOW_CONGESTION": 1,
     "QUIT_ON_LINTER_ERRORS": 0,
     "GRT_ADJUSTMENT": 0.1,
 	"MACRO_PLACEMENT_CFG": "dir::macro.cfg",
@@ -78,7 +78,7 @@
     "ROUTING_CORES": 20,
 	"KLAYOUT_XOR_THREADS": 20,
 	"FP_IO_UNMATCHED_ERROR": 0,
-    "FP_PDN_MACRO_HOOKS": "soc_i.sram.sram0 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram1 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram2 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram3 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram4 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram5 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram6 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram7 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram8 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram9 vccd1 vssd1 vccd1 vssd1",
+    "FP_PDN_MACRO_HOOKS": "soc_i.sram.sram0 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram1 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram2 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram3 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram4 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram5 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram6 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram7 vccd1 vssd1 vccd1 vssd1",
 	"CLOCK_PORT": "user_clock2",
     "FP_SIZING": "absolute",
     "DIE_AREA": "0 0 2920 3520",
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 90df956..88f531a 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,11 +1,9 @@
-soc_i.sram.sram0 376.9 200 R180
-soc_i.sram.sram1 376.9 875.865 MY
-soc_i.sram.sram2 376.9 1551.73 R180
-soc_i.sram.sram3 376.9 2227.595 MY
-soc_i.sram.sram4 376.9 2903.46 R180
+soc_i.sram.sram0 376.9 300 R180
+soc_i.sram.sram1 376.9 1134.5 MY
+soc_i.sram.sram2 376.9 1968.97 R180
+soc_i.sram.sram3 376.9 2803.46 MY
 
-soc_i.sram.sram5 1860 200 MX
-soc_i.sram.sram6 1860 875.865 R0
-soc_i.sram.sram7 1860 1551.73 MX
-soc_i.sram.sram8 1860 2227.595 R0
-soc_i.sram.sram9 1860 2903.46 MX
+soc_i.sram.sram4 1860 300 MX
+soc_i.sram.sram5 1860 1134.5 R0
+soc_i.sram.sram6 1860 1968.97 MX
+soc_i.sram.sram7 1860 2803.46 R0
diff --git a/verilog/rtl/rtl/soc/modules/sram_wrap.sv b/verilog/rtl/rtl/soc/modules/sram_wrap.sv
index 3966793..efe14a4 100644
--- a/verilog/rtl/rtl/soc/modules/sram_wrap.sv
+++ b/verilog/rtl/rtl/soc/modules/sram_wrap.sv
@@ -12,7 +12,7 @@
 
 module sram_wrap #(
     parameter SRAM_BASE_ADDR      = 32'h8000_0000,
-    parameter SRAM_NUM_BLOCKS     = 10,
+    parameter SRAM_NUM_BLOCKS     = 8,
     parameter SRAM_BLOCK_SIZE     = 512,
     parameter SRAM_LOG_BLOCK_SIZE = $clog2(SRAM_BLOCK_SIZE),
     parameter SRAM_END_ADDR       = (SRAM_BASE_ADDR + (SRAM_NUM_BLOCKS * SRAM_BLOCK_SIZE)),
@@ -87,8 +87,8 @@ module sram_wrap #(
         for (int i = 0; i < SRAM_NUM_BLOCKS; i++ )
         begin
             // CS selection
-            if ( sram_d_req_i && i == {28'b0, sram_d_cs_addr}) cs_data[i] = 1;
-            if ( sram_i_req_i && i == {28'b0, sram_i_cs_addr}) cs_inst[i] = 1;
+            if ( sram_d_req_i && i == {29'b0, sram_d_cs_addr}) cs_data[i] = 1;
+            if ( sram_i_req_i && i == {29'b0, sram_i_cs_addr}) cs_inst[i] = 1;
 
             if (cs_data_prev[i] == 1'b1) sram_d_rdata_o = sram_d_read_vec[i];
             if (cs_inst_prev[i] == 1'b1) sram_i_rdata_o = sram_i_read_vec[i];
@@ -245,42 +245,6 @@ module sram_wrap #(
         .dout1     (sram_i_read_vec[7]) 
     );
 
-    sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram8 (
-    `ifdef USE_POWER_PINS
-        .vccd1(vccd1), // 1.8V
-        .vssd1(vssd1), // Digital ground
-    `endif
-        .clk0      (clk_i),
-        .csb0      (~cs_data[8]),   // Active Low
-        .web0      (~sram_d_we_i),  // Active Low
-        .wmask0    (sram_d_be_i),
-        .addr0     (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
-        .din0      (sram_d_wdata_i), 
-        .dout0     (sram_d_read_vec[8]), 
-        .clk1      (clk_i),
-        .csb1      (~cs_inst[8]),    // Active Low
-        .addr1     (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]), 
-        .dout1     (sram_i_read_vec[8]) 
-    );
-
-    sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram9 (
-    `ifdef USE_POWER_PINS
-        .vccd1(vccd1), // 1.8V
-        .vssd1(vssd1), // Digital ground
-    `endif
-        .clk0      (clk_i),
-        .csb0      (~cs_data[9]),   // Active Low
-        .web0      (~sram_d_we_i),  // Active Low
-        .wmask0    (sram_d_be_i),
-        .addr0     (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
-        .din0      (sram_d_wdata_i), 
-        .dout0     (sram_d_read_vec[9]), 
-        .clk1      (clk_i),
-        .csb1      (~cs_inst[9]),    // Active Low
-        .addr1     (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]), 
-        .dout1     (sram_i_read_vec[9]) 
-    );
-
 
 `ifdef VERILATOR
     logic [31:0] _unused;