From 17ce9f326389cccfeb02e83dd69dba558dbe78c1 Mon Sep 17 00:00:00 2001 From: Peter-Herrmann Date: Mon, 16 Oct 2023 17:23:22 -0700 Subject: [PATCH] making verilog black box empty --- .../sky130_sram_2kbyte_1rw1r_32x512_8.v | 150 +++++++++--------- 1 file changed, 75 insertions(+), 75 deletions(-) diff --git a/openlane/macros/sky130_sram_2kbyte_1rw1r_32x512_8.v b/openlane/macros/sky130_sram_2kbyte_1rw1r_32x512_8.v index 20437c5..d89a565 100644 --- a/openlane/macros/sky130_sram_2kbyte_1rw1r_32x512_8.v +++ b/openlane/macros/sky130_sram_2kbyte_1rw1r_32x512_8.v @@ -21,90 +21,90 @@ module sky130_sram_2kbyte_1rw1r_32x512_8( // FIXME: This delay is arbitrary. parameter DELAY = 3 ; -`ifdef USE_POWER_PINS - inout vccd1; - inout vssd1; -`endif - input clk0; // clock - input csb0; // active low chip select - input web0; // active low write control - input [NUM_WMASKS-1:0] wmask0; // write mask - input [ADDR_WIDTH-1:0] addr0; - input [DATA_WIDTH-1:0] din0; - output [DATA_WIDTH-1:0] dout0; - input clk1; // clock - input csb1; // active low chip select - input [ADDR_WIDTH-1:0] addr1; - output [DATA_WIDTH-1:0] dout1; +// `ifdef USE_POWER_PINS +// inout vccd1; +// inout vssd1; +// `endif +// input clk0; // clock +// input csb0; // active low chip select +// input web0; // active low write control +// input [NUM_WMASKS-1:0] wmask0; // write mask +// input [ADDR_WIDTH-1:0] addr0; +// input [DATA_WIDTH-1:0] din0; +// output [DATA_WIDTH-1:0] dout0; +// input clk1; // clock +// input csb1; // active low chip select +// input [ADDR_WIDTH-1:0] addr1; +// output [DATA_WIDTH-1:0] dout1; - reg csb0_reg; - reg web0_reg; - reg [NUM_WMASKS-1:0] wmask0_reg; - reg [ADDR_WIDTH-1:0] addr0_reg; - reg [DATA_WIDTH-1:0] din0_reg; - reg [DATA_WIDTH-1:0] dout0; +// reg csb0_reg; +// reg web0_reg; +// reg [NUM_WMASKS-1:0] wmask0_reg; +// reg [ADDR_WIDTH-1:0] addr0_reg; +// reg [DATA_WIDTH-1:0] din0_reg; +// reg [DATA_WIDTH-1:0] dout0; - // All inputs are registers - always @(posedge clk0) - begin - csb0_reg <= csb0; - web0_reg <= web0; - wmask0_reg <= wmask0; - addr0_reg <= addr0; - din0_reg <= din0; - end +// // All inputs are registers +// always @(posedge clk0) +// begin +// csb0_reg <= csb0; +// web0_reg <= web0; +// wmask0_reg <= wmask0; +// addr0_reg <= addr0; +// din0_reg <= din0; +// end - reg csb1_reg; - reg [ADDR_WIDTH-1:0] addr1_reg; - reg [DATA_WIDTH-1:0] dout1; +// reg csb1_reg; +// reg [ADDR_WIDTH-1:0] addr1_reg; +// reg [DATA_WIDTH-1:0] dout1; - // All inputs are registers - always @(posedge clk1) - begin - csb1_reg <= csb1; - addr1_reg <= addr1; - end +// // All inputs are registers +// always @(posedge clk1) +// begin +// csb1_reg <= csb1; +// addr1_reg <= addr1; +// end -reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; +// reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; - // Memory Write Block Port 0 - // Write Operation : When web0 = 0, csb0 = 0 - always @ (negedge clk0) - begin : MEM_WRITE0 - if ( !csb0_reg && !web0_reg ) begin - if (wmask0_reg[0]) - mem[addr0_reg][7:0] <= din0_reg[7:0]; - if (wmask0_reg[1]) - mem[addr0_reg][15:8] <= din0_reg[15:8]; - if (wmask0_reg[2]) - mem[addr0_reg][23:16] <= din0_reg[23:16]; - if (wmask0_reg[3]) - mem[addr0_reg][31:24] <= din0_reg[31:24]; - end - end +// // Memory Write Block Port 0 +// // Write Operation : When web0 = 0, csb0 = 0 +// always @ (negedge clk0) +// begin : MEM_WRITE0 +// if ( !csb0_reg && !web0_reg ) begin +// if (wmask0_reg[0]) +// mem[addr0_reg][7:0] <= din0_reg[7:0]; +// if (wmask0_reg[1]) +// mem[addr0_reg][15:8] <= din0_reg[15:8]; +// if (wmask0_reg[2]) +// mem[addr0_reg][23:16] <= din0_reg[23:16]; +// if (wmask0_reg[3]) +// mem[addr0_reg][31:24] <= din0_reg[31:24]; +// end +// end - // Memory Read Block Port 0 - // Read Operation : When web0 = 1, csb0 = 0 - always @ (negedge clk0) - begin : MEM_READ0 - if (!csb0_reg && web0_reg) - dout0 <= mem[addr0_reg]; - end +// // Memory Read Block Port 0 +// // Read Operation : When web0 = 1, csb0 = 0 +// always @ (negedge clk0) +// begin : MEM_READ0 +// if (!csb0_reg && web0_reg) +// dout0 <= mem[addr0_reg]; +// end - // Memory Read Block Port 1 - // Read Operation : When web1 = 1, csb1 = 0 - always @ (negedge clk1) - begin : MEM_READ1 - if (!csb1_reg) - dout1 <= mem[addr1_reg]; - end +// // Memory Read Block Port 1 +// // Read Operation : When web1 = 1, csb1 = 0 +// always @ (negedge clk1) +// begin : MEM_READ1 +// if (!csb1_reg) +// dout1 <= mem[addr1_reg]; +// end - `ifdef VERILATOR - logic [31:0] _unused; +// `ifdef VERILATOR +// logic [31:0] _unused; - always_comb begin : terminations - _unused[1:0] = DELAY; - end - `endif +// always_comb begin : terminations +// _unused[1:0] = DELAY; +// end +// `endif endmodule