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Fix for single element designs #347

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merged 3 commits into from
Apr 30, 2024
Merged

Fix for single element designs #347

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c918dbc
single net and test
ducky64 Apr 30, 2024
2c5f249
fix test
ducky64 Apr 30, 2024
ed249f2
Update test_kicad_import_netlist.py
ducky64 Apr 30, 2024
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15 changes: 9 additions & 6 deletions electronics_abstract_parts/test_kicad_import_netlist.py
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Original file line number Diff line number Diff line change
Expand Up @@ -71,16 +71,19 @@ def test_netlist(self):
self.assertIn(NetBlock('Package_TO_SOT_SMD:SOT-23', 'U1',
# expected value is wonky because netlisting combines part and value
'Sensor_Temperature:MCP9700AT-ETT', 'MCP9700AT-ETT',
['dut', 'U1'], ['U1'],
['electronics_model.KiCadSchematicBlock.KiCadBlackbox']),
['dut', 'U1'], ['dut', 'U1'],
['electronics_model.test_kicad_import_blackbox.KiCadBlackboxBlock',
'electronics_model.KiCadSchematicBlock.KiCadBlackbox']),
net.blocks)
self.assertIn(NetBlock('Symbol:Symbol_ESD-Logo_CopperTop', 'SYM1',
# expected value is wonky because netlisting combines part and value
'Graphic:SYM_ESD_Small', 'SYM_ESD_Small',
['dut', 'SYM1'], ['SYM1'],
['electronics_model.KiCadSchematicBlock.KiCadBlackbox']),
['dut', 'SYM1'], ['dut', 'SYM1'],
['electronics_model.test_kicad_import_blackbox.KiCadBlackboxBlock',
'electronics_model.KiCadSchematicBlock.KiCadBlackbox']),
net.blocks)
self.assertIn(NetBlock('Resistor_SMD:R_0603_1608Metric', 'R1', '', '',
['dut', 'res'], ['res'],
['electronics_abstract_parts.test_kicad_import_netlist.DummyResistor']),
['dut', 'res'], ['dut', 'res'],
['electronics_model.test_kicad_import_blackbox.KiCadBlackboxBlock',
'electronics_abstract_parts.test_kicad_import_netlist.DummyResistor']),
net.blocks)
2 changes: 1 addition & 1 deletion electronics_model/NetlistGenerator.py
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Original file line number Diff line number Diff line change
Expand Up @@ -79,7 +79,7 @@ def process_blocklike(self, path: TransformUtil.Path, block: Union[edgir.Link, e
short_path = self.short_paths[path]
class_path = self.class_paths[path]

if len(main_internal_blocks) == 1:
if len(main_internal_blocks) == 1 and short_path: # never shorten top-level blocks
name = list(main_internal_blocks.keys())[0]
self.short_paths[path.append_block(name)] = short_path
self.class_paths[path.append_block(name)] = class_path
Expand Down
19 changes: 17 additions & 2 deletions electronics_model/test_netlist.py
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Original file line number Diff line number Diff line change
Expand Up @@ -24,8 +24,8 @@ class TestFakeSource(FootprintBlock):
def __init__(self) -> None:
super().__init__()

self.pos = self.Port(VoltageSource())
self.neg = self.Port(VoltageSource())
self.pos = self.Port(VoltageSource(), optional=True)
self.neg = self.Port(VoltageSource(), optional=True)

def contents(self) -> None:
super().contents()
Expand Down Expand Up @@ -63,6 +63,13 @@ def contents(self) -> None:
)


class TestSinglePart(Block):
def contents(self) -> None:
super().contents()

self.source = self.Block(TestFakeSource())


class TestBasicCircuit(Block):
def contents(self) -> None:
super().contents()
Expand Down Expand Up @@ -182,6 +189,14 @@ def generate_net(design: Type[Block], refinements: Refinements = Refinements()):
compiled.append_values(RefdesRefinementPass().run(compiled))
return NetlistTransform(compiled).run()

def test_single_netlist(self) -> None:
net = self.generate_net(TestSinglePart)

# check that the top-level path element is never pruned, even when the design is one element
self.assertIn(NetBlock('Capacitor_SMD:C_0603_1608Metric', 'C1', '', '1uF',
['source'], ['source'],
['electronics_model.test_netlist.TestFakeSource']), net.blocks)

def test_basic_netlist(self) -> None:
net = self.generate_net(TestBasicCircuit)

Expand Down
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