From d4b2c7dd85fe775ecddc8b79b14c73896fb82f72 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Mon, 7 Aug 2023 22:57:53 -0700 Subject: [PATCH] consistent-ize --- electronics_abstract_parts/MergedBlocks.py | 4 +-- electronics_abstract_parts/__init__.py | 2 +- electronics_lib/Fpga_Ice40up.py | 2 +- electronics_lib/Microcontroller_Esp32c3.py | 2 +- electronics_lib/Microcontroller_Esp32s3.py | 2 +- electronics_model/test_bundle_netlist.py | 36 +++++++++++----------- electronics_model/test_i2c_link.py | 4 +-- 7 files changed, 26 insertions(+), 26 deletions(-) diff --git a/electronics_abstract_parts/MergedBlocks.py b/electronics_abstract_parts/MergedBlocks.py index 44ea328e7..fff514243 100644 --- a/electronics_abstract_parts/MergedBlocks.py +++ b/electronics_abstract_parts/MergedBlocks.py @@ -108,7 +108,7 @@ def connected_from(self, *inputs: Port[AnalogLink]) -> 'MergedAnalogSource': return self -class MergedSpiMaster(DummyDevice, GeneratorBlock): +class MergedSpiController(DummyDevice, GeneratorBlock): def __init__(self) -> None: super().__init__() self.ins = self.Port(Vector(SpiPeripheral.empty())) @@ -130,7 +130,7 @@ def generate(self): self.connect(self.sck_merge.ins.request(in_request), in_port.sck) self.connect(self.mosi_merge.ins.request(in_request), in_port.mosi) - def connected_from(self, *ins: Port[SpiLink]) -> 'MergedSpiMaster': + def connected_from(self, *ins: Port[SpiLink]) -> 'MergedSpiController': for in_port in ins: cast(Block, builder.get_enclosing_block()).connect(in_port, self.ins.request()) return self diff --git a/electronics_abstract_parts/__init__.py b/electronics_abstract_parts/__init__.py index 13edc4473..7097af296 100644 --- a/electronics_abstract_parts/__init__.py +++ b/electronics_abstract_parts/__init__.py @@ -89,4 +89,4 @@ from .DummyDevices import DummyPassive, DummyVoltageSource, DummyVoltageSink, DummyDigitalSink, DummyAnalogSink from .DummyDevices import ForcedVoltageCurrentDraw, ForcedVoltage, ForcedDigitalSinkCurrentDraw -from .MergedBlocks import MergedVoltageSource, MergedDigitalSource, MergedAnalogSource, MergedSpiMaster +from .MergedBlocks import MergedVoltageSource, MergedDigitalSource, MergedAnalogSource, MergedSpiController diff --git a/electronics_lib/Fpga_Ice40up.py b/electronics_lib/Fpga_Ice40up.py index 7274f8715..ca81f13ef 100644 --- a/electronics_lib/Fpga_Ice40up.py +++ b/electronics_lib/Fpga_Ice40up.py @@ -285,7 +285,7 @@ def contents(self): # this defaults to flash programming, but to use CRAM programming you can swap the # SDI/SDO pins on the debug probe and disconnect the CS line - self.spi_merge = self.Block(MergedSpiMaster()).connected_from(self.ic.spi_config, self.prog.spi) + self.spi_merge = self.Block(MergedSpiController()).connected_from(self.ic.spi_config, self.prog.spi) self.connect(self.spi_merge.out, self.mem.spi) self.connect(self.ic.spi_config_cs, self.prog.cs) (self.cs_jmp, ), _ = self.chain(self.ic.spi_config_cs, self.Block(DigitalJumper()), self.mem.cs) diff --git a/electronics_lib/Microcontroller_Esp32c3.py b/electronics_lib/Microcontroller_Esp32c3.py index 2af4ff438..fa6503b03 100644 --- a/electronics_lib/Microcontroller_Esp32c3.py +++ b/electronics_lib/Microcontroller_Esp32c3.py @@ -64,7 +64,7 @@ def _io_pinmap(self) -> PinMapUtil: ) uart_model = UartPort(DigitalBidir.empty()) - spi_model = SpiController(DigitalBidir.empty(), (0, 60) * MHertz) # section 3.4.2, max block in GP master mode + spi_model = SpiController(DigitalBidir.empty(), (0, 60) * MHertz) # section 3.4.2, max block in GP controller mode spi_peripheral_model = SpiPeripheral(DigitalBidir.empty(), (0, 60) * MHertz) i2c_model = I2cController(DigitalBidir.empty()) # section 3.4.4, supporting 100/400 and up to 800 kbit/s i2c_target_model = I2cTarget(DigitalBidir.empty()) diff --git a/electronics_lib/Microcontroller_Esp32s3.py b/electronics_lib/Microcontroller_Esp32s3.py index cdc1067ac..5e1b55582 100644 --- a/electronics_lib/Microcontroller_Esp32s3.py +++ b/electronics_lib/Microcontroller_Esp32s3.py @@ -44,7 +44,7 @@ def _io_pinmap(self) -> PinMapUtil: adc_model = AnalogSink.from_supply(gnd, pwr) # table 4-5, no other specs given uart_model = UartPort(DigitalBidir.empty()) # section 3.5.5, up to 5Mbps - spi_model = SpiController(DigitalBidir.empty(), (0, 80) * MHertz) # section 3.5.2, 80MHz in master, 60MHz in slave + spi_model = SpiController(DigitalBidir.empty(), (0, 80) * MHertz) # section 3.5.2, 80MHz in controller, 60MHz in peripheral spi_peripheral_model = SpiPeripheral(DigitalBidir.empty(), (0, 80) * MHertz) i2c_model = I2cController(DigitalBidir.empty()) # section 3.5.6, 100/400kHz and up to 800kbit/s i2c_target_model = I2cController(DigitalBidir.empty()) diff --git a/electronics_model/test_bundle_netlist.py b/electronics_model/test_bundle_netlist.py index f3844e2d6..a1b61daf9 100644 --- a/electronics_model/test_bundle_netlist.py +++ b/electronics_model/test_bundle_netlist.py @@ -10,7 +10,7 @@ from .test_netlist import NetlistTestCase -class TestFakeSpiMaster(FootprintBlock): +class TestFakeSpiController(FootprintBlock): def __init__(self) -> None: super().__init__() @@ -20,7 +20,7 @@ def __init__(self) -> None: def contents(self) -> None: super().contents() - self.footprint( # it's anyone's guess why the resistor array is a SPI master + self.footprint( # it's anyone's guess why the resistor array is a SPI controller 'R', 'Resistor_SMD:R_Array_Concave_2x0603', { '0': self.cs_out_1, # the mythical and elusive pin 0 @@ -29,11 +29,11 @@ def contents(self) -> None: '3': self.spi.miso, '4': self.spi.mosi, }, - value='WeirdSpiMaster' + value='WeirdSpiController' ) -class TestFakeSpiSlave(FootprintBlock): +class TestFakeSpiPeripheral(FootprintBlock): def __init__(self) -> None: super().__init__() @@ -42,7 +42,7 @@ def __init__(self) -> None: def contents(self) -> None: super().contents() - self.footprint( # it's anyone's guess why this resistor array has a different pinning in slave mode + self.footprint( # it's anyone's guess why this resistor array has a different pinning in peripheral mode 'R', 'Resistor_SMD:R_Array_Concave_2x0603', { '1': self.spi.sck, @@ -50,7 +50,7 @@ def contents(self) -> None: '3': self.spi.miso, '4': self.cs_in, }, - value='WeirdSpiSlave' + value='WeirdSpiPeripheral' ) @@ -58,9 +58,9 @@ class TestSpiCircuit(Block): def contents(self) -> None: super().contents() - self.controller = self.Block(TestFakeSpiMaster()) - self.peripheral1 = self.Block(TestFakeSpiSlave()) - self.peripheral2 = self.Block(TestFakeSpiSlave()) + self.controller = self.Block(TestFakeSpiController()) + self.peripheral1 = self.Block(TestFakeSpiPeripheral()) + self.peripheral2 = self.Block(TestFakeSpiPeripheral()) self.spi_link = self.connect(self.controller.spi, self.peripheral1.spi, self.peripheral2.spi) self.cs1_link = self.connect(self.controller.cs_out_1, self.peripheral1.cs_in) @@ -152,15 +152,15 @@ def test_spi_netlist(self) -> None: Pin('peripheral2', '3'), ]) - self.assertEqual(net.blocks['controller'], FBlock('Resistor_SMD:R_Array_Concave_2x0603', 'R1', '', 'WeirdSpiMaster', - ['controller'], ['controller'], - ['electronics_model.test_bundle_netlist.TestFakeSpiMaster'])) - self.assertEqual(net.blocks['peripheral1'], FBlock('Resistor_SMD:R_Array_Concave_2x0603', 'R2', '', 'WeirdSpiSlave', - ['peripheral1'], ['peripheral1'], - ['electronics_model.test_bundle_netlist.TestFakeSpiSlave'])) - self.assertEqual(net.blocks['peripheral2'], FBlock('Resistor_SMD:R_Array_Concave_2x0603', 'R3', '', 'WeirdSpiSlave', - ['peripheral2'], ['peripheral2'], - ['electronics_model.test_bundle_netlist.TestFakeSpiSlave'])) + self.assertEqual(net.blocks['controller'], FBlock( + 'Resistor_SMD:R_Array_Concave_2x0603', 'R1', '', 'WeirdSpiController', + ['controller'], ['controller'], ['electronics_model.test_bundle_netlist.TestFakeSpiController'])) + self.assertEqual(net.blocks['peripheral1'], FBlock( + 'Resistor_SMD:R_Array_Concave_2x0603', 'R2', '', 'WeirdSpiPeripheral', + ['peripheral1'], ['peripheral1'], ['electronics_model.test_bundle_netlist.TestFakeSpiPeripheral'])) + self.assertEqual(net.blocks['peripheral2'], FBlock( + 'Resistor_SMD:R_Array_Concave_2x0603', 'R3', '', 'WeirdSpiPeripheral', + ['peripheral2'], ['peripheral2'], ['electronics_model.test_bundle_netlist.TestFakeSpiPeripheral'])) def test_uart_netlist(self) -> None: net = NetlistTestCase.generate_net(TestUartCircuit) diff --git a/electronics_model/test_i2c_link.py b/electronics_model/test_i2c_link.py index 768b42d3f..a09ca6ee9 100644 --- a/electronics_model/test_i2c_link.py +++ b/electronics_model/test_i2c_link.py @@ -45,11 +45,11 @@ def __init__(self): class I2cConflictTest(DesignTop): def __init__(self): super().__init__() - self.master = self.Block(I2cControllerBlock()) + self.controller = self.Block(I2cControllerBlock()) self.pull = self.Block(I2cPullupBlock()) self.device1 = self.Block(I2cTargetBlock(1)) self.device2 = self.Block(I2cTargetBlock(1)) - self.link = self.connect(self.master.port, self.pull.port, self.device1.port, self.device2.port) + self.link = self.connect(self.controller.port, self.pull.port, self.device1.port, self.device2.port) class I2cTestCase(unittest.TestCase):