From c918dbc47d9ad7cbb6a28863b80bf3b50b1345e6 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Tue, 30 Apr 2024 09:56:48 -0700 Subject: [PATCH] single net and test --- electronics_model/NetlistGenerator.py | 2 +- electronics_model/test_netlist.py | 19 +++++++++++++++++-- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/electronics_model/NetlistGenerator.py b/electronics_model/NetlistGenerator.py index 131478fd8..c7b62340b 100644 --- a/electronics_model/NetlistGenerator.py +++ b/electronics_model/NetlistGenerator.py @@ -79,7 +79,7 @@ def process_blocklike(self, path: TransformUtil.Path, block: Union[edgir.Link, e short_path = self.short_paths[path] class_path = self.class_paths[path] - if len(main_internal_blocks) == 1: + if len(main_internal_blocks) == 1 and short_path: # never shorten top-level blocks name = list(main_internal_blocks.keys())[0] self.short_paths[path.append_block(name)] = short_path self.class_paths[path.append_block(name)] = class_path diff --git a/electronics_model/test_netlist.py b/electronics_model/test_netlist.py index 910a86b1d..15ff1bcbe 100644 --- a/electronics_model/test_netlist.py +++ b/electronics_model/test_netlist.py @@ -24,8 +24,8 @@ class TestFakeSource(FootprintBlock): def __init__(self) -> None: super().__init__() - self.pos = self.Port(VoltageSource()) - self.neg = self.Port(VoltageSource()) + self.pos = self.Port(VoltageSource(), optional=True) + self.neg = self.Port(VoltageSource(), optional=True) def contents(self) -> None: super().contents() @@ -63,6 +63,13 @@ def contents(self) -> None: ) +class TestSinglePart(Block): + def contents(self) -> None: + super().contents() + + self.source = self.Block(TestFakeSource()) + + class TestBasicCircuit(Block): def contents(self) -> None: super().contents() @@ -182,6 +189,14 @@ def generate_net(design: Type[Block], refinements: Refinements = Refinements()): compiled.append_values(RefdesRefinementPass().run(compiled)) return NetlistTransform(compiled).run() + def test_single_netlist(self) -> None: + net = self.generate_net(TestSinglePart) + + # check that the top-level path element is never pruned, even when the design is one element + self.assertIn(NetBlock('Capacitor_SMD:C_0603_1608Metric', 'C1', '', '1uF', + ['source'], ['source'], + ['electronics_model.test_netlist.TestFakeSource']), net.blocks) + def test_basic_netlist(self) -> None: net = self.generate_net(TestBasicCircuit)