diff --git a/core/cva6.sv b/core/cva6.sv index a86caf81da..fd7ae31435 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -201,6 +201,7 @@ module cva6 CVA6Cfg.XFVec, CVA6Cfg.CvxifEn, CVA6Cfg.ZiCondExtEn, + CVA6Cfg.ZiCfiLPEn, CVA6Cfg.RVSCLIC, // Extended bit'(RVF), diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index b204e2dad8..8d8c0f4ee6 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -76,6 +76,8 @@ package config_pkg; bit CvxifEn; // Zicond RISC-V extension bit ZiCondExtEn; + // Control-Flow Integrity - Zicfilp extension + bit ZiCfiLPEn; // CLIC extension bit RVSCLIC; // Single precision FP RISC-V extension @@ -108,7 +110,7 @@ package config_pkg; bit RVU; // Address to jump when halt request logic [63:0] HaltAddress; - // Address to jump when exception + // Address to jump when exception logic [63:0] ExceptionAddress; // Return address stack depth int unsigned RASDepth; diff --git a/core/include/cv64a6_imafdch_sv39_wb_alsaqr_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_wb_alsaqr_config_pkg.sv index 858b376f6f..450bd3c0aa 100644 --- a/core/include/cv64a6_imafdch_sv39_wb_alsaqr_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_wb_alsaqr_config_pkg.sv @@ -27,6 +27,7 @@ package cva6_config_pkg; localparam CVA6ConfigVExtEn = 0; localparam CVA6ConfigHExtEn = 1; localparam CVA6ConfigZiCondExtEn = 1; + localparam CVA6ConfigZiCfiLPEn = 1; localparam CVA6ConfigSclicExtEn = 0; localparam CVA6ConfigAxiIdWidth = 4; @@ -102,6 +103,7 @@ package cva6_config_pkg; XFVec: bit'(CVA6ConfigFVecEn), CvxifEn: bit'(CVA6ConfigCvxifEn), ZiCondExtEn: bit'(CVA6ConfigZiCondExtEn), + ZiCfiLPEn: bit'(CVA6ConfigZiCfiLPEn), RVSCLIC: bit'(CVA6ConfigSclicExtEn), // Extended RVF: