forked from pulp-platform/ace
-
Notifications
You must be signed in to change notification settings - Fork 0
/
ace_ccu_top.sv
342 lines (305 loc) · 15.9 KB
/
ace_ccu_top.sv
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
// Copyright (c) 2014-2018 ETH Zurich, University of Bologna
// Copyright (c) 2022 PlanV GmbH
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// ace_ccu_top: Top level module for closely coupled cache coherency protocol
`include "ace/assign.svh"
`include "ace/typedef.svh"
module ace_ccu_top
import cf_math_pkg::idx_width;
#(
parameter ace_pkg::ccu_cfg_t Cfg = '0,
parameter bit ATOPs = 1'b1,
parameter type slv_aw_chan_t = logic,
parameter type mst_aw_chan_t = logic,
parameter type mst_stg_aw_chan_t = logic,
parameter type w_chan_t = logic,
parameter type slv_b_chan_t = logic,
parameter type mst_b_chan_t = logic,
parameter type mst_stg_b_chan_t = logic,
parameter type slv_ar_chan_t = logic,
parameter type mst_ar_chan_t = logic,
parameter type mst_stg_ar_chan_t = logic,
parameter type slv_r_chan_t = logic,
parameter type mst_r_chan_t = logic,
parameter type mst_stg_r_chan_t = logic,
parameter type slv_req_t = logic,
parameter type slv_resp_t = logic,
parameter type mst_req_t = logic,
parameter type mst_resp_t = logic,
parameter type mst_stg_req_t = logic,
parameter type mst_stg_resp_t = logic,
parameter type snoop_req_t = logic,
parameter type snoop_resp_t = logic
) (
input logic clk_i,
input logic rst_ni,
input logic test_i,
input slv_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i,
output slv_resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o,
output snoop_req_t [Cfg.NoSlvPorts-1:0] slv_snp_req_o,
input snoop_resp_t [Cfg.NoSlvPorts-1:0] slv_snp_resp_i,
output mst_req_t mst_ports_req_o,
input mst_resp_t mst_ports_resp_i
);
// signals from the ace_demuxes
slv_req_t [Cfg.NoSlvPorts-1:0] [1:0] slv_reqs; // one for non-shareable and one for shareable req
slv_resp_t [Cfg.NoSlvPorts-1:0] [1:0] slv_resps;
// signals into the ace_muxes
mst_stg_req_t [Cfg.NoSlvPorts:0] mst_reqs; // one extra port for CCU
mst_stg_resp_t [Cfg.NoSlvPorts:0] mst_resps;
// signals into the CCU
slv_req_t [Cfg.NoSlvPorts-1:0] ccu_reqs_i;
slv_resp_t [Cfg.NoSlvPorts-1:0] ccu_resps_o;
// signals from the CCU
mst_stg_req_t ccu_reqs_mux_o;
mst_stg_resp_t ccu_resps_mux_i;
mst_stg_req_t ccu_reqs_o;
mst_stg_resp_t ccu_resps_i;
// selection lines for mux and demuxes
logic [Cfg.NoSlvPorts-1:0] slv_aw_select, slv_ar_select;
for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_slv_port_demux
// routing of incoming request through transaction type
ace_trs_dec #(
.slv_ace_req_t ( slv_req_t )
) i_ace_trs_dec (
.slv_reqs_i ( slv_ports_req_i[i] ),
.snoop_aw_trs ( slv_aw_select[i] ),
.snoop_ar_trs ( slv_ar_select[i] )
);
// demux
axi_demux #(
.AxiIdWidth ( Cfg.AxiIdWidthSlvPorts ), // ID Width
.aw_chan_t ( slv_aw_chan_t ), // AW Channel Type
.w_chan_t ( w_chan_t ), // W Channel Type
.b_chan_t ( slv_b_chan_t ), // B Channel Type
.ar_chan_t ( slv_ar_chan_t ), // AR Channel Type
.r_chan_t ( slv_r_chan_t ), // R Channel Type
.req_t ( slv_req_t ),
.resp_t ( slv_resp_t ),
.NoMstPorts ( 2 ), // one for CCU module and one for mux
.MaxTrans ( Cfg.MaxSlvTrans ),
.AxiLookBits ( Cfg.AxiIdUsedSlvPorts ),
.UniqueIds ( Cfg.UniqueIds ),
//.FallThrough ( Cfg.FallThrough ),
.SpillAw ( Cfg.LatencyMode[9] ),
.SpillW ( Cfg.LatencyMode[8] ),
.SpillB ( Cfg.LatencyMode[7] ),
.SpillAr ( Cfg.LatencyMode[6] ),
.SpillR ( Cfg.LatencyMode[5] )
) i_axi_demux (
.clk_i, // Clock
.rst_ni, // Asynchronous reset active low
.test_i, // Testmode enable
.slv_req_i ( slv_ports_req_i[i] ),
.slv_aw_select_i ( slv_aw_select[i] ),
.slv_ar_select_i ( slv_ar_select[i] ),
.slv_resp_o ( slv_ports_resp_o[i] ),
.mst_reqs_o ( slv_reqs[i] ),
.mst_resps_i ( slv_resps[i] )
);
end
axi_mux #(
.SlvAxiIDWidth ( Cfg.AxiIdWidthSlvPorts+$clog2(Cfg.NoSlvPorts) ), // ID width of the slave ports
.slv_aw_chan_t ( mst_stg_aw_chan_t ), // AW Channel Type, slave ports
.mst_aw_chan_t ( mst_aw_chan_t ), // AW Channel Type, master port
.w_chan_t ( w_chan_t ), // W Channel Type, all ports
.slv_b_chan_t ( mst_stg_b_chan_t ), // B Channel Type, slave ports
.mst_b_chan_t ( mst_b_chan_t ), // B Channel Type, master port
.slv_ar_chan_t ( mst_stg_ar_chan_t ), // AR Channel Type, slave ports
.mst_ar_chan_t ( mst_ar_chan_t ), // AR Channel Type, master port
.slv_r_chan_t ( mst_stg_r_chan_t ), // R Channel Type, slave ports
.mst_r_chan_t ( mst_r_chan_t ), // R Channel Type, master port
.slv_req_t ( mst_stg_req_t ),
.slv_resp_t ( mst_stg_resp_t ),
.mst_req_t ( mst_req_t ),
.mst_resp_t ( mst_resp_t ),
.NoSlvPorts ( Cfg.NoSlvPorts + 1 ), // Number of Masters for the modules
.MaxWTrans ( Cfg.MaxMstTrans ),
.FallThrough ( Cfg.FallThrough ),
.SpillAw ( Cfg.LatencyMode[4] ),
.SpillW ( Cfg.LatencyMode[3] ),
.SpillB ( Cfg.LatencyMode[2] ),
.SpillAr ( Cfg.LatencyMode[1] ),
.SpillR ( Cfg.LatencyMode[0] )
) i_axi_mux (
.clk_i, // Clock
.rst_ni, // Asynchronous reset active low
.test_i, // Test Mode enable
.slv_reqs_i ( mst_reqs ),
.slv_resps_o ( mst_resps ),
.mst_req_o ( mst_ports_req_o ),
.mst_resp_i ( mst_ports_resp_i )
);
// connection reqs and resps for non-shareable tarnsactions with axi_mux
for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_non_shared_conn
`ACE_ASSIGN_REQ_STRUCT(mst_reqs[i], slv_reqs[i][0])
`ACE_ASSIGN_RESP_STRUCT(slv_resps[i][0], mst_resps[i])
end
// connection reqs and resps for shareable transactions with CCU
for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_shared_conn
`ACE_ASSIGN_REQ_STRUCT(ccu_reqs_i[i], slv_reqs[i][1])
`ACE_ASSIGN_RESP_STRUCT(slv_resps[i][1], ccu_resps_o[i])
end
axi_mux #(
.SlvAxiIDWidth ( Cfg.AxiIdWidthSlvPorts ), // ID width of the slave ports
.slv_aw_chan_t ( slv_aw_chan_t ), // AW Channel Type, slave ports
.mst_aw_chan_t ( mst_stg_aw_chan_t ), // AW Channel Type, master port
.w_chan_t ( w_chan_t ), // W Channel Type, all ports
.slv_b_chan_t ( slv_b_chan_t ), // B Channel Type, slave ports
.mst_b_chan_t ( mst_stg_b_chan_t ), // B Channel Type, master port
.slv_ar_chan_t ( slv_ar_chan_t ), // AR Channel Type, slave ports
.mst_ar_chan_t ( mst_stg_ar_chan_t ), // AR Channel Type, master port
.slv_r_chan_t ( slv_r_chan_t ), // R Channel Type, slave ports
.mst_r_chan_t ( mst_stg_r_chan_t ), // R Channel Type, master port
.slv_req_t ( slv_req_t ),
.slv_resp_t ( slv_resp_t ),
.mst_req_t ( mst_stg_req_t ),
.mst_resp_t ( mst_stg_resp_t ),
.NoSlvPorts ( Cfg.NoSlvPorts ), // Number of Masters for the modules
.MaxWTrans ( Cfg.MaxMstTrans ),
.FallThrough ( Cfg.FallThrough ),
.SpillAw ( Cfg.LatencyMode[4] ),
.SpillW ( Cfg.LatencyMode[3] ),
.SpillB ( Cfg.LatencyMode[2] ),
.SpillAr ( Cfg.LatencyMode[1] ),
.SpillR ( Cfg.LatencyMode[0] )
) i_ace_mux (
.clk_i, // Clock
.rst_ni, // Asynchronous reset active low
.test_i, // Test Mode enable
.slv_reqs_i ( ccu_reqs_i ),
.slv_resps_o ( ccu_resps_o ),
.mst_req_o ( ccu_reqs_mux_o ),
.mst_resp_i ( ccu_resps_mux_i )
);
ccu_fsm
#(
.NoMstPorts ( Cfg.NoSlvPorts ),
.mst_req_t ( mst_stg_req_t ),
.mst_resp_t ( mst_stg_resp_t ),
.snoop_req_t ( snoop_req_t ),
.snoop_resp_t ( snoop_resp_t )
) fsm (
.clk_i,
.rst_ni,
.ccu_req_i ( ccu_reqs_mux_o ),
.ccu_resp_o ( ccu_resps_mux_i ),
.ccu_req_o ( ccu_reqs_o ),
.ccu_resp_i ( ccu_resps_i ),
.s2m_req_o ( slv_snp_req_o ),
.m2s_resp_i ( slv_snp_resp_i )
);
// connect CCU reqs and resps to mux
`ACE_ASSIGN_REQ_STRUCT(mst_reqs[Cfg.NoSlvPorts], ccu_reqs_o)
`ACE_ASSIGN_RESP_STRUCT(ccu_resps_i, mst_resps[Cfg.NoSlvPorts])
endmodule
module ace_ccu_top_intf
import cf_math_pkg::idx_width;
#(
parameter int unsigned AXI_USER_WIDTH = 0,
parameter ace_pkg::ccu_cfg_t Cfg = '0,
parameter bit ATOPS = 1'b1
) (
input logic clk_i,
input logic rst_ni,
input logic test_i,
SNOOP_BUS.Slave snoop_ports [Cfg.NoSlvPorts-1:0],
ACE_BUS.Slave slv_ports [Cfg.NoSlvPorts-1:0],
AXI_BUS.Master mst_ports
);
localparam int unsigned AxiIdWidthMstPortsStage = Cfg.AxiIdWidthSlvPorts +$clog2(Cfg.NoSlvPorts);
localparam int unsigned AxiIdWidthMstPorts = AxiIdWidthMstPortsStage + $clog2(Cfg.NoSlvPorts+1);
typedef logic [AxiIdWidthMstPortsStage-1:0] id_mst_stg_t;
typedef logic [AxiIdWidthMstPorts -1:0] id_mst_t;
typedef logic [Cfg.AxiIdWidthSlvPorts -1:0] id_slv_t;
typedef logic [Cfg.AxiAddrWidth -1:0] addr_t;
typedef logic [Cfg.AxiDataWidth -1:0] data_t;
typedef logic [Cfg.AxiDataWidth/8 -1:0] strb_t;
typedef logic [AXI_USER_WIDTH -1:0] user_t;
// snoop channel conversion
`ACE_TYPEDEF_AW_CHAN_T(mst_ace_stg_aw_chan_t, addr_t, id_mst_stg_t, user_t)
`ACE_TYPEDEF_AW_CHAN_T(mst_ace_aw_chan_t, addr_t, id_mst_t, user_t)
`ACE_TYPEDEF_AW_CHAN_T(slv_ace_aw_chan_t, addr_t, id_slv_t, user_t)
`ACE_TYPEDEF_AR_CHAN_T(mst_ace_stg_ar_chan_t, addr_t, id_mst_stg_t, user_t)
`ACE_TYPEDEF_AR_CHAN_T(mst_ace_ar_chan_t, addr_t, id_mst_t, user_t)
`ACE_TYPEDEF_AR_CHAN_T(slv_ace_ar_chan_t, addr_t, id_slv_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(mst_stg_b_chan_t, id_mst_stg_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, id_mst_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, id_slv_t, user_t)
`ACE_TYPEDEF_R_CHAN_T(mst_ace_stg_r_chan_t, data_t, id_mst_stg_t, user_t)
`ACE_TYPEDEF_R_CHAN_T(mst_ace_r_chan_t, data_t, id_mst_t, user_t)
`ACE_TYPEDEF_R_CHAN_T(slv_ace_r_chan_t, data_t, id_slv_t, user_t)
`ACE_TYPEDEF_REQ_T(mst_ace_stg_req_t, mst_ace_stg_aw_chan_t, w_chan_t, mst_ace_stg_ar_chan_t)
`ACE_TYPEDEF_REQ_T(mst_ace_req_t, mst_ace_aw_chan_t, w_chan_t, mst_ace_ar_chan_t)
`ACE_TYPEDEF_REQ_T(slv_ace_req_t, slv_ace_aw_chan_t, w_chan_t, slv_ace_ar_chan_t)
`ACE_TYPEDEF_RESP_T(mst_ace_stg_resp_t, mst_stg_b_chan_t, mst_ace_stg_r_chan_t)
`ACE_TYPEDEF_RESP_T(mst_ace_resp_t, mst_b_chan_t, mst_ace_r_chan_t)
`ACE_TYPEDEF_RESP_T(slv_ace_resp_t, slv_b_chan_t, slv_ace_r_chan_t)
`SNOOP_TYPEDEF_AC_CHAN_T(snoop_ac_t, addr_t)
`SNOOP_TYPEDEF_CD_CHAN_T(snoop_cd_t, data_t)
`SNOOP_TYPEDEF_CR_CHAN_T(snoop_cr_t)
`SNOOP_TYPEDEF_REQ_T(snoop_req_t, snoop_ac_t)
`SNOOP_TYPEDEF_RESP_T(snoop_resp_t, snoop_cd_t, snoop_cr_t)
mst_ace_req_t mst_ace_reqs;
mst_ace_resp_t mst_ace_resps;
slv_ace_req_t [Cfg.NoSlvPorts-1:0] slv_ace_reqs;
slv_ace_resp_t [Cfg.NoSlvPorts-1:0] slv_ace_resps;
snoop_req_t [Cfg.NoSlvPorts-1:0] snoop_reqs;
snoop_resp_t [Cfg.NoSlvPorts-1:0] snoop_resps;
/// Assigning ACE request from CCU Mux to slave(RAM )
`AXI_ASSIGN_FROM_REQ(mst_ports, mst_ace_reqs)
/// Assigning AXI response from slave (RAM) to CCU mux which accepts only ACE type response
`ACE_ASSIGN_TO_RESP(mst_ace_resps, mst_ports)
for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_assign_slv
`ACE_ASSIGN_TO_REQ(slv_ace_reqs[i], slv_ports[i])
`ACE_ASSIGN_FROM_RESP(slv_ports[i], slv_ace_resps[i])
/// Assigning SNOOP request from CCU logic to master
`SNOOP_ASSIGN_FROM_REQ(snoop_ports[i], snoop_reqs[i])
/// Assigning SNOOP response from master to CCU logic
`SNOOP_ASSIGN_TO_RESP(snoop_resps[i], snoop_ports[i])
end
ace_ccu_top #(
.Cfg ( Cfg ),
.ATOPs ( ATOPS ),
.slv_aw_chan_t ( slv_ace_aw_chan_t ),
.mst_stg_aw_chan_t ( mst_ace_stg_aw_chan_t ),
.mst_aw_chan_t ( mst_ace_aw_chan_t ),
.w_chan_t ( w_chan_t ),
.slv_b_chan_t ( slv_b_chan_t ),
.mst_b_chan_t ( mst_b_chan_t ),
.mst_stg_b_chan_t ( mst_stg_b_chan_t ),
.slv_ar_chan_t ( slv_ace_ar_chan_t ),
.mst_ar_chan_t ( mst_ace_ar_chan_t ),
.mst_stg_ar_chan_t ( mst_ace_stg_ar_chan_t ),
.slv_r_chan_t ( slv_ace_r_chan_t ),
.mst_r_chan_t ( mst_ace_r_chan_t ),
.mst_stg_r_chan_t ( mst_ace_stg_r_chan_t ),
.slv_req_t ( slv_ace_req_t ),
.slv_resp_t ( slv_ace_resp_t ),
.mst_req_t ( mst_ace_req_t ),
.mst_resp_t ( mst_ace_resp_t ),
.mst_stg_req_t ( mst_ace_stg_req_t ),
.mst_stg_resp_t ( mst_ace_stg_resp_t ),
.snoop_req_t ( snoop_req_t ),
.snoop_resp_t ( snoop_resp_t )
) i_ccu_top (
.clk_i,
.rst_ni,
.test_i,
.slv_ports_req_i ( slv_ace_reqs ),
.slv_ports_resp_o ( slv_ace_resps ),
.slv_snp_req_o ( snoop_reqs ),
.slv_snp_resp_i ( snoop_resps ),
.mst_ports_req_o ( mst_ace_reqs ),
.mst_ports_resp_i ( mst_ace_resps )
);
endmodule