diff --git a/README.md b/README.md index eff5b470..434c13d3 100644 --- a/README.md +++ b/README.md @@ -3,7 +3,7 @@ ## Server Base System Architecture -**Server Base System Architecture** (SBSA) specification specifies a hardware system architecture based on the ARM 64-bit architecture. Server system software such as operating systems, hypervisors, and firmware rely on this. It addresses processing element features and key aspects of system architecture. +**Server Base System Architecture** (SBSA) specification specifies a hardware system architecture based on the Arm 64-bit architecture. Server system software such as operating systems, hypervisors, and firmware rely on this. It addresses processing element features and key aspects of system architecture. For more information, download the [SBSA specification](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0029b/index.html) @@ -11,16 +11,17 @@ For more information, download the [SBSA specification](http://infocenter.arm.co ## SBSA - Architecture Compliance Suite SBSA **Architecture Compliance Suite** (ACS) is a collection of self-checking, portable C-based tests. -This suite includes a set of examples of the invariant behaviours that are provided by the [SBSA](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0029b/index.html) specification, so that implementers can verify if these behaviours have been interpreted correctly. +This suite includes a set of examples of the invariant behaviors that are provided by the [SBSA](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0029b/index.html) specification, so that implementers can verify if these behaviours have been interpreted correctly. Most of the tests are executed from UEFI Shell by executing the SBSA UEFI shell application. A few tests are executed by running the SBSA ACS Linux application which in turn depends on the SBSA ACS Linux kernel module. ## Release details - - Code Quality: REL v2.3 + - Code Quality: REL v2.4 - The tests are written for version 5.0 of the SBSA specification. + - PCIe RCiEP tests for Appendix E of SBSA 6.0 specification are also included. - The compliance suite is not a substitute for design verification. - - To review the SBSA ACS logs, ARM licensees can contact ARM directly through their partner managers. + - To review the SBSA ACS logs, Arm licensees can contact Arm directly through their partner managers. - To know about the gaps in the test coverage, see [Testcase checklist](docs/testcase-checklist.md). - Refer to changelog.txt to know about the changes. @@ -49,7 +50,7 @@ Prebuilt images for each release are available in the prebuilt_images folder of ### Prerequisites Before starting the ACS build, ensure that the following requirements are met. -- Any mainstream Linux based OS distribution. +- Any mainstream Linux based OS distribution running on a x86 or aarch64 machine. - git clone the UDK2018 branch of [EDK2 tree](https://github.com/tianocore/edk2). - Install GCC 5.3 or later toolchain for Linux from [here](https://releases.linaro.org/components/toolchain/binaries/). - Install the build prerequisite packages to build EDK2. @@ -66,7 +67,7 @@ To start the ACS build, perform the following steps: ### Linux build environment If the build environment is Linux, perform the following steps: -1. export GCC49_AARCH64_PREFIX= GCC5.3 toolchain path pointing to /bin/aarch64-linux-gnu- +1. export GCC49_AARCH64_PREFIX= GCC5.3 toolchain path pointing to /bin/aarch64-linux-gnu- in case of x86 machine. For aarch64 build it should point to /usr/bin/ 2. source edksetup.sh 3. make -C BaseTools/Source/C 4. source AppPkg/Applications/sbsa-acs/tools/scripts/avsbuild.sh @@ -80,17 +81,18 @@ If the build environment is Windows, perform the following steps: build -a AARCH64 -t GCC49 -p ShellPkg/ShellPkg.dsc -m AppPkg/Applications/sbsa-acs/uefi_app/SbsaAvs.inf +**Note:** To build the ACS with NIST Statistical Test Suite, see [SBSA_NIST_User_Guide](docs/Arm_SBSA_NIST_User_Guide.md) + ### Build output -The EFI executable file is generated at -edk2_path /Build/Shell/DEBUG_GCC49/AARCH64/Sbsa.efi +The EFI executable file is generated at /Build/Shell/DEBUG_GCC49/AARCH64/Sbsa.efi ## Test suite execution The execution of the compliance suite varies depending on the test environment. These steps assume that the test suite is invoked through the ACS UEFI shell application. -For details about the SBSA ACS UEFI Shell application, see [SBSA ACS USER Guide](docs/SBSA_ACS_User_Guide.pdf) +For details about the SBSA ACS UEFI Shell application, see [SBSA ACS USER Guide](docs/Arm_SBSA_Architecture_Compliance_User_Guide.pdf) ### Post-Silicon @@ -102,7 +104,7 @@ On a system where a USB port is available and functional, perform the following 4. To determine the file system number of the plugged in USB drive, execute 'map -r' command. 5. Type 'fsx' where 'x' is replaced by the number determined in step 4. 6. To start the compliance tests, run the executable Sbsa.efi with the appropriate parameters. - For details on the parameters, refer to [SBSA ACS User Guide](docs/SBSA_ACS_User_Guide.pdf) + For details on the parameters, refer to [SBSA ACS User Guide](docs/Arm_SBSA_Architecture_Compliance_User_Guide.pdf) 7. Copy the UART console output to a log file for analysis and certification. @@ -119,7 +121,7 @@ On an emulation environment with secondary storage, perform the following steps: 4. To determine the file system number of the secondary storage, execute 'map -r' command. 5. Type 'fsx' where 'x' is replaced by the number determined in step 4. 6. To start the compliance tests, run the executable Sbsa.efi with the appropriate parameters. - For details on the parameters, see [SBSA ACS User Guide](docs/SBSA_ACS_User_Guide.pdf) + For details on the parameters, see [SBSA ACS User Guide](docs/Arm_SBSA_Architecture_Compliance_User_Guide.pdf) 7. Copy the UART console output to a log file for analysis and certification. @@ -130,12 +132,17 @@ On an Emulation platform where secondary storage is not available, perform the f 1. Add the path to 'Sbsa.efi' file in the UEFI FD file. 2. Build UEFI image including the UEFI Shell. 3. Boot the system to UEFI shell. -4. Run the executable 'Sbsa.efi' to start the compliance tests. For details about the parameters, see [SBSA ACS User Guide](docs/SBSA_ACS_User_Guide.pdf). +4. Run the executable 'Sbsa.efi' to start the compliance tests. For details about the parameters, + see [SBSA ACS User Guide](docs/Arm_SBSA_Architecture_Compliance_User_Guide.pdf). 5. Copy the UART console output to a log file for analysis and certification. ## Linux OS-based tests -Certain PCIe and IOMMU tests require Linux operating system with kernel version 4.10 or above. The procedure to build and run these tests is described in [SBSA ACS User Guide](docs/SBSA_ACS_User_Guide.pdf). +Certain PCIe and IOMMU tests require Linux operating system with kernel version 4.10 or above. +The procedure to build and run these tests is described in [SBSA ACS User Guide](docs/Arm_SBSA_Architecture_Compliance_User_Guide.pdf). + +## Security implication +Arm Enterprise ACS test suite may run at higher privilege level. An attacker may utilize these tests as a means to elevate privilege which can potentially reveal the platform security assets. To prevent the leakage of secure information, it is strongly recommended that the ACS test suite is run only on development platforms. If it is run on production systems, the system should be scrubbed after running the test suite. ## License @@ -146,5 +153,9 @@ SBSA ACS is distributed under Apache v2.0 License. - For feedback, use the GitHub Issue Tracker that is associated with this repository. - For support, please send an email to "support-enterprise-acs@arm.com" with details. - - ARM licensees can contact ARM directly through their partner managers. - - ARM welcomes code contributions through GitHub pull requests. See GitHub documentation on how to raise pull requests. + - Arm licensees may contact Arm directly through their partner managers. + - Arm welcomes code contributions through GitHub pull requests. See GitHub documentation on how to raise pull requests. + +-------------- + +*Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.* diff --git a/docs/Arm_SBSA_Architecture_Compliance_Test_Scenario.pdf b/docs/Arm_SBSA_Architecture_Compliance_Test_Scenario.pdf index d5d0def3..a21dfaee 100755 Binary files a/docs/Arm_SBSA_Architecture_Compliance_Test_Scenario.pdf and b/docs/Arm_SBSA_Architecture_Compliance_Test_Scenario.pdf differ diff --git a/docs/Arm_SBSA_Architecture_Compliance_User_Guide.pdf b/docs/Arm_SBSA_Architecture_Compliance_User_Guide.pdf index 62fd3e8c..46839381 100755 Binary files a/docs/Arm_SBSA_Architecture_Compliance_User_Guide.pdf and b/docs/Arm_SBSA_Architecture_Compliance_User_Guide.pdf differ diff --git a/docs/Arm_SBSA_Architecture_Compliance_Validation_Methodology.pdf b/docs/Arm_SBSA_Architecture_Compliance_Validation_Methodology.pdf index 04a035d0..7adc91be 100755 Binary files a/docs/Arm_SBSA_Architecture_Compliance_Validation_Methodology.pdf and b/docs/Arm_SBSA_Architecture_Compliance_Validation_Methodology.pdf differ diff --git a/docs/Arm_SBSA_NIST_User_Guide.md b/docs/Arm_SBSA_NIST_User_Guide.md new file mode 100644 index 00000000..da285eae --- /dev/null +++ b/docs/Arm_SBSA_NIST_User_Guide.md @@ -0,0 +1,177 @@ +# National Institute of Standards and Technology: Statistical Test Suite + +**Need for Randomness?** + +Randomness relates to many areas of computer science, in particular with cryptography. Well-designed cryptographic primitives like hash functions, stream ciphers should produce pseudorandom data. The outputs of such generators may be used in many cryptographic applications like the generation of key material. Generators suitable for use in cryptographic applications need to meet stronger requirements than for other applications. In particular, their outputs must be unpredictable in the absence of knowledge of the inputs. + +**Statistical Test Suites** + +Randomness testing plays a fundamental role in cryptography. Randomness is tested using test suites consisting of many tests of randomness each focusing on different feature. These tests can be used as first steps in determining whether or not a generator is suitable for a particular cryptographic application. + +**NIST with SBSA** + +There are five well-known statistical test suites -- NIST STS, Diehard, TestU01, ENT and CryptX. Only the first three test suites are commonly used for the randomness analysis since CryptX is a commercial software and ENT provides only basic randomness testing. Since NIST STS has a special position by being published as an official document, it is often used in the preparation of formal certifications or approvals. + +**Building NIST STS with SBSA ACS** + +To build NIST statistical test suite with SBSA ACS, NIST STS 2.1.2 package is required. This package is obtained from and is downloaded automatically as part of the build process. + +This is an updated version of [NIST Statistical Test Suite (STS)](http://csrc.nist.gov/groups/ST/toolkit/rng/documentation_software.html) tool for randomness testing. The reason for the update is, the original source code provided with NIST does not compile cleanly in UEFI because it does not provide erf() and erfc() functions in the standard math library and (harcoded the inputs -- needs to be rephrased). Implementation of these functions has been added as part of SBSA val and a patch file is created. + +**Tool Requirement** + +Current release require the below tool: + +1. unzip + +**Build steps** + +To start the ACS build with NIST STS, perform the following steps: + +1. Add the following to the [LibraryClasses.common] section in ShellPkg/ShellPkg.dsc +``` + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + !ifdef $(ENABLE_NIST) + SbsaNistLib|AppPkg/Applications/sbsa-acs/test_pool/nist_sts/SbsaNistLib.inf + SbsaValNistLib|AppPkg/Applications/sbsa-acs/val/SbsaValNistLib.inf + SbsaPalNistLib|AppPkg/Applications/sbsa-acs/platform/pal_uefi/SbsaPalNistLib.inf + !else + SbsaValLib|AppPkg/Applications/sbsa-acs/val/SbsaValLib.inf + SbsaPalLib|AppPkg/Applications/sbsa-acs/platform/pal_uefi/SbsaPalLib.inf + !endif +``` +2. Add the following in the [components] section of ShellPkg/ShellPkg.dsc +``` + !ifdef $(ENABLE_NIST) + AppPkg/Applications/sbsa-acs/uefi_app/SbsaAvsNist.inf + !else + AppPkg/Applications/sbsa-acs/uefi_app/SbsaAvs.inf + !endif +``` +3. Modify CC Flags in the [BuildOptions] section of ShellPkg/ShellPkg.dsc +``` + !ifdef $(ENABLE_NIST) + *_*_*_CC_FLAGS = -DENABLE_NIST + !else + *_*_*_CC_FLAGS = + !endif + + !include StdLib/StdLib.inc +``` +4. Modify the following in the StdLib/LibC/Main/Main.c +``` + -extern int main( int, char**); + +extern int ShellAppMainsbsa( int, char**); +``` +5. Modify the following in ShellAppMain() of StdLib/LibC/Main/Main.c +``` + -ExitVal = (INTN)main( (int)Argc, gMD->NArgV); + +ExitVal = (INTN)ShellAppMainsbsa( (int)Argc, gMD->NArgV); +``` +6. Comment the map[] variable in StdLib/LibC/Main/Arm/flt_rounds.c to avoid -werror=unused-variable +``` + +#if 0 + static const int map[] = { + 1, /* round to nearest */ + 2, /* round to positive infinity */ + 3, /* round to negative infinity */ + 0 /* round to zero */ + }; + +#endif +``` + + +To build the SBSA test suite with NIST STS, execute the following commands: +***Linux build environment*** +``` +source AppPkg/Applications/sbsa-acs/tools/scripts/avsbuild.sh NIST +``` + +***Windows build environment*** +``` +build -a AARCH64 -t GCC49 -p ShellPkg/ShellPkg.dsc -m AppPkg/Applications/sbsa-acs/uefi_app/SbsaAvs.inf -D ENABLE_NIST +``` + +**Directory structure of SBSA ACS** + +The following figure shows the source code directory for SBSA ACS + +    sbsa
+    ├── docs
+    ├── linux_app
+    ├── patches
+    │   └── nist_sbsa_sts.diff ────────> Patch to compile NIST STS with SBSA ACS
+    │
+    ├── platform
+    │   ├── pal_baremetal
+    │   ├── pal_linux
+    │   ├── pal_uefi
+    │   └── secure_sw
+    │       └── arm-tf
+    │
+    ├── test_pool
+    │   ├── exerciser
+    │   ├── gic
+    │   ├── io_virt
+    │   ├── pcie
+    │   ├── pe
+    │   ├── peripherals
+    │   ├── power_wakeup
+    │   ├── secure
+    │   ├── timer_wd
+    │   └── nist_sts
+    │       ├── test_n001.c     ────────>  NIST entry point to STS
+    │       └── sts-2.1.2
+    │           └── sts-2.1.2   ────────>  NIST STS package
+    │
+    ├── tools
+    │   └── scripts
+    ├── uefi_app
+    └── val
+        ├── include
+        └── src
+            └── avs_nist.c      ────────>  erf and erfc() implementations
+ +**Running NIST STS** + +Run the UEFI Shell application with the "-nist" as an argument argument + + uefi shell> sbsa.efi -nist + +**Interpreting the results** + +Final analysis report is generated when statistical testing is complete. The report contains a summary of empirical results which is displayed on the console. A test is unsuccessful when P-value < 0.01 and then the sequence under test should be considered as non-random. Example result as below + + ------------------------------------------------------------------------------ + RESULTS FOR THE UNIFORMITY OF P-VALUES AND THE PROPORTION OF PASSING SEQUENCES + ------------------------------------------------------------------------------ + ------------------------------------------------------------------------------ + C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 P-VALUE PROPORTION STATISTICAL TEST + ------------------------------------------------------------------------------ + 4 1 1 2 1 1 0 0 0 0 0.122325 10/10 OverlappingTemplate + 10 0 0 0 0 0 0 0 0 0 0.000000 * 0/10 * Universal + 7 2 1 0 0 0 0 0 0 0 0.000001 * 8/10 ApproximateEntropy + 3 4 1 0 2 0 0 0 0 0 0.017912 9/10 Serial + 4 0 1 0 2 1 0 1 1 0 0.122325 10/10 Serial + 1 1 1 1 0 2 0 3 0 1 0.534146 10/10 LinearComplexity + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + The minimum pass rate for each statistical test with the exception of the + random excursion (variant) test is approximately = 8 for a + sample size = 10 binary sequences. + + The minimum pass rate for the random excursion (variant) test is undefined. + + For further guidelines construct a probability table using the MAPLE program + provided in the addendum section of the documentation. + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + +For more details on NIST STS, see: + +**Note**: For SBSA level 6 compliance, passing the NIST statistical test suite is not mandatory. + +-------------- + +*Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.* diff --git a/docs/testcase-checklist.md b/docs/testcase-checklist.md index 410603af..dfc99311 100644 --- a/docs/testcase-checklist.md +++ b/docs/testcase-checklist.md @@ -1,137 +1,185 @@ -# SBSA ACS Testcase checklist - -## Test Number mapped to SBSA specification section - - - Also, indicates the test coverage. - -| Test Number | Component | Level | Test assertion | Section | Checked by ACS Now | Test Environment | -|----------------|----------------------------------|-------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-----------------|--------------------|----------------------------| -| 1 | PE | L0 | Number must be < 8 | 4.1.1 | yes | UEFI App | -| 2 | PE | L0+ | PE(s) must implement SIMD extensions | 4.1.1 | yes | UEFI App | -| 3 | PE | L0+ | PE(s) shall implement 16 bit ASID support | 4.1.1 | yes | UEFI App | -| 4 | PE | L0+ | PE(s) shall support 4KB and 64KB at stage 1 and 2 | 4.1.1 | yes | UEFI App | -| 5 | PE | L0+ | cache architecture type VIPT or PIPT | 4.1.1 | yes | UEFI App | -| 6 | PE | L0+ | All PE(s) are coherent in the same same inner sharable domain | 4.1.1 | yes | UEFI App | -| 7 | PE | L0+ | PE(s) where export restrictions allow should implement cryptography extensions | 4.1.1 | yes | UEFI App | -| 8 | PE | L0+ | PE(s) shall implement LE support | 4.1.1 | yes | UEFI App | -| 9 | PE | L0+ | PE(s) shall implement EL2 | 4.1.1 | yes | UEFI App | -| 10 | PE | L0+ | PE(s) shall implement AArch64 at all levels | 4.1.1 | yes | UEFI App | -| 11 | PE | L1- | The PMU overflow signal for each PE must be wired as a unique SPI or PPI with no intervening logic | 4.1.1 | yes | UEFI App | -| 11 | PE | L2+ | The PMU overflow signal from each PE must be wired to a unique PPI interrupt with no intervening logic. PPI must be 23 | 4.3.1 | yes | UEFI App | -| 12 | PE | L0 | Each PE will implement a minimal of four programable PMU counters | 4.1.1 | yes | UEFI App | -| 12 | PE | L1+ | Each PE must implement a minimum of six programmable PMU counters | 4.2.1 | yes | UEFI App | -| 13 | PE | L0+ | Each PE will implement a minimal of four synchronous watchpoints | 4.1.1 | yes | UEFI App | -| 14 | PE | L0 | Each PE implements a minimum of four breakpoints, two of which must be able to match virtual address, contextID or VMID | 4.1.1 | yes | UEFI App | -| 14 | PE | L1+ | Each PE must implement a minimum of six breakpoints, two of which must be able to match virtual address, contextID or VMID | 4.2.1 | yes | UEFI App | -| 15 | PE | L0+ | All PE(s) are architecturally symetric (allowed exceptions in Appendix C) | 4.1.1 | yes | UEFI App | -| 16 | PE | L3+ | Each PE implements EL3 Exception Level | 4.4.1 | yes | UEFI App | -| 17 | PE | L3+ | Each PE implements CRC32 instructions | 4.4.1 | yes | UEFI App | -| 18 | PE | L2+ | PMBIRQ will be wired as PPI 21 | 4.3.2.2 | yes | UEFI App | -| 19 | PE | L4+ | All PEs must implement the RAS extension introduced in ARMv8.2 | 4.3.1 | yes | UEFI App | -| 20 | PE | L4+ | All PEs must implement support for 16-bit VMD | 4.3.1 | yes | UEFI App | -| 21 | PE | L4+ | All PEs must implement virtual host extensions | 4.3.1 | yes | UEFI App | -| 22 | PE | L5+ | All PEs must provide support for stage-2 control of memory types and cacheability, as introduced by ARMv8.4 extensions | 4.4.1 | yes | UEFI App | -| 23 | PE | L5+ | All PEs must implement enhanced nested virtualization | 4.4.1 | yes | UEFI App | -| 24 | PE | L5+ | All PEs must support changing of page table mapping size using level1 and level2 solution proposed in the ARMv8.4 extension. Level2 is recommended | 4.4.1 | yes | UEFI App | -| 25 | PE | L4+ | If PEs implement ARMv8.3 pointer signing, the PEs must provide the standard algorithm defined by the ARM architecture | 4.4.1 | yes | UEFI App | -| 26 | PE | L5+ | All PEs must implement the Activity Monitors Extension | 4.4.1 | yes | UEFI App | -| 27 | PE | L5+ | Where export control allows, all PEs must implement cryptography support for SHA3 and SHA512 | 4.4.1 | yes | UEFI App | -| 28 | PE | L3+ | Where PEs implement the scalar vector extension, the vector length maximum must be at least 256 bits | 4.1.1 | yes | UEFI App | -| 101 | GICv3 | L2+ | Interrupt controller shall conform to GICv3 specification | 4.3.2 | yes | UEFI App | -| 102 | GICv3 | L2+ | If the base server system includes PCI Express then the GICv3 interrupt controller shall implement ITS and LPI | 4.3.2 | yes | UEFI App | -| 103 | GIC | L3+ | The GICv3 interrupt controller shall support two Security states | 4.4.4 | yes | UEFI App | -| 104 | GICv2/3 | L2+ | GIC maintenance interrupt shall be wired as PPI 25 | 4.3.2.4 | yes | UEFI App | -| 201 | System counter and generic timer | L0+ | Must run between 10Mhz and 400Mhz | 4.1.5 | yes | UEFI App | -| 202 | System counter and generic timer | L1- | The local PE timer when expiring must generate a PPI when EL1 physical timer expires | 4.1.5 | yes | UEFI App | -| 202 | System counter and generic timer | L2+ | The local PE timer when expiring must generate a PPI when EL1 physical timer expires, and PPI must be 30 | 4.3.2.1 | yes | UEFI App | -| 203 | System counter and generic timer | L1- | The local PE timer when expiring must generate a PPI when the virtual timer expires | 4.1.5 | yes | UEFI App | -| 203 | System counter and generic timer | L2+ | The local PE timer when expiring must generate a PPI when the virtual timer expires, and PPI must be 27 | 4.3.2.1 | yes | UEFI App | -| 204 | System counter and generic timer | L1- | The local PE timer when expiring must generate a PPI when EL2 physical timer expires | 4.1.5 | yes | UEFI App | -| 204 | System counter and generic timer | L2+ | The local PE timer when expiring must generate a PPI when EL2 physical timer expires, and PPI must be 26 | 4.3.2.1 | yes | UEFI App | -| 205 | System counter and generic timer | L1- | For systems where PE are 8.1 or greater local PE timer when expiring must generate a PPI when EL2 virtual timer expires | 4.1.5 | yes | UEFI App | -| 205 | System counter and generic timer | L2+ | For systems where PE are 8.1 or greater local PE timer when expiring must generate a PPI when EL2 virtual timer expires, and PPI must be 28 | 4.3.2.1 | yes | UEFI App | -| 206 | System counter and generic timer | L1+ | In systems that implement EL3, the memory mapped timer (the CNTBaseN frame and associated CNTCTLBase frame) must be mapped into the Non-secure address space | 4.2.3. | yes | UEFI App | -| 206 | System counter and generic timer | L3+ | If the system includes a system wakeup timer, this memory-mapped timer must be mapped on to Non-secure address space | 4.4.6 | yes | UEFI App | -| 207 | System counter and generic timer | L1+ | Unless all local PE timers are Always ON, a system timer based on architecture memory mapped generic itmer view shall generate an SPI | 4.2.3 | yes | UEFI App | -| 208 | System counter and generic timer | L0 | A system specific system timer shall generate an SPI | 4.1.7 | yes | UEFI App | -| 301 | Watchdog | L1+ | system implements a Generic Watchdog as specified in APPENDIX A: Generic Watchdog. | | yes | UEFI App | -| 301 | Watchdog | L3+ | The watchdog required by level 2 must have both its register frames mapped on to Non-secure address space; this is referred to as the Non-secure watchdog | 4.4.7 | yes | UEFI App | -| 302 | Watchdog | L1- | Watchdog Signal 0 is routed as an SPI to the GIC and usable as a EL2 interrupt | 4.2.4 | yes | UEFI App | -| 302 | Watchdog | L2+ | Watchdog Signal 0 is routed as an SPIor LPI to the GIC and usable as a EL2 interrupt | 4.3.8 | yes | UEFI App | -| 401 | PCIe | L1+ | Systems must map memory space to PCI Express configuration space, using the PCI Express Enhanced Configuration Access Mechanism (ECAM). Tests should be robust to ARI being implemented | 8.1 | yes | Linux driver | -| 402 | PCIe | L1+ | The base address of each ECAM region is discoverable from system firmware data | 8.1 | yes | Linux driver | -| 403, 801 | PCIe | L1+ | PEs are able to access the ECAM region | 8.1 | yes | Linux driver | -| 404, 802 | PCIe | L1+ | All systems must support mapping PCI Express memory space as either device memory or non-cacheable memory | 8.2 | yes | Linux driver | -| 404, 802 | PCIe | L1+ | When PCI Express memory space is mapped as normal memory, the system must support unaligned accesses to that region. | 8.2 | yes | Linux driver | -| 405 | PCIe | L3+ | In systems that are compatible with level 3 or above of the SBSA, the addresses sent by PCI express devices must be presented to the memory system or SMMU unmodified | 8.3 | yes | Linux driver | -| 405 | PCIe | L0+ | In a system where the PCI express does not use an SMMU, the PCI express devices have the same view of physical memory as the PEs | 8.3 | yes | Linux driver | -| 405, 803 | PCIe | L0+ | PCIe I/O Coherency Scenarios without System MMU are covered | 8.7.1 | yes | Linux driver | -| 405 | PCIe | L1+ | PCIe I/O Coherency Scenarios with System MMU are covered | 8.7.2 | yes | Linux driver | -| 406 | PCIe | L0+ | In a system with a SMMU for PCI express there are no transformations to addresses being sent by PCI express devices before they are presented as an input address to the SMMU. | 8.3 | yes | Linux driver | -| 406 | PCIe | L3+ | the addresses sent by PCI express devices must be presented to the memory system or SMMU unmodified | 4.4.8 | yes | Linux driver | -| 407 | PCIe | L1+ | Support for Message Signaled Interrupts (MSI/MSI-X) is required for PCI Express devices. MSI and MSI-X are edge-triggered interrupts that are delivered as a memory write transaction | 8.4 | yes | Linux driver | -| 408, 804 | PCIe | L1+ | each unique MSI(-X) shall trigger an interrupt with a unique ID and the MSI(-X) shall target GIC registers requiring no hardware specific software to service the interrupt | 8.4 | Yes | Linux driver | -| | PCIe | L1+ | Add GICv2/v3 support details | 8.4.1/2 | No | Linux driver | -| 409 | GICv3 | L2+ | All MSIs and MSI-x are mapped to LPI | 4.3.2 | yes | Linux driver | -| 410, 805 | PCIe | L3+ | If the system supports PCIe PASID, then at least 16 bits of PASID must be supported | 8.11 | yes | Linux driver | -| 411 | PCIe | L0+ | The PCI Express root complex is in the same Inner Shareable domain as the PEs | 8.7 | yes | Linux driver | -| 412, 806 | PCIe | L1+ | Each of the 4 legacy interrupt lines must be allocated a unique SPI ID and is programmed as level sensitive | 8.5 | yes | Linux driver | -| 413 | MemoryMap | L3+ | All Non-secure on-chip masters in a base server system that are expected to be under the control of the OS or hypervisor must be capable of addressing all of the NS address space. If the master goes through a SMMU then it must be capable of addressing all of the NS address space when the SMMU is off. | 4.4.3 | yes | Linux driver | -| 413 | MemoryMap / PCIe | L3+ | Non-secure off-chip devices that cannot directly address all of the Non-secure address space must be placed behind a stage 1 System MMU compatible with the ARM SMMUv2 or SMMUv3 specification. that has an output address size large enough to address all of the Non-secure address space. | 4.4.3 | yes | Linux driver | -| 414 | Peripheral Subsystems | L3+ | Memory Attributes of DMA traffic are one of (1) Inner WB, Outer WB, Inner Shareable (2) Inner/Outer Non-Cacheable (3) Device TypeIO Coherent DMA is as per (1) Inner/Outer WB, Inner Shareable | 4.4.8 | yes | Linux driver | -| 415, 807 | PCIe | L0+ | PCI Express transactions not marked as No_snoop accessing memory that the PE translation tables attribute as cacheable and shared are I/O Coherent with the PEs. | 8.7 | yes | Linux driver | -| 416 | PCIe | L4+ | For Non-prefetchable (NP) memory, type-1 headers only support 32bit address, systems complaint with SBSA level 4 or above must support 32bit programming of NP BARs on such endpoints | D.2 | yes | Linux driver | -| 504 | Watchdog | L1+ | Watchdog Signal 0 should be able to wakeup at least one PE from various low power states. Based off power states supported - this should be covered for 1 of N condition with some PEs in low power and from the lowest power stated where the Watchdog is ON. | 4.2.6 | yes | UEFI App | -| 504 | System counter and generic timer | L1+ | Unless all local PE timers are Always ON, a system timer based on architecture memory mapped generic timer view shall generate an SPI that wake the platform from states with semantics B,C,D,E,F,H,I | 4.2.3 | yes | UEFI App | -| 505 | System counter and generic timer | L0 | A system specific system timer shall generate an SPI that wake the platform from states with semantics B,C,D,E,F,H,I | 4.1.7 | no | UEFI App | -| 505 | Wakeup semantics | L0+ | Whilst in state F a PE must not wake upon receipt of an SGI, PPI or SPI that directly targets the PE | 4.3.4/7 | yes | UEFI App | -| 601 | Peripheral Subsystems | L0+ | If the system has a USB2.0 host controller peripheral it must conform to EHCI v1.1 or later - Peripheral subsystems which do not conform to the above are permitted, provided that they are not required to boot and install an OS | 4.1.8 | yes | UEFI App | -| 601 | Peripheral Subsystems | L0+ | If the system has a USB3.0 host controller peripheral it must conform to XHCI v1.0 or later - Peripheral subsystems which do not conform to the above are permitted, provided that they are not required to boot and install an OS | 4.1.8 | yes | UEFI App | -| 602 | Peripheral Subsystems | L0+ | If the system has a SATA host controller peripheral it must conform to AHCI v1.3 or later - Peripheral subsystems which do not conform to the above are permitted, provided that they are not required to boot and install an OS | 4.1.8 | yes | UEFI App | -| 603 | Peripheral Subsystems | L1+ | For the purpose of system development and bring up, the base server system shall include a Generic UART. The Generic UART is specified in Appendix B. The UARTINTR interrupt output is connected to the GIC as an SPI. | 4.2.7 | yes | UEFI App | -| 603 | Peripheral Subsystems | L3+ | Check that that Generic UART is mapped to Non-Secure address space | 4.4.8 | yes | UEFI App | -| 604 | Peripheral Subsystems | L2+ | UARTINTR of the generic UART shall be connected as SPI or LPI | 4.3.9 | yes | UEFI App | -| 605 | MemoryMap | L0+ | Accesses to part of the memory map that is unpopulated should not deadlock and cause a precise data abort, SEI or SPU interrupt delivered to the GIC | 4.1.3 | yes | UEFI App | -| 605 | MemoryMap | L2+ | Where a memory access is to an unpopulated part of the addressable memory space, accesses must be terminated in a manner that is presented to the PE as either a precise Data Abort or that causes a system error interrupt or an SPI or LPI interrupt to be delivered to the GIC. | 4.3.3 | yes | UEFI App | -| 606 | Peripheral Subsystems | L3 FW | Some memory is mapped in secure address space. The memory shall not be aliased in Non-secure address space | 4.5.1 | yes | UEFI App | -| 701 | IO Virtualisation | L0+ | SMMU if present must spport a 64KB granule, For L1- this would be an SMMUv1 for L2 SMMUv2, and | 4.1.4 | yes | UEFI App | -| 702 | SMMU | L3+ | All the System MMUs in the system must the compliant with the same architecture version | 4.4.5 | yes | UEFI App | -| 703 | SMMU | L3+ | If SMMUv3 is in use, The integration of the System MMUs is compliant with the specification in APPENDIX H: SMMUv3 Integration | 4.4.5Appendix H | yes | UEFI App | -| 703 | IO Virtualisation | L2+ | Stage 2 System MMU functionality must be provided by a System MMU compatible with the ARM SMMUv2 spec | 4.3.5 | yes | UEFI App | -| 703 | SMMU | L3+ | Stage 2 System MMU functionality must be provided by a System MMU compatible with the ARM SMMUv2 or SMMUv3 specification | 4.4.5 | yes | UEFI App | -| 703 | PCIe | L1+ | Hardware support for I/O Virtualization is optional, but if required shall use a System MMU compliant with the ARM System MMU specification | 8.6 | yes | UEFI App | -| 703 | IO Virtualisation | L0+ | Policing is required at stage 2 | 4.1.4 | yes | UEFI App | -| 703 | SMMU | L4+ | Stage 1 and 2 SMMU functionality must be provided by a SMMU compatible with ARM SMMUv3 or higher | 4.3.2 | yes | UEFI App | -| 703 | SMMU | L5+ | SMMU implementations must be complaint with the ARM SMMUv3.2 architecture revision or higher | 4.3.2 | yes | UEFI App | -| 704 | SMMU | L3+ | The SMMUv3 spec requires that PCIe root complex must not use the stall model due to potential deadlock. | Appendix H | yes | UEFI App | -| 705 | SMMU | L3+ | If SMMUv2 is in use, Each context bank must present a unique physical interrupt to the GIC | 4.4.5 | yes | UEFI App | -| 706 | PCIe | L1+ | Each function, or virtual function, that requires hardware I/O virtualization is associated with a SMMU context. The programming of this association is IMPLEMENTATION DEFINED and is expected to be described by system firmware data. | 8.6 | yes | UEFI App | -| 901 | Watchdog | L1+ | Watchdog Signal 1 is available. This may be confirmed in the data base. This may not be possible to exersice as its handling is platform specific | 4.2.4 | yes | Secure FW | -| 901 | Watchdog | L3 FW | The Watchdog Signal 1 is routed as a SPI to GIC and usable as an EL3 interrupt, directly targetting a single PE | 4.5.3 | yes | Secure FW | -| 902 | System counter and generic timer | L0+ | Must implement at least 56 bits | 4.1.5 | yes | Secure FW | -| 902 | System counter and generic timer | L0+ | The counter shall be sized and programmed to ensure that rollover never occurs in pract | 4.1.5 | yes | Secure FW | -| 902 | System counter and generic timer | L1+ | In systems that implement EL3, CNTControlBase should be mapped to Secure address space only | 4.2.3 | yes | Secure FW | -| 902 | System counter and generic timer | L1+ | Generic Timer required registers are implemented as specified in section 4.2.3.1 "Summary of required registers of the CNTControlBase frame" | 4.2.3.1 | yes | Secure FW | -| 903 | System counter and generic timer | L1- | The local PE timer when expiring must generate a PPI when EL3 physical timer expires | 4.1.5 | yes | Secure FW | -| 903 | System counter and generic timer | L2+ | The local PE timer when expiring must generate a PPI when EL3 physical timer expires, and PPI must be 29 | 4.3.2.1 | yes | Secure FW | -| 904 | System counter and generic timer | L0+ | Any local timers that are marked by PE as always ON must be able to wake up the system. This applies to expiry of all secure views of the local timer (CNTPS) | 4.1.7 | yes | Secure FW | -| 904 | Watchdog | L3 FW | Secure Watchdog is implemented. Secure watchdog is not-aliased in non-secure address space. Signal 0 if secure watchdog is routed as an SPI and usable as an interrupt to EL3, directly targetting a single PE | 4.5.3 | yes | Secure FW | -| 905 | Peripheral Subsystems | L3 FW | Secure Generic UART is present. It is not aliased in Non-secure address space. The UARTINTR output of the secure generic UART is connected to the GIC as an SPI | 4.5.4 | yes | Secure FW | -| 906 | System counter and generic timer | L3 FW | A secure system wakeup timer is present and the interrupt is presented to GIC as a SPI | 4.5.2 | yes | Secure FW | -| 501, 502 | System counter and generic timer | L0+ | Any local timers that are marked by PE as always ON must be able to wake up the system. This applies to expiry of all non-secure views of the local timer (CNTV/P/HP/HV) | 4.1.7 | yes | UEFI App | -| 501, 502, 503, 504 | Wakeup semantics | L0+ | Whilst in state B a PE must be able to wake upon receipt of an SGI, PPI or SPI that directly targets the PE | 4.3.4/7 | yes | UEFI App | -| | PCIe | L1+ | only registers defined in the PCI Express specification and the ARM GIC specification are used to deliver legacy interrupts | 8.5 | yes | ARM Enterprise ACS package | -| | PCIe | L1+ | All end points claiming PCIe support must follow PCIe rules. | 8.9 | yes | ARM Enterprise ACS package | -| | Wakeup semantics | L0+ | Whilst in state C a PE must be able to wake upon receipt of an SGI, PPI or SPI that directly targets the PE | 4.3.4/7 | no | | -| | Wakeup semantics | L0+ | Whilst in state D a PE must be able to wake upon receipt of an SGI, PPI or SPI that directly targets the PE | 4.3.4/7 | no | | -| | Wakeup semantics | L0+ | Whilst in state E a PE must be able to wake upon receipt of an SGI, PPI or SPI that directly targets the PE | 4.3.4/7 | no | | -| | Wakeup semantics | L0+ | Whilst in state G a PE must be able to wake upon receipt of an SGI, PPI or SPI that directly targets the PE | 4.3.4/7 | no | | -| | Wakeup semantics | L0+ | Whilst in state H a PE must be able to wake upon receipt of an SGI, PPI or SPI that directly targets the PE | 4.3.4/7 | no | | -| | Power State Semantics | L2+ | System MMUs and, in the future, GICv3, make use of tables in memory in the power states where GIC is ‘On’, system memory shall be available and will respond to requests without requiring intervention from software. | 4.1.7 | no | | -| | Wakeup semantics | L1+ | Power States A-I as described in "Requirements on power state semantics" shall be covered | 4.2.5 | no | | -| | PCIe | L0+ | PCI Express transactions marked as No_snoop accessing memory that the PE translation tables attribute as cacheable and shared behave correctly when appropriate SW coherence is deployed | 8.7 | no | | -| | PCIe | L3+ | Systems compatible with level 3 or above of the SBSA must not deadlock if PCI express devices attempt peer-to-peer transactions – even if the system does not support peer-to-peer traffic | 8.10 | no | | -| | Debug | L2+ | COMMIRQ interrupt for Debug Communications Channel will be wired as PPI 22 | 4.3.2.1 | no | | -| | Debug | L2+ | Cross trigger interface interrupt shall be wired as PPI 24 | 4.3.2.3 | no | | -| | System counter and generic timer | L2+ | Where a system wake up timer is present it shall generate an SPI or LPI that wake the platform from states with semantics B,C,D,E,F,H,I | 4.3.6 | no | | -| | Watchdog | L3 FW | Routing of Signal 1 of Secure Watchdog to Platform | 4.5.3 | no | | +# SBSA ACS Testcase checklist + +## Test Number mapped to SBSA specification section + + - Also, indicates the test coverage. + +| Test Number | Component | Level | Test assertion | Section | Checked by ACS Now | Test Environment | +|----------------|----------------------------------|-------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-----------------|--------------------|----------------------------| +| 1 | PE | L0 | Number must be < 8 | 4.1.1 | yes | UEFI App | +| 2 | PE | L0+ | PE(s) must implement SIMD extensions | 4.1.1 | yes | UEFI App | +| 3 | PE | L0+ | PE(s) shall implement 16 bit ASID support | 4.1.1 | yes | UEFI App | +| 4 | PE | L0+ | PE(s) shall support 4KB and 64KB at stage 1 and 2 | 4.1.1 | yes | UEFI App | +| 5 | PE | L0+ | cache architecture type VIPT or PIPT | 4.1.1 | yes | UEFI App | +| 6 | PE | L0+ | All PE(s) are coherent in the same same inner sharable domain | 4.1.1 | yes | UEFI App | +| 7 | PE | L0+ | PE(s) where export restrictions allow should implement cryptography extensions | 4.1.1 | yes | UEFI App | +| 8 | PE | L0+ | PE(s) shall implement LE support | 4.1.1 | yes | UEFI App | +| 9 | PE | L0+ | PE(s) shall implement EL2 | 4.1.1 | yes | UEFI App | +| 10 | PE | L0+ | PE(s) shall implement AArch64 at all levels | 4.1.1 | yes | UEFI App | +| 11 | PE | L1- | The PMU overflow signal for each PE must be wired as a unique SPI or PPI with no intervening logic | 4.1.1 | yes | UEFI App | +| 11 | PE | L2+ | The PMU overflow signal from each PE must be wired to a unique PPI interrupt with no intervening logic. PPI must be 23 | 4.3.1 | yes | UEFI App | +| 12 | PE | L0 | Each PE will implement a minimal of four programable PMU counters | 4.1.1 | yes | UEFI App | +| 12 | PE | L1+ | Each PE must implement a minimum of six programmable PMU counters | 4.2.1 | yes | UEFI App | +| 13 | PE | L0+ | Each PE will implement a minimal of four synchronous watchpoints | 4.1.1 | yes | UEFI App | +| 14 | PE | L0 | Each PE implements a minimum of four breakpoints, two of which must be able to match virtual address, contextID or VMID | 4.1.1 | yes | UEFI App | +| 14 | PE | L1+ | Each PE must implement a minimum of six breakpoints, two of which must be able to match virtual address, contextID or VMID | 4.2.1 | yes | UEFI App | +| 15 | PE | L0+ | All PE(s) are architecturally symetric (allowed exceptions in Appendix C) | 4.1.1 | yes | UEFI App | +| 16 | PE | L3+ | Each PE implements EL3 Exception Level | 4.4.1 | yes | UEFI App | +| 17 | PE | L3+ | Each PE implements CRC32 instructions | 4.4.1 | yes | UEFI App | +| 18 | PE | L2+ | PMBIRQ will be wired as PPI 21 | 4.3.2.2 | yes | UEFI App | +| 19 | PE | L4+ | All PEs must implement the RAS extension introduced in ARMv8.2 | 4.3.1 | yes | UEFI App | +| 20 | PE | L4+ | All PEs must implement support for 16-bit VMD | 4.3.1 | yes | UEFI App | +| 21 | PE | L4+ | All PEs must implement virtual host extensions | 4.3.1 | yes | UEFI App | +| 22 | PE | L5+ | All PEs must provide support for stage-2 control of memory types and cacheability, as introduced by ARMv8.4 extensions | 4.4.1 | yes | UEFI App | +| 23 | PE | L5+ | All PEs must implement enhanced nested virtualization | 4.4.1 | yes | UEFI App | +| 24 | PE | L5+ | All PEs must support changing of page table mapping size using level1 and level2 solution proposed in the ARMv8.4 extension. Level2 is recommended | 4.4.1 | yes | UEFI App | +| 25 | PE | L4+ | If PEs implement ARMv8.3 pointer signing, the PEs must provide the standard algorithm defined by the ARM architecture | 4.4.1 | yes | UEFI App | +| 26 | PE | L5+ | All PEs must implement the Activity Monitors Extension | 4.4.1 | yes | UEFI App | +| 27 | PE | L5+ | Where export control allows, all PEs must implement cryptography support for SHA3 and SHA512 | 4.4.1 | yes | UEFI App | +| 28 | PE | L3+ | Where PEs implement the scalar vector extension, the vector length maximum must be at least 256 bits | 4.1.1 | yes | UEFI App | +| 101 | GICv3 | L2+ | Interrupt controller shall conform to GICv3 specification | 4.3.2 | yes | UEFI App | +| 102 | GICv3 | L2+ | If the base server system includes PCI Express then the GICv3 interrupt controller shall implement ITS and LPI | 4.3.2 | yes | UEFI App | +| 103 | GIC | L3+ | The GICv3 interrupt controller shall support two Security states | 4.4.4 | yes | UEFI App | +| 104 | GICv2/3 | L2+ | GIC maintenance interrupt shall be wired as PPI 25 | 4.3.2.4 | yes | UEFI App | +| 201 | System counter and generic timer | L0+ | Must run between 10Mhz and 400Mhz | 4.1.5 | yes | UEFI App | +| 202 | System counter and generic timer | L1- | The local PE timer when expiring must generate a PPI when EL1 physical timer expires | 4.1.5 | yes | UEFI App | +| 202 | System counter and generic timer | L2+ | The local PE timer when expiring must generate a PPI when EL1 physical timer expires, and PPI must be 30 | 4.3.2.1 | yes | UEFI App | +| 203 | System counter and generic timer | L1- | The local PE timer when expiring must generate a PPI when the virtual timer expires | 4.1.5 | yes | UEFI App | +| 203 | System counter and generic timer | L2+ | The local PE timer when expiring must generate a PPI when the virtual timer expires, and PPI must be 27 | 4.3.2.1 | yes | UEFI App | +| 204 | System counter and generic timer | L1- | The local PE timer when expiring must generate a PPI when EL2 physical timer expires | 4.1.5 | yes | UEFI App | +| 204 | System counter and generic timer | L2+ | The local PE timer when expiring must generate a PPI when EL2 physical timer expires, and PPI must be 26 | 4.3.2.1 | yes | UEFI App | +| 205 | System counter and generic timer | L1- | For systems where PE are 8.1 or greater local PE timer when expiring must generate a PPI when EL2 virtual timer expires | 4.1.5 | yes | UEFI App | +| 205 | System counter and generic timer | L2+ | For systems where PE are 8.1 or greater local PE timer when expiring must generate a PPI when EL2 virtual timer expires, and PPI must be 28 | 4.3.2.1 | yes | UEFI App | +| 206 | System counter and generic timer | L1+ | In systems that implement EL3, the memory mapped timer (the CNTBaseN frame and associated CNTCTLBase frame) must be mapped into the Non-secure address space | 4.2.3. | yes | UEFI App | +| 206 | System counter and generic timer | L3+ | If the system includes a system wakeup timer, this memory-mapped timer must be mapped on to Non-secure address space | 4.4.6 | yes | UEFI App | +| 207 | System counter and generic timer | L1+ | Unless all local PE timers are Always ON, a system timer based on architecture memory mapped generic itmer view shall generate an SPI | 4.2.3 | yes | UEFI App | +| 208 | System counter and generic timer | L0 | A system specific system timer shall generate an SPI | 4.1.7 | yes | UEFI App | +| 301 | Watchdog | L1+ | system implements a Generic Watchdog as specified in APPENDIX A: Generic Watchdog. | | yes | UEFI App | +| 301 | Watchdog | L3+ | The watchdog required by level 2 must have both its register frames mapped on to Non-secure address space; this is referred to as the Non-secure watchdog | 4.4.7 | yes | UEFI App | +| 302 | Watchdog | L1- | Watchdog Signal 0 is routed as an SPI to the GIC and usable as a EL2 interrupt | 4.2.4 | yes | UEFI App | +| 302 | Watchdog | L2+ | Watchdog Signal 0 is routed as an SPIor LPI to the GIC and usable as a EL2 interrupt | 4.3.8 | yes | UEFI App | +| 401 | PCIe | L1+ | Systems must map memory space to PCI Express configuration space, using the PCI Express Enhanced Configuration Access Mechanism (ECAM). Tests should be robust to ARI being implemented | 8.1 | yes | Linux driver | +| 402 | PCIe | L1+ | The base address of each ECAM region is discoverable from system firmware data | 8.1 | yes | Linux driver | +| 403 | PCIe | L1+ | PEs are able to access the ECAM region | 8.1 | yes | UEFI App | +| 801 | PCIe | L3+ | PEs are able to access the ECAM region | 8.1 | yes | Linux driver | +| 404 | PCIe | L1+ | All systems must support mapping PCI Express memory space as either device memory or non-cacheable memory | 8.2 | yes | Linux driver | +| 802 | PCIe | L3+ | All systems must support mapping PCI Express memory space as either device memory or non-cacheable memory | 8.2 | yes | UEFI App | +| 404 | PCIe | L1+ | When PCI Express memory space is mapped as normal memory, the system must support unaligned accesses to that region. | 8.2 | yes | Linux driver | +| 802 | PCIe | L3+ | When PCI Express memory space is mapped as normal memory, the system must support unaligned accesses to that region. | 8.2 | yes | UEFI App | +| 405 | PCIe | L3+ | In systems that are compatible with level 3 or above of the SBSA, the addresses sent by PCI express devices must be presented to the memory system or SMMU unmodified | 8.3 | yes | Linux driver | +| 405 | PCIe | L0+ | In a system where the PCI express does not use an SMMU, the PCI express devices have the same view of physical memory as the PEs | 8.3 | yes | Linux driver | +| 405 | PCIe | L0+ | PCIe I/O Coherency Scenarios without System MMU are covered | 8.7.1 | yes | Linux driver | +| 803 | PCIe | L3+ | PCIe I/O Coherency Scenarios without System MMU are covered | 8.7.1 | yes | UEFI App | +| 405 | PCIe | L1+ | PCIe I/O Coherency Scenarios with System MMU are covered | 8.7.2 | yes | Linux driver | +| 406 | PCIe | L0+ | In a system with a SMMU for PCI express there are no transformations to addresses being sent by PCI express devices before they are presented as an input address to the SMMU. | 8.3 | yes | Linux driver | +| 406 | PCIe | L3+ | the addresses sent by PCI express devices must be presented to the memory system or SMMU unmodified | 4.4.8 | yes | Linux driver | +| 407 | PCIe | L1+ | Support for Message Signaled Interrupts (MSI/MSI-X) is required for PCI Express devices. MSI and MSI-X are edge-triggered interrupts that are delivered as a memory write transaction | 8.4 | yes | Linux driver | +| 408 | PCIe | L1+ | each unique MSI(-X) shall trigger an interrupt with a unique ID and the MSI(-X) shall target GIC registers requiring no hardware specific software to service the interrupt | 8.4 | Yes | Linux driver | +| 804 | PCIe | L3+ | each unique MSI(-X) shall trigger an interrupt with a unique ID and the MSI(-X) shall target GIC registers requiring no hardware specific software to service the interrupt | 8.4 | Yes | UEFI App | +| | PCIe | L3+ | Add GICv2/v3 support details | 8.4.1/2 | No | Linux driver | +| 409 | GICv3 | L2+ | All MSIs and MSI-x are mapped to LPI | 4.3.2 | yes | Linux driver | +| 410 | PCIe | L3+ | If the system supports PCIe PASID, then at least 16 bits of PASID must be supported | 8.11 | yes | Linux driver | +| 805 | PCIe | L3+ | If the system supports PCIe PASID, then at least 16 bits of PASID must be supported | 8.11 | yes | UEFI App | +| 411 | PCIe | L0+ | The PCI Express root complex is in the same Inner Shareable domain as the PEs | 8.7 | yes | Linux driver | +| 412 | PCIe | L1+ | Each of the 4 legacy interrupt lines must be allocated a unique SPI ID and is programmed as level sensitive | 8.5 | yes | Linux driver | +| 806 | PCIe | L3+ | Each of the 4 legacy interrupt lines must be allocated a unique SPI ID and is programmed as level sensitive | 8.5 | yes | UEFI App | +| 413 | MemoryMap | L3+ | All Non-secure on-chip masters in a base server system that are expected to be under the control of the OS or hypervisor must be capable of addressing all of the NS address space. If the master goes through a SMMU then it must be capable of addressing all of the NS address space when the SMMU is off. | 4.4.3 | yes | Linux driver | +| 413 | MemoryMap / PCIe | L3+ | Non-secure off-chip devices that cannot directly address all of the Non-secure address space must be placed behind a stage 1 System MMU compatible with the ARM SMMUv2 or SMMUv3 specification. that has an output address size large enough to address all of the Non-secure address space. | 4.4.3 | yes | Linux driver | +| 414 | Peripheral Subsystems | L3+ | Memory Attributes of DMA traffic are one of (1) Inner WB, Outer WB, Inner Shareable (2) Inner/Outer Non-Cacheable (3) Device TypeIO Coherent DMA is as per (1) Inner/Outer WB, Inner Shareable | 4.4.8 | yes | Linux driver | +| 415 | PCIe | L0+ | PCI Express transactions not marked as No_snoop accessing memory that the PE translation tables attribute as cacheable and shared are I/O Coherent with the PEs. | 8.7 | yes | Linux driver | +| 807 | PCIe | L3+ | PCI Express transactions not marked as No_snoop accessing memory that the PE translation tables attribute as cacheable and shared are I/O Coherent with the PEs. | 8.7 | yes | UEFI App | +| 416 | PCIe | L4+ | For Non-prefetchable (NP) memory, type-1 headers only support 32bit address, systems complaint with SBSA level 4 or above must support 32bit programming of NP BARs on such endpoints | D.2 | yes | Linux driver | +| 417 | PCIe | L3+ | In a system where the PCIe hierarchy allows peer to peer transactions, the root ports in an ARM based SoC must implement PCIe access control service (ACS) features | D.13 | yes | Linux driver | +| 418 | PCIe | L3+ | All PCIe switches should support the minimal features, refer D.13 section for features list | D.13 | yes | Linux driver | +| 419 | PCIe | L3+ | All multi-function devices, SR-IOV and non-SR-IOV, that are capable of peer to peer traffic between different functions should support the minimal features, refer D.13 section for features list | D.13 | no | Linux driver | +| 420, 431, 432 | PCIe | L3+ | All PCIe devices, must implement the common registers of Type 0/1 header, as per requirements in E.3 and E.4 section | E.3/4 | yes | UEFI App +| 421, 434 | PCIe | L3+ | All PCIe devices, must implement the registers of Type 0 header, as per requirements in E.3 section | E.3 | yes | UEFI App +| 422 | PCIe | L3+ | All PCIe devices, must implement the registers of Type 1 header, as per requirements in E.4 section | E.3 | yes | UEFI App +| 423 | PCIe | L3+ | i-EP Root Port, must implement the registers of PCIe capability(10h), as per requirements in E.15 section | E.15 | yes | UEFI App +| 424, 433, 435 | PCIe | L3+ | All PCIe devices, must implement the Device capability register of PCIe capability(10h), as per requirements in E.14/15 section | E.14/15 | yes | UEFI App +| 425 | PCIe | L3+ | All PCIe devices, must implement the Device Control register of PCIe capability(10h), as per requirements in E.14/15 section | E.14/15 | yes | UEFI App +| 426, 436, 437 | PCIe | L3+ | All PCIe devices, must implement the Device capabilities 2 register of PCIe capability(10h), as per requirements in E.14/15 section | E.14/15 | yes | UEFI App +| 427 | PCIe | L3+ | All PCIe devices, must implement the Device control 2 register of PCIe capability(10h), as per requirements in E.14/15 section | E.14/15 | yes | UEFI App +| 428 | PCIe | L3+ | All PCIe devices, must implement the power management capability register of power management capability(01h), as per requirements in E.14/15 section | E.14/15 | yes | UEFI App +| 429 | PCIe | L3+ | All PCIe devices, must implement the power management control/status register of power management capability(01h), as per requirements in E.14/15 section | E.14/15 | yes | UEFI App +| 430, 808 | PCIe | L3+ | Memory space access should raised Unsupported Request, when device Memory Space enable bit is clear | E.3/4 | yes | UEFI App +| 438, 439 | PCIe | L3+ | iEP root port must follow Completion timeout ranges supported, Completion timeout disable supported and AtomicOp routing supported bit as per Section E.15.11 | E.15.11 | yes | UEFI App +| 440 | PCIe | L3+ | root port must not support ATS and PRS extened capability | | yes | UEFI App +| 441 | PCIe | L3+ | RCiEP and iEP end point must support MSI or MSI-X interrupts | E.7 | yes | UEFI App +| 442 | PCIe | L3+ | RCiEP, iEP root port and iEP end point must support have Power Management Capability | E.11 | yes | UEFI App +| 443 | PCIe | L3+ | Root Port must implement ARI forwarding enable as per in E.15.12 section | E.15.12 | yes | UEFI App +| 444 | PCIe | L3+ | Root Port Configuration Space must be under same ECAM as the Configuration Space of Endpoints and switches in hierachy that originates from that port | D.1 | yes | UEFI App +| 445 | PCIe | L3+ | All Root Port Configuration Space under same Host Bridge must be in same ECAM | D.1 | yes | UEFI App +| 809 | PCIe | L3+ | Configuration transactions indented for secondary bus of root port must be of Type0 | D.1 | yes | Baremetal +| 810 | PCIe | L3+ | Configuration transactions indented for subordinate bus range of root port must be of Type1 | D.1 | yes | Baremetal +| 504 | Watchdog | L1+ | Watchdog Signal 0 should be able to wakeup at least one PE from various low power states. Based off power states supported - this should be covered for 1 of N condition with some PEs in low power and from the lowest power stated where the Watchdog is ON. | 4.2.6 | yes | UEFI App | +| 504 | System counter and generic timer | L1+ | Unless all local PE timers are Always ON, a system timer based on architecture memory mapped generic timer view shall generate an SPI that wake the platform from states with semantics B,C,D,E,F,H,I | 4.2.3 | yes | UEFI App | +| 505 | System counter and generic timer | L0 | A system specific system timer shall generate an SPI that wake the platform from states with semantics B,C,D,E,F,H,I | 4.1.7 | no | UEFI App | +| 505 | Wakeup semantics | L0+ | Whilst in state F a PE must not wake upon receipt of an SGI, PPI or SPI that directly targets the PE | 4.3.4/7 | yes | UEFI App | +| 601 | Peripheral Subsystems | L0+ | If the system has a USB2.0 host controller peripheral it must conform to EHCI v1.1 or later - Peripheral subsystems which do not conform to the above are permitted, provided that they are not required to boot and install an OS | 4.1.8 | yes | UEFI App | +| 601 | Peripheral Subsystems | L0+ | If the system has a USB3.0 host controller peripheral it must conform to XHCI v1.0 or later - Peripheral subsystems which do not conform to the above are permitted, provided that they are not required to boot and install an OS | 4.1.8 | yes | UEFI App | +| 602 | Peripheral Subsystems | L0+ | If the system has a SATA host controller peripheral it must conform to AHCI v1.3 or later - Peripheral subsystems which do not conform to the above are permitted, provided that they are not required to boot and install an OS | 4.1.8 | yes | UEFI App | +| 603 | Peripheral Subsystems | L1+ | For the purpose of system development and bring up, the base server system shall include a Generic UART. The Generic UART is specified in Appendix B. The UARTINTR interrupt output is connected to the GIC as an SPI. | 4.2.7 | yes | UEFI App | +| 603 | Peripheral Subsystems | L3+ | Check that that Generic UART is mapped to Non-Secure address space | 4.4.8 | yes | UEFI App | +| 604 | Peripheral Subsystems | L2+ | UARTINTR of the generic UART shall be connected as SPI or LPI | 4.3.9 | yes | UEFI App | +| 605 | MemoryMap | L0+ | Accesses to part of the memory map that is unpopulated should not deadlock and cause a precise data abort, SEI or SPU interrupt delivered to the GIC | 4.1.3 | yes | UEFI App | +| 605 | MemoryMap | L2+ | Where a memory access is to an unpopulated part of the addressable memory space, accesses must be terminated in a manner that is presented to the PE as either a precise Data Abort or that causes a system error interrupt or an SPI or LPI interrupt to be delivered to the GIC. | 4.3.3 | yes | UEFI App | +| 606 | Peripheral Subsystems | L3 FW | Some memory is mapped in secure address space. The memory shall not be aliased in Non-secure address space | 4.5.1 | yes | UEFI App | +| 701 | IO Virtualisation | L0+ | SMMU if present must spport a 64KB granule, For L1- this would be an SMMUv1 for L2 SMMUv2, and | 4.1.4 | yes | UEFI App | +| 702 | SMMU | L3+ | All the System MMUs in the system must the compliant with the same architecture version | 4.4.5 | yes | UEFI App | +| 703 | SMMU | L3+ | If SMMUv3 is in use, The integration of the System MMUs is compliant with the specification in APPENDIX H: SMMUv3 Integration | 4.4.5Appendix H | yes | UEFI App | +| 703 | IO Virtualisation | L2+ | Stage 2 System MMU functionality must be provided by a System MMU compatible with the ARM SMMUv2 spec | 4.3.5 | yes | UEFI App | +| 703 | SMMU | L3+ | Stage 2 System MMU functionality must be provided by a System MMU compatible with the ARM SMMUv2 or SMMUv3 specification | 4.4.5 | yes | UEFI App | +| 703 | PCIe | L1+ | Hardware support for I/O Virtualization is optional, but if required shall use a System MMU compliant with the ARM System MMU specification | 8.6 | yes | UEFI App | +| 703 | IO Virtualisation | L0+ | Policing is required at stage 2 | 4.1.4 | yes | UEFI App | +| 703 | SMMU | L4+ | Stage 1 and 2 SMMU functionality must be provided by a SMMU compatible with ARM SMMUv3 or higher | 4.3.2 | yes | UEFI App | +| 703 | SMMU | L5+ | SMMU implementations must be complaint with the ARM SMMUv3.2 architecture revision or higher | 4.3.2 | yes | UEFI App | +| 704 | SMMU | L3+ | The SMMUv3 spec requires that PCIe root complex must not use the stall model due to potential deadlock. | Appendix H | yes | UEFI App | +| 705 | SMMU | L3+ | If SMMUv2 is in use, Each context bank must present a unique physical interrupt to the GIC | 4.4.5 | yes | UEFI App | +| 706 | PCIe | L1+ | Each function, or virtual function, that requires hardware I/O virtualization is associated with a SMMU context. The programming of this association is IMPLEMENTATION DEFINED and is expected to be described by system firmware data. | 8.6 | yes | UEFI App | +| 901 | Watchdog | L1+ | Watchdog Signal 1 is available. This may be confirmed in the data base. This may not be possible to exersice as its handling is platform specific | 4.2.4 | yes | Secure FW | +| 901 | Watchdog | L3 FW | The Watchdog Signal 1 is routed as a SPI to GIC and usable as an EL3 interrupt, directly targetting a single PE | 4.5.3 | yes | Secure FW | +| 902 | System counter and generic timer | L0+ | Must implement at least 56 bits | 4.1.5 | yes | Secure FW | +| 902 | System counter and generic timer | L0+ | The counter shall be sized and programmed to ensure that rollover never occurs in pract | 4.1.5 | yes | Secure FW | +| 902 | System counter and generic timer | L1+ | In systems that implement EL3, CNTControlBase should be mapped to Secure address space only | 4.2.3 | yes | Secure FW | +| 902 | System counter and generic timer | L1+ | Generic Timer required registers are implemented as specified in section 4.2.3.1 "Summary of required registers of the CNTControlBase frame" | 4.2.3.1 | yes | Secure FW | +| 903 | System counter and generic timer | L1- | The local PE timer when expiring must generate a PPI when EL3 physical timer expires | 4.1.5 | yes | Secure FW | +| 903 | System counter and generic timer | L2+ | The local PE timer when expiring must generate a PPI when EL3 physical timer expires, and PPI must be 29 | 4.3.2.1 | yes | Secure FW | +| 904 | System counter and generic timer | L0+ | Any local timers that are marked by PE as always ON must be able to wake up the system. This applies to expiry of all secure views of the local timer (CNTPS) | 4.1.7 | yes | Secure FW | +| 904 | Watchdog | L3 FW | Secure Watchdog is implemented. Secure watchdog is not-aliased in non-secure address space. Signal 0 if secure watchdog is routed as an SPI and usable as an interrupt to EL3, directly targetting a single PE | 4.5.3 | yes | Secure FW | +| 905 | Peripheral Subsystems | L3 FW | Secure Generic UART is present. It is not aliased in Non-secure address space. The UARTINTR output of the secure generic UART is connected to the GIC as an SPI | 4.5.4 | yes | Secure FW | +| 906 | System counter and generic timer | L3 FW | A secure system wakeup timer is present and the interrupt is presented to GIC as a SPI | 4.5.2 | yes | Secure FW | +| 501, 502 | System counter and generic timer | L0+ | Any local timers that are marked by PE as always ON must be able to wake up the system. This applies to expiry of all non-secure views of the local timer (CNTV/P/HP/HV) | 4.1.7 | yes | UEFI App | +| 501, 502, 503, 504 | Wakeup semantics | L0+ | Whilst in state B a PE must be able to wake upon receipt of an SGI, PPI or SPI that directly targets the PE | 4.3.4/7 | yes | UEFI App | +| | PCIe | L1+ | only registers defined in the PCI Express specification and the ARM GIC specification are used to deliver legacy interrupts | 8.5 | yes | ARM Enterprise ACS package | +| | PCIe | L1+ | All end points claiming PCIe support must follow PCIe rules. | 8.9 | yes | ARM Enterprise ACS package | +| | Wakeup semantics | L0+ | Whilst in state C a PE must be able to wake upon receipt of an SGI, PPI or SPI that directly targets the PE | 4.3.4/7 | no | | +| | Wakeup semantics | L0+ | Whilst in state D a PE must be able to wake upon receipt of an SGI, PPI or SPI that directly targets the PE | 4.3.4/7 | no | | +| | Wakeup semantics | L0+ | Whilst in state E a PE must be able to wake upon receipt of an SGI, PPI or SPI that directly targets the PE | 4.3.4/7 | no | | +| | Wakeup semantics | L0+ | Whilst in state G a PE must be able to wake upon receipt of an SGI, PPI or SPI that directly targets the PE | 4.3.4/7 | no | | +| | Wakeup semantics | L0+ | Whilst in state H a PE must be able to wake upon receipt of an SGI, PPI or SPI that directly targets the PE | 4.3.4/7 | no | | +| | Power State Semantics | L2+ | System MMUs and, in the future, GICv3, make use of tables in memory in the power states where GIC is ‘On’, system memory shall be available and will respond to requests without requiring intervention from software. | 4.1.7 | no | | +| | Wakeup semantics | L1+ | Power States A-I as described in "Requirements on power state semantics" shall be covered | 4.2.5 | no | | +| | PCIe | L0+ | PCI Express transactions marked as No_snoop accessing memory that the PE translation tables attribute as cacheable and shared behave correctly when appropriate SW coherence is deployed | 8.7 | no | | +| | PCIe | L3+ | Systems compatible with level 3 or above of the SBSA must not deadlock if PCI express devices attempt peer-to-peer transactions – even if the system does not support peer-to-peer traffic | 8.10 | no | | +| | Debug | L2+ | COMMIRQ interrupt for Debug Communications Channel will be wired as PPI 22 | 4.3.2.1 | no | | +| | Debug | L2+ | Cross trigger interface interrupt shall be wired as PPI 24 | 4.3.2.3 | no | | +| | System counter and generic timer | L2+ | Where a system wake up timer is present it shall generate an SPI or LPI that wake the platform from states with semantics B,C,D,E,F,H,I | 4.3.6 | no | | +| | Watchdog | L3 FW | Routing of Signal 1 of Secure Watchdog to Platform | 4.5.3 | no | | +| | SMMU | L4+ | All addresses output from a device to an SMMU must lie in a continuous space with no holes. All address in said space will be treated equally by the SMMU. There should be no areas within the address space that receive exceptional treatment, such as bypassing the SMMU | 4.3.2 | no | | +| | PE | L5+ | PEs based on ARMv8.4 must implement the requirements of the CS-BSA combination C [6] | 4.4.1 | no | | +| | PE | L5+ | All PEs must implement the Memory Partitioning and Monitoring Extension with a minimal configuration | 4.4.1 | no | | +| | System counter | L5+ | A system compatible with level 5 will implement counter scaling as described in the ARMv8.4 architecture | 4.4.4 | no | | +| | PE | L4+ | if the system contains persistent memory that is exposed to the OS, all PEs must support the clean to point of persistence instruction (DC CVAP). The instruction must be able to perform a clean to the point of persistence for all memory that is exposed as persistent memory to the OS | 4.3.1 | no | | +| | PCIe | L5+ | Any system that implements PCIe Precision Time Measurement (PTM) [8] must use the ARM architecture defined System Counter [2] as PTM master time source at the PTM root(s) | D.15 | no | | +| | IO Virtualisation | L3+ | ARMv8.4 introduces TLB Invalidation instructions which apply to a range of input addresses rather than just to a single address. If PEs used by the server base system support TLB range instructions, then all OS visible masters that contain a TLB must support range invalidates | 4.1.6 | no | | +| | System counter and generic timer | L3+ | Previous versions of the SBSA imposed an upper limit of 400Mhz. This is instead replaced by an upper limit on the roll over period | 4.1.7 | no | | +| | IO Virtualisation | L5+ | MPAM architecture requires that all masters that can access an MPAM controlled resource, must support passing MPAM ID information. Therefore, an SMMUv3.2 implementation must support the MPAM extension if the requests it serves access MPAM controlled resources | 4.4.3 | no | | +| | PCIe | L3+ | If the Root port supports peer to peer traffic with other root ports, then it must support minimal features. Refer D.13 section for features list | D.13 | no | | + +## License +Arm SBSA ACS is distributed under Apache v2.0 License. + +-------------- + +*Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.* diff --git a/linux_app/sbsa-acs-app.bb b/linux_app/sbsa-acs-app.bb index 00be5336..cbd27387 100644 --- a/linux_app/sbsa-acs-app.bb +++ b/linux_app/sbsa-acs-app.bb @@ -1,3 +1,18 @@ +# Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + # yocto-bsp-filename {{=example_recipe_name}}_0.1.bb # # This file was derived from the 'Hello World!' example recipe in the @@ -16,11 +31,12 @@ SRC_URI = "file://sbsa_app_main.c \ file://include/sbsa_app.h \ file://include/sbsa_avs_common.h \ " +SRC_URI[md5sum] = "3bff44b2755c130da1c74fbf2a0223d5" S = "${WORKDIR}" do_compile() { - ${CC} sbsa_app_main.c sbsa_app_pcie.c sbsa_drv_intf.c -Iinclude -o sbsa + ${CC} sbsa_app_main.c sbsa_app_pcie.c sbsa_drv_intf.c -Iinclude -o sbsa } do_install() { diff --git a/linux_app/sbsa-acs-app/include/sbsa_app.h b/linux_app/sbsa-acs-app/include/sbsa_app.h index 4394d324..71a3a41b 100644 --- a/linux_app/sbsa-acs-app/include/sbsa_app.h +++ b/linux_app/sbsa-acs-app/include/sbsa_app.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -21,7 +21,7 @@ #define SBSA_APP_VERSION_MAJOR 2 -#define SBSA_APP_VERSION_MINOR 3 +#define SBSA_APP_VERSION_MINOR 4 #include "sbsa_drv_intf.h" diff --git a/linux_app/sbsa-acs-app/sbsa_app_main.c b/linux_app/sbsa-acs-app/sbsa_app_main.c index c82a37f5..6a9befa4 100644 --- a/linux_app/sbsa-acs-app/sbsa_app_main.c +++ b/linux_app/sbsa-acs-app/sbsa_app_main.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2020 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,7 +24,7 @@ #include "include/sbsa_app.h" #include -int g_sbsa_level = 3; +int g_sbsa_level = 4; int g_print_level = 3; int g_skip_test_num[3] = {10000, 10000, 10000}; unsigned long int g_exception_ret_addr; @@ -127,8 +127,8 @@ main (int argc, char **argv) } if (run_exerciser) { - printf("\n *** Starting PCIe Exerciser tests *** \n"); - execute_tests_exerciser(1, g_sbsa_level, g_print_level); + printf("\n *** PCIe Exerciser tests only runs on UEFI *** \n"); + //execute_tests_exerciser(1, g_sbsa_level, g_print_level); } else { printf("\n *** Starting PCIe tests *** \n"); execute_tests_pcie(1, g_sbsa_level, g_print_level); diff --git a/patches/nist_sbsa_sts.diff b/patches/nist_sbsa_sts.diff new file mode 100644 index 00000000..d0a08ad1 --- /dev/null +++ b/patches/nist_sbsa_sts.diff @@ -0,0 +1,401 @@ +diff -crB sts-2.1.2_orginal/sts-2.1.2/include/cephes.h sts-2.1.2/sts-2.1.2/include/cephes.h +*** sts-2.1.2_orginal/sts-2.1.2/include/cephes.h 2020-02-07 10:15:28.011200182 +0530 +--- sts-2.1.2/sts-2.1.2/include/cephes.h 2020-02-06 13:15:21.122288105 +0530 +*************** +*** 2,7 **** +--- 2,10 ---- + #ifndef _CEPHES_H_ + #define _CEPHES_H_ + ++ #include "../../val/include/sbsa_avs_val.h" ++ #include "../../val/include/sbsa_avs_nist.h" ++ + double cephes_igamc(double a, double x); + double cephes_igam(double a, double x); + double cephes_lgam(double x); +diff -crB sts-2.1.2_orginal/sts-2.1.2/include/defs.h sts-2.1.2/sts-2.1.2/include/defs.h +*** sts-2.1.2_orginal/sts-2.1.2/include/defs.h 2020-02-07 10:15:28.011200182 +0530 +--- sts-2.1.2/sts-2.1.2/include/defs.h 2020-02-06 13:15:21.118288188 +0530 +*************** +*** 8,15 **** + M A C R O S + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ + +! #define MAX(x,y) ((x) < (y) ? (y) : (x)) +! #define MIN(x,y) ((x) > (y) ? (y) : (x)) + #define isNonPositive(x) ((x) <= 0.e0 ? 1 : 0) + #define isPositive(x) ((x) > 0.e0 ? 1 : 0) + #define isNegative(x) ((x) < 0.e0 ? 1 : 0) +--- 8,15 ---- + M A C R O S + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ + +! //#define MAX(x,y) ((x) < (y) ? (y) : (x)) +! //#define MIN(x,y) ((x) > (y) ? (y) : (x)) + #define isNonPositive(x) ((x) <= 0.e0 ? 1 : 0) + #define isPositive(x) ((x) > 0.e0 ? 1 : 0) + #define isNegative(x) ((x) < 0.e0 ? 1 : 0) +diff -crB sts-2.1.2_orginal/sts-2.1.2/src/assess.c sts-2.1.2/sts-2.1.2/src/assess.c +*** sts-2.1.2_orginal/sts-2.1.2/src/assess.c 2020-02-07 10:15:28.011200182 +0530 +--- sts-2.1.2/sts-2.1.2/src/assess.c 2020-02-06 13:16:06.229346560 +0530 +*************** +*** 118,124 **** + int i, k, m, j, start, end, num, numread; + float c; + FILE **fp = (FILE **)calloc(numOfFiles+1, sizeof(FILE *)); +- int *results = (int *)calloc(numOfFiles, sizeof(int *)); + char *s[MAXFILESPERMITTEDFORPARTITION]; + char resultsDir[200]; + +--- 118,123 ---- +*************** +*** 284,290 **** + { + int j, pos, count, passCount, sampleSize, expCount, proportion_threshold_min, proportion_threshold_max; + int freqPerBin[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; +! double *A, *T, chi2, proportion, uniformity, p_hat, tmp; + float c; + FILE *fp; + +--- 283,289 ---- + { + int j, pos, count, passCount, sampleSize, expCount, proportion_threshold_min, proportion_threshold_max; + int freqPerBin[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; +! double *A, *T, chi2, uniformity, p_hat; + float c; + FILE *fp; + +diff -crB sts-2.1.2_orginal/sts-2.1.2/src/frequency.c sts-2.1.2/sts-2.1.2/src/frequency.c +*** sts-2.1.2_orginal/sts-2.1.2/src/frequency.c 2020-02-07 10:15:28.011200182 +0530 +--- sts-2.1.2/sts-2.1.2/src/frequency.c 2020-02-06 13:15:21.098288605 +0530 +*************** +*** 2,7 **** +--- 2,8 ---- + #include + #include + #include "../include/externs.h" ++ #include "../include/cephes.h" + + /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * + F R E Q U E N C Y T E S T +diff -crB sts-2.1.2_orginal/sts-2.1.2/src/generators.c sts-2.1.2/sts-2.1.2/src/generators.c +*** sts-2.1.2_orginal/sts-2.1.2/src/generators.c 2020-02-07 10:15:28.011200182 +0530 +--- sts-2.1.2/sts-2.1.2/src/generators.c 2020-02-06 13:17:02.508172019 +0530 +*************** +*** 45,51 **** + lcg() + { + double *DUNIF, SEED; +! int i, counter; + unsigned bit; + int num_0s, num_1s, v, bitsRead; + +--- 45,51 ---- + lcg() + { + double *DUNIF, SEED; +! int i; + unsigned bit; + int num_0s, num_1s, v, bitsRead; + +*************** +*** 55,61 **** + printf("Insufficient memory available.\n"); + exit(1); + } +- counter = 1; + + for ( v=0; v=0; i-- ) { + result = 0; +--- 172,180 ---- + ******************************************/ + int Mult(BYTE *A, BYTE *B, int LB, BYTE *C, int LC) + { +! int i, j, k; + DIGIT result; + + + for ( i=LB-1; i>=0; i-- ) { + result = 0; +*************** +*** 664,667 **** + nibble -= '0'; + p_binary[i] += nibble; + } +! } +\ No newline at end of file +--- 663,666 ---- + nibble -= '0'; + p_binary[i] += nibble; + } +! } +diff -crB sts-2.1.2_orginal/sts-2.1.2/src/matrix.c sts-2.1.2/sts-2.1.2/src/matrix.c +*** sts-2.1.2_orginal/sts-2.1.2/src/matrix.c 2020-02-07 10:15:28.011200182 +0530 +--- sts-2.1.2/sts-2.1.2/src/matrix.c 2020-02-06 13:19:10.861494036 +0530 +*************** +*** 68,81 **** + index = i+1; + while ( (index < M) && (A[index][i] == 0) ) + index++; +! if ( index < M ) + row_op = swap_rows(i, index, Q, A); + } + else { + index = i-1; + while ( (index >= 0) && (A[index][i] == 0) ) + index--; +! if ( index >= 0 ) + row_op = swap_rows(i, index, Q, A); + } + +--- 68,83 ---- + index = i+1; + while ( (index < M) && (A[index][i] == 0) ) + index++; +! +! if ( index < M ) + row_op = swap_rows(i, index, Q, A); + } + else { + index = i-1; + while ( (index >= 0) && (A[index][i] == 0) ) + index--; +! +! if ( index >= 0 ) + row_op = swap_rows(i, index, Q, A); + } + +diff -crB sts-2.1.2_orginal/sts-2.1.2/src/nonOverlappingTemplateMatchings.c sts-2.1.2/sts-2.1.2/src/nonOverlappingTemplateMatchings.c +*** sts-2.1.2_orginal/sts-2.1.2/src/nonOverlappingTemplateMatchings.c 2020-02-07 10:15:28.011200182 +0530 +--- sts-2.1.2/sts-2.1.2/src/nonOverlappingTemplateMatchings.c 2020-02-06 13:19:45.424773092 +0530 +*************** +*** 21,27 **** + number of nonperiodic templates for that file be stored in the m-th + position in the numOfTemplates variable. + ----------------------------------------------------------------------------*/ +! unsigned int bit, W_obs, nu[6], *Wj = NULL; + FILE *fp = NULL; + double sum, chi2, p_value, lambda, pi[6], varWj; + int i, j, jj, k, match, SKIP, M, N, K = 5; +--- 21,27 ---- + number of nonperiodic templates for that file be stored in the m-th + position in the numOfTemplates variable. + ----------------------------------------------------------------------------*/ +! unsigned int bit, W_obs, *Wj = NULL; + FILE *fp = NULL; + double sum, chi2, p_value, lambda, pi[6], varWj; + int i, j, jj, k, match, SKIP, M, N, K = 5; +*************** +*** 88,95 **** + fprintf(stats[TEST_NONPERIODIC], "%d", sequence[k]); + } + fprintf(stats[TEST_NONPERIODIC], " "); +- for ( k=0; k<=K; k++ ) +- nu[k] = 0; + for ( i=0; i> i) & 1; + } + } + +*************** +*** 163,169 **** + printf(" [%d] Linear Complexity Test - block length(M): %d\n", counter++, tp.linearComplexitySequenceLength); + printf("\n"); + printf(" Select Test (0 to continue): "); +! scanf("%1d", &testid); + printf("\n"); + + counter = 0; +--- 163,169 ---- + printf(" [%d] Linear Complexity Test - block length(M): %d\n", counter++, tp.linearComplexitySequenceLength); + printf("\n"); + printf(" Select Test (0 to continue): "); +! testid = 0; + printf("\n"); + + counter = 0; +*************** +*** 235,241 **** + printf(" [0] ASCII - A sequence of ASCII 0's and 1's\n"); + printf(" [1] Binary - Each byte in data file contains 8 bits of data\n\n"); + printf(" Select input mode: "); +! scanf("%1d", &mode); + printf("\n"); + if ( mode == 0 ) { + if ( (fp = fopen(streamFile, "r")) == NULL ) { +--- 235,241 ---- + printf(" [0] ASCII - A sequence of ASCII 0's and 1's\n"); + printf(" [1] Binary - Each byte in data file contains 8 bits of data\n\n"); + printf(" Select input mode: "); +! mode = 0; + printf("\n"); + if ( mode == 0 ) { + if ( (fp = fopen(streamFile, "r")) == NULL ) { +*************** +*** 376,382 **** + exit(-1); + } + sprintf(summaryfn, "experiments/%s/finalAnalysisReport.txt", generatorDir[option]); +! if ( (summary = fopen(summaryfn, "w")) == NULL ) { + printf("\t\tMAIN: Could not open stats file: <%s>", summaryfn); + exit(-1); + } +--- 376,382 ---- + exit(-1); + } + sprintf(summaryfn, "experiments/%s/finalAnalysisReport.txt", generatorDir[option]); +! if ( (summary = fopen(summaryfn, "a")) == NULL ) { + printf("\t\tMAIN: Could not open stats file: <%s>", summaryfn); + exit(-1); + } +*************** +*** 404,410 **** + } + } + printf(" How many bitstreams? "); +! scanf("%d", &numOfBitStreams); + tp.numOfBitStreams = numOfBitStreams; + printf("\n"); + } +--- 404,410 ---- + } + } + printf(" How many bitstreams? "); +! numOfBitStreams=10; + tp.numOfBitStreams = numOfBitStreams; + printf("\n"); + } +*************** +*** 507,510 **** + + if ( (testVector[0] == 1) || (testVector[TEST_LINEARCOMPLEXITY] == 1) ) + LinearComplexity(tp.linearComplexitySequenceLength, tp.n); +! } +\ No newline at end of file +--- 507,510 ---- + + if ( (testVector[0] == 1) || (testVector[TEST_LINEARCOMPLEXITY] == 1) ) + LinearComplexity(tp.linearComplexitySequenceLength, tp.n); +! } diff --git a/platform/pal_uefi/SbsaPalLib.inf b/platform/pal_uefi/SbsaPalLib.inf index 337ecb9c..e695f7f9 100644 --- a/platform/pal_uefi/SbsaPalLib.inf +++ b/platform/pal_uefi/SbsaPalLib.inf @@ -1,5 +1,5 @@ ## @file -# Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -47,7 +47,6 @@ MdeModulePkg/MdeModulePkg.dec EdkCompatibilityPkg/EdkCompatibilityPkg.dec - [LibraryClasses] IoLib BaseLib diff --git a/platform/pal_uefi/SbsaPalNistLib.inf b/platform/pal_uefi/SbsaPalNistLib.inf new file mode 100644 index 00000000..c9f47364 --- /dev/null +++ b/platform/pal_uefi/SbsaPalNistLib.inf @@ -0,0 +1,77 @@ +## @file +# Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SbsaPalNistLib + FILE_GUID = 7f2093fb-2e69-46eb-af52-ba1df42f6195 + MODULE_TYPE = UEFI_APPLICATION + VERSION_STRING = 1.0 + LIBRARY_CLASS = SbsaPalNistLib|UEFI_APPLICATION UEFI_DRIVER + +[Sources.common] + src/AArch64/ArmSmc.S + src/AArch64/AvsTestInfra.S + src/AArch64/ModuleEntryPoint.S + src/pal_misc.c + src/pal_acpi.c + src/pal_pe.c + src/pal_gic.c + src/pal_timer_wd.c + src/pal_pcie.c + src/pal_iovirt.c + src/pal_pcie_enumeration.c + src/pal_peripherals.c + src/pal_exerciser.c + src/pal_smmu.c + src/pal_nist.c + +[Packages] + StdLib/StdLib.dec + MdePkg/MdePkg.dec + ShellPkg/ShellPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + EdkCompatibilityPkg/EdkCompatibilityPkg.dec + +[LibraryClasses] + LibC + LibStdLib + IoLib + BaseLib + UefiLib + ShellLib + DebugLib + BaseMemoryLib + ShellCEntryLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + +[Protocols] + gEfiAcpiTableProtocolGuid ## CONSUMES + gHardwareInterruptProtocolGuid ## CONSUMES + gEfiCpuArchProtocolGuid ## CONSUMES + gEfiPciIoProtocolGuid ## CONSUMES + gHardwareInterrupt2ProtocolGuid ## CONSUMES + +[Guids] + gEfiAcpi20TableGuid + gEfiAcpiTableGuid + +[BuildOptions] + GCC:*_*_*_ASM_FLAGS = -march=armv8.2-a diff --git a/platform/pal_uefi/include/pal_exerciser.h b/platform/pal_uefi/include/pal_exerciser.h index ed8b5a15..ea245c5c 100644 --- a/platform/pal_uefi/include/pal_exerciser.h +++ b/platform/pal_uefi/include/pal_exerciser.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -14,27 +14,83 @@ * See the License for the specific language governing permissions and * limitations under the License. **/ +/** + * This file contains REFERENCE CODE for Exerciser PAL layer. + * The API's and MACROS needs to be populate as per platform config. +**/ #ifndef __PAL_EXERCISER_H__ #define __PAL_EXERCISER_H__ -#define EXERCISER_CLASSCODE 0x010203 -#define MAX_ARRAY_SIZE 32 +#define EXERCISER_ID 0xED0113B5 //device id + vendor id #define TEST_REG_COUNT 10 #define TEST_DDR_REGION_CNT 16 -typedef struct { - UINT64 buf[MAX_ARRAY_SIZE]; -} EXERCISER_INFO_BLOCK; +#define BUS_MEM_EN_MASK 0x06 + +/* PCIe Config space Offset */ +#define BAR0_OFFSET 0x10 +#define COMMAND_REG_OFFSET 0x04 +#define CAP_PTR_OFFSET 0x34 +#define PCIE_CAP_OFFSET 0x100 + +#define PCIE_CAP_CTRL_OFFSET 0x4// offset from the extended capability header + +/* Exerciser MMIO Offsets */ +#define INTXCTL 0x004 +#define MSICTL 0x000 +#define DMACTL1 0x08 +#define DMA_BUS_ADDR 0x010 +#define DMA_LEN 0x018 +#define DMASTATUS 0x01C +#define PCI_MAX_BUS 255 +#define PCI_MAX_DEVICE 31 + +#define PCI_EXT_CAP_ID 0x10 +#define PASID 0x1B +#define PCIE 0x1 +#define PCI 0x0 + +/* PCI/PCIe express extended capability structure's + next capability pointer mask and cap ID mask */ +#define PCIE_NXT_CAP_PTR_MASK 0x0FFF +#define PCIE_CAP_ID_MASK 0xFFFF +#define PCI_CAP_ID_MASK 0x00FF +#define PCI_NXT_CAP_PTR_MASK 0x00FF +#define CAP_PTR_MASK 0x00FF + +#define CLR_INTR_MASK 0xFFFFFFFE +#define PASID_TLP_STOP_MASK 0xFFFFFFBF +#define PASID_LEN_MASK 0xFFFFFC7F +#define DMA_TO_DEVICE_MASK 0xFFFFFFEF + +/* shift_bit */ +#define SHIFT_1BIT 1 +#define SHIFT_2BIT 2 +#define SHIFT_4BIT 4 +#define SHITT_8BIT 8 +#define MASK_BIT 1 +#define PREFETCHABLE_BIT_SHIFT 3 + +#define PCI_CAP_PTR_OFFSET 8 +#define PCIE_CAP_PTR_OFFSET 20 + +#define NO_SNOOP_START_MASK 0x20 +#define NO_SNOOP_STOP_MASK 0xFFFFFFDF +#define PCIE_CAP_DIS_MASK 0xFFFEFFFF +#define PCIE_CAP_EN_MASK (1 << 16) +#define PASID_EN_MASK (1 << 6) + -typedef struct { - UINT32 num_exerciser_cards; - EXERCISER_INFO_BLOCK info[]; //Array of information blocks - per stimulus generation controller -} EXERCISER_INFO_TABLE; +typedef enum { + TYPE0 = 0x0, + TYPE1 = 0x1, +} EXERCISER_CFG_HEADER_TYPE; typedef enum { - EXERCISER_NUM_CARDS = 0x1 -} EXERCISER_INFO_TYPE; + CFG_READ = 0x0, + CFG_WRITE = 0x1, +} EXERCISER_CFG_TXN_ATTR; typedef enum { EDMA_NO_SUPPORT = 0x0, @@ -50,7 +106,8 @@ typedef enum { MSIX_ATTRIBUTES = 0x3, DMA_ATTRIBUTES = 0x4, P2P_ATTRIBUTES = 0x5, - PASID_ATTRIBUTES = 0x6 + PASID_ATTRIBUTES = 0x6, + CFG_TXN_ATTRIBUTES = 0x7 } EXERCISER_PARAM_TYPE; typedef enum { @@ -70,7 +127,9 @@ typedef enum { PASID_TLP_START = 0x7, PASID_TLP_STOP = 0x8, NO_SNOOP_CLEAR_TLP_START = 0x9, - NO_SNOOP_CLEAR_TLP_STOP = 0xa + NO_SNOOP_CLEAR_TLP_STOP = 0xa, + START_TXN_MONITOR = 0xb, + STOP_TXN_MONITOR = 0xc } EXERCISER_OPS; typedef enum { @@ -120,13 +179,11 @@ typedef enum { EXERCISER_DATA_BAR0_SPACE = 0x2, } EXERCISER_DATA_TYPE; -VOID pal_exerciser_create_info_table (EXERCISER_INFO_TABLE *ExerciserInfoTable); -UINT32 pal_exerciser_get_info(EXERCISER_INFO_TYPE Type, UINT32 Instance); -UINT32 pal_exerciser_set_param(EXERCISER_PARAM_TYPE Type, UINT64 Value1, UINT64 Value2, UINT32 Instance); -UINT32 pal_exerciser_get_param(EXERCISER_PARAM_TYPE Type, UINT64 *Value1, UINT64 *Value2, UINT32 Instance); -UINT32 pal_exerciser_set_state(EXERCISER_STATE State, UINT64 *Value, UINT32 Instance); -UINT32 pal_exerciser_get_state(EXERCISER_STATE State, UINT64 *Value, UINT32 Instance); -UINT32 pal_exerciser_ops(EXERCISER_OPS Ops, UINT64 Param, UINT32 Instance); -UINT32 pal_exerciser_get_data(EXERCISER_DATA_TYPE Type, exerciser_data_t *Data, UINT32 Instance); +UINT32 pal_exerciser_set_param(EXERCISER_PARAM_TYPE Type, UINT64 Value1, UINT64 Value2, UINT32 Bdf); +UINT32 pal_exerciser_get_param(EXERCISER_PARAM_TYPE Type, UINT64 *Value1, UINT64 *Value2, UINT32 Bdf); +UINT32 pal_exerciser_set_state(EXERCISER_STATE State, UINT64 *Value, UINT32 Bdf); +UINT32 pal_exerciser_get_state(EXERCISER_STATE *State, UINT32 Bdf); +UINT32 pal_exerciser_ops(EXERCISER_OPS Ops, UINT64 Param, UINT32 Bdf); +UINT32 pal_exerciser_get_data(EXERCISER_DATA_TYPE Type, exerciser_data_t *Data, UINT32 Bdf, UINT64 Ecam); #endif diff --git a/platform/pal_uefi/include/pal_uefi.h b/platform/pal_uefi/include/pal_uefi.h index 86acd219..5dd8f56f 100644 --- a/platform/pal_uefi/include/pal_uefi.h +++ b/platform/pal_uefi/include/pal_uefi.h @@ -27,7 +27,11 @@ extern UINT32 g_print_level; #define AVS_PRINT_DEBUG 2 /* For Debug statements. contains register dumps etc */ #define AVS_PRINT_INFO 1 /* Print all statements. Do not use unless really needed */ -#define PCIE_READ_ERR -1 +#define PCIE_SUCCESS 0x00000000 /* Operation completed successfully */ +#define PCIE_NO_MAPPING 0x10000001 /* A mapping to a Function does not exist */ +#define PCIE_CAP_NOT_FOUND 0x10000010 /* The specified capability was not found */ +#define PCIE_UNKNOWN_RESPONSE 0xFFFFFFFF /* Function not found or UR response from completer */ + typedef struct { UINT64 Arg0; diff --git a/platform/pal_uefi/include/sbsa_pcie_enum.h b/platform/pal_uefi/include/sbsa_pcie_enum.h index b92162b4..eea47965 100644 --- a/platform/pal_uefi/include/sbsa_pcie_enum.h +++ b/platform/pal_uefi/include/sbsa_pcie_enum.h @@ -24,6 +24,10 @@ #define PCIE_EXTRACT_BDF_DEV(bdf) ((bdf >> 8) & 0xFF) #define PCIE_EXTRACT_BDF_FUNC(bdf) (bdf & 0xFF) +#define PCIE_MAX_BUS 256 +#define PCIE_MAX_DEV 32 +#define PCIE_MAX_FUNC 8 + #define PCIE_CREATE_BDF(Seg, Bus, Dev, Func) ((Seg << 24) | (Bus << 16) | (Dev << 8) | Func) diff --git a/platform/pal_uefi/src/pal_exerciser.c b/platform/pal_uefi/src/pal_exerciser.c index 3411ccf1..293eafa2 100644 --- a/platform/pal_uefi/src/pal_exerciser.c +++ b/platform/pal_uefi/src/pal_exerciser.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -14,39 +14,158 @@ * See the License for the specific language governing permissions and * limitations under the License. **/ +/** + * This file contains REFERENCE CODE for Exerciser PAL layer. + * The API's and MACROS needs to be populate as per platform config. +**/ +#include +#include +#include +#include +#include +#include +#include +#include "include/pal_uefi.h" +#include "include/pal_exerciser.h" -/* This is a place-holder file. Porting to match implementation is required */ -#include "include/pal_exerciser.h" +UINT32 +pal_mmio_read(UINT64 addr); + +VOID +pal_mmio_write(UINT64 addr, UINT32 data); + +UINT64 +pal_pcie_get_mcfg_ecam(); + /** - @brief This API popultaes information from all the PCIe stimulus generation IP available - in the system into exerciser_info_table structure - @param ExerciserInfoTable - Table pointer to be filled by this API - @return ExerciserInfoTable - Contains info to communicate with stimulus generation hardware + @brief This API increments the BDF **/ -VOID -pal_exerciser_create_info_table ( - EXERCISER_INFO_TABLE *ExerciserInfoTable +UINT32 +pal_increment_bus_dev( + UINT32 Bdf ) { - return; + UINT32 Seg; + UINT32 Bus; + UINT32 Dev; + + Seg = PCIE_EXTRACT_BDF_SEG(Bdf); + Bus = PCIE_EXTRACT_BDF_BUS(Bdf); + Dev = PCIE_EXTRACT_BDF_DEV(Bdf); + + if (Dev != PCI_MAX_DEVICE) { + Dev++; + } else { + Bus++; + Dev = 0; + } + + return PCIE_CREATE_BDF(Seg, Bus, Dev, 0); } /** - @brief This API returns the requested information about the PCIe stimulus hardware - @param Type - Information type required from the stimulus hadrware - @param Instance - Stimulus hadrware instance number - @return Value - Information value for input type + @brief This API will return the ECSR base address of particular BAR Index +**/ +UINT64 +pal_exerciser_get_ecsr_base ( + UINT32 Bdf, + UINT32 BarIndex + ) +{ + return palPcieGetBase(Bdf, BarIndex); +} + +UINT64 +pal_exerciser_get_pcie_config_offset(UINT32 Bdf) +{ + UINT32 bus = PCIE_EXTRACT_BDF_BUS(Bdf); + UINT32 dev = PCIE_EXTRACT_BDF_DEV(Bdf); + UINT32 func = PCIE_EXTRACT_BDF_FUNC(Bdf); + UINT64 cfg_addr; + + /* There are 8 functions / device, 32 devices / Bus and each has a 4KB config space */ + cfg_addr = (bus * PCIE_MAX_DEV * PCIE_MAX_FUNC * 4096) + \ + (dev * PCIE_MAX_FUNC * 4096) + (func * 4096); + + return cfg_addr; +} + +/** + @brief This function triggers the DMA operation **/ UINT32 -pal_exerciser_get_info ( - EXERCISER_INFO_TYPE Type, - UINT32 Instance +pal_exerciser_start_dma_direction ( + UINT64 Base, + EXERCISER_DMA_ATTR Direction ) { - return 0; + UINT32 Mask; + + if (Direction == EDMA_TO_DEVICE) { + Mask = DMA_TO_DEVICE_MASK;// DMA direction:to Device + // Setting DMA direction in DMA control register 1 + pal_mmio_write(Base + DMACTL1, (pal_mmio_read(Base + DMACTL1) & Mask)); + } + if (Direction == EDMA_FROM_DEVICE) { + Mask = (MASK_BIT << SHIFT_4BIT);// DMA direction:from device + // Setting DMA direction in DMA control register 1 + pal_mmio_write(Base + DMACTL1, (pal_mmio_read(Base + DMACTL1) | Mask)); + } + // Triggering the DMA + pal_mmio_write(Base + DMACTL1, (pal_mmio_read(Base + DMACTL1) | MASK_BIT)); + + // Reading the Status of the DMA + return (pal_mmio_read(Base + DMASTATUS) & ((MASK_BIT << 1) | MASK_BIT)); +} + +/** + @brief This function finds the PCI capability and return 0 if it finds. +**/ +UINT32 +pal_exerciser_find_pcie_capability ( + UINT32 ID, + UINT32 Bdf, + UINT32 Value, + UINT32 *Offset + ) +{ + UINT64 NxtPtr; + UINT32 Data; + UINT32 TempId; + UINT32 Ecam; + UINT32 IdMask; + UINT32 PtrMask; + UINT32 PtrOffset; + + Ecam = pal_pcie_get_mcfg_ecam(); + NxtPtr = PCIE_CAP_OFFSET; + + if (Value == 1) { + IdMask = PCIE_CAP_ID_MASK; + PtrMask = PCIE_NXT_CAP_PTR_MASK; + PtrOffset = PCIE_CAP_PTR_OFFSET; + NxtPtr = PCIE_CAP_OFFSET; + } + else { + IdMask = PCI_CAP_ID_MASK; + PtrMask = PCI_NXT_CAP_PTR_MASK; + PtrOffset = PCI_CAP_PTR_OFFSET; + NxtPtr = (pal_mmio_read(Ecam + CAP_PTR_OFFSET + pal_exerciser_get_pcie_config_offset(Bdf))) & CAP_PTR_MASK; + } + while (NxtPtr != 0) { + Data = pal_mmio_read(Ecam + pal_exerciser_get_pcie_config_offset(Bdf) + NxtPtr); + TempId = Data & IdMask; + if (TempId == ID){ + *Offset = NxtPtr; + return 0; + } + NxtPtr = (Data >> PtrOffset) & PtrMask; + } + sbsa_print(AVS_PRINT_ERR,L"\n No capabilities found",0); + return 1; } /** @@ -61,10 +180,41 @@ UINT32 pal_exerciser_set_param ( EXERCISER_PARAM_TYPE Type, UINT64 Value1, UINT64 Value2, - UINT32 Instance + UINT32 Bdf ) { - return 0; + UINT32 Status; + UINT32 Temp; + UINT64 Base; + + Base = pal_exerciser_get_ecsr_base(Bdf,0); + switch (Type) { + + case SNOOP_ATTRIBUTES: + return 0; + + case LEGACY_IRQ: + return 0; + + case DMA_ATTRIBUTES: + pal_mmio_write(Base + DMA_BUS_ADDR,Value1);// wrting into the DMA Control Register 2 + pal_mmio_write(Base + DMA_LEN,Value2);// writing into the DMA Control Register 3 + Temp = pal_mmio_read(Base + DMASTATUS);// Reading the DMA status register + Status = Temp & ((MASK_BIT << 1) | MASK_BIT); + return Status; + + case P2P_ATTRIBUTES: + return 0; + + case PASID_ATTRIBUTES: + return 0; + + case MSIX_ATTRIBUTES: + return 0; + + default: + return 1; + } } /** @@ -80,10 +230,37 @@ pal_exerciser_get_param ( EXERCISER_PARAM_TYPE Type, UINT64 *Value1, UINT64 *Value2, - UINT32 Instance + UINT32 Bdf ) { - return 0; + UINT32 Status; + UINT32 Temp; + UINT64 Base; + + Base = pal_exerciser_get_ecsr_base(Bdf,0); + switch (Type) { + + case SNOOP_ATTRIBUTES: + return 0; + case LEGACY_IRQ: + *Value1 = pal_mmio_read(Base + INTXCTL); + return pal_mmio_read(Base + INTXCTL) | MASK_BIT ; + case DMA_ATTRIBUTES: + *Value1 = pal_mmio_read(Base + DMA_BUS_ADDR); // Reading the data from DMA Control Register 2 + *Value2 = pal_mmio_read(Base + DMA_LEN); // Reading the data from DMA Control Register 3 + Temp = pal_mmio_read(Base + DMASTATUS); + Status = Temp & MASK_BIT;// returning the DMA status + return Status; + case P2P_ATTRIBUTES: + return 0; + case PASID_ATTRIBUTES: + return 0; + case MSIX_ATTRIBUTES: + *Value1 = pal_mmio_read(Base + MSICTL); + return pal_mmio_read(Base + MSICTL) | MASK_BIT; + default: + return 1; + } } /** @@ -100,24 +277,23 @@ pal_exerciser_set_state ( UINT32 Instance ) { - return 0; + return 0; } /** @brief This API obtains the state of the PCIe stimulus generation hardware @param State - State that is read from the stimulus hadrware - @param Value - Additional information associated with the state - @param Instance - Stimulus hardware instance number + @param Bdf - Stimulus hardware bdf number @return Status - SUCCESS if the state is successfully read from hardware **/ UINT32 pal_exerciser_get_state ( - EXERCISER_STATE State, - UINT64 *Value, - UINT32 Instance + EXERCISER_STATE *State, + UINT32 Bdf ) { - return 0; + *State = EXERCISER_ON; + return 0; } /** @@ -131,10 +307,85 @@ UINT32 pal_exerciser_ops ( EXERCISER_OPS Ops, UINT64 Param, - UINT32 Instance + UINT32 Bdf ) { - return 0; + UINT64 Base; + UINT32 Ecam; + UINT32 CapabilityOffset; + + Base = pal_exerciser_get_ecsr_base(Bdf,0); + Ecam = pal_pcie_get_mcfg_ecam(); // Getting the ECAM address + switch(Ops){ + + case START_DMA: + switch (Param) { + + case EDMA_NO_SUPPORT: + return 0; + case EDMA_COHERENT: + return 0; + case EDMA_NOT_COHERENT: + return 0; + case EDMA_FROM_DEVICE: + return pal_exerciser_start_dma_direction(Base, EDMA_FROM_DEVICE);// DMA from Device + case EDMA_TO_DEVICE: + return pal_exerciser_start_dma_direction(Base, EDMA_TO_DEVICE);// DMA to Device + default: + return 1; + } + + case GENERATE_MSI: + pal_mmio_write( Base + MSICTL , Param << 1); + pal_mmio_write( Base + MSICTL ,(pal_mmio_read(Base + MSICTL) | MASK_BIT)); + return (pal_mmio_read(Base + MSICTL ) & MASK_BIT); + + case GENERATE_L_INTR: + pal_mmio_write(Base + INTXCTL , (pal_mmio_read(Base + INTXCTL) | MASK_BIT)); + return 0; //Legacy interrupt + + case MEM_READ: + return 0; + + case MEM_WRITE: + return 0; + + case CLEAR_INTR: + pal_mmio_write(Base + INTXCTL , (pal_mmio_read(Base + INTXCTL) & CLR_INTR_MASK)); + return 0; + + case PASID_TLP_START: + pal_mmio_write(Base + DMACTL1, (pal_mmio_read(Base + DMACTL1) | (MASK_BIT << 6))); + pal_mmio_write(Base + DMACTL1, (pal_mmio_read(Base + DMACTL1) & PASID_LEN_MASK));// pasidlen + + if (!pal_exerciser_find_pcie_capability(PASID, Bdf, PCIE, &CapabilityOffset)) { + pal_mmio_write(Ecam + pal_exerciser_get_pcie_config_offset(Bdf) + CapabilityOffset + PCIE_CAP_CTRL_OFFSET, + (pal_mmio_read(Ecam + pal_exerciser_get_pcie_config_offset(Bdf) + CapabilityOffset + PCIE_CAP_CTRL_OFFSET)) | PCIE_CAP_EN_MASK); + return 0; + } + return 1; + + case PASID_TLP_STOP: + pal_mmio_write(Base + DMACTL1, (pal_mmio_read(Base + DMACTL1) & PASID_TLP_STOP_MASK)); + + if (!pal_exerciser_find_pcie_capability(PASID, Bdf, PCIE, &CapabilityOffset)) { + pal_mmio_write(Ecam + pal_exerciser_get_pcie_config_offset(Bdf) + CapabilityOffset + PCIE_CAP_CTRL_OFFSET, + (pal_mmio_read(Ecam + pal_exerciser_get_pcie_config_offset(Bdf) + CapabilityOffset + PCIE_CAP_CTRL_OFFSET)) & PCIE_CAP_DIS_MASK); + return 0; + } + return 1; + + case NO_SNOOP_CLEAR_TLP_START: + pal_mmio_write(Base + DMACTL1, (pal_mmio_read(Base + DMACTL1)) | NO_SNOOP_START_MASK);//enabling the NO SNOOP + return 0; + + case NO_SNOOP_CLEAR_TLP_STOP: + pal_mmio_write(Base + DMACTL1, (pal_mmio_read(Base + DMACTL1)) & NO_SNOOP_STOP_MASK);//disabling the NO SNOOP + return 0; + + default: + return 1; + } } /** @@ -148,8 +399,36 @@ UINT32 pal_exerciser_get_data ( EXERCISER_DATA_TYPE Type, exerciser_data_t *Data, - UINT32 Instance + UINT32 Bdf, + UINT64 Ecam ) { - return 0; + UINT32 Index; + UINT64 EcamBase; + + EcamBase = (Ecam + pal_exerciser_get_pcie_config_offset(Bdf)); + + //In the Latest version of SBSA 6.0 this part of the test is obsolete hence filling the reg with same data + UINT32 offset_table[TEST_REG_COUNT] = {0x00,0x08,0x00,0x08,0x00,0x08,0x00,0x08,0x00,0x08}; + UINT32 attr_table[TEST_REG_COUNT] = {ACCESS_TYPE_RD,ACCESS_TYPE_RD,ACCESS_TYPE_RD,ACCESS_TYPE_RD,ACCESS_TYPE_RD, + ACCESS_TYPE_RD,ACCESS_TYPE_RD,ACCESS_TYPE_RD,ACCESS_TYPE_RD,ACCESS_TYPE_RD,}; + + switch(Type){ + case EXERCISER_DATA_CFG_SPACE: + for (Index = 0; Index < TEST_REG_COUNT; Index++) { + Data->cfg_space.reg[Index].offset = (offset_table[Index] + pal_exerciser_get_pcie_config_offset (Bdf)); + Data->cfg_space.reg[Index].attribute = attr_table[Index]; + Data->cfg_space.reg[Index].value = pal_mmio_read(EcamBase + offset_table[Index]); + } + return 0; + case EXERCISER_DATA_BAR0_SPACE: + Data->bar_space.base_addr = &EcamBase; + if (((pal_exerciser_get_ecsr_base(Bdf,0) >> PREFETCHABLE_BIT_SHIFT) & MASK_BIT) == 0x1) + Data->bar_space.type = MMIO_PREFETCHABLE; + else + Data->bar_space.type = MMIO_NON_PREFETCHABLE; + return 0; + default: + return 1; + } } diff --git a/platform/pal_uefi/src/pal_gic.c b/platform/pal_uefi/src/pal_gic.c index a8337b9a..ee327e91 100644 --- a/platform/pal_uefi/src/pal_gic.c +++ b/platform/pal_uefi/src/pal_gic.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -238,3 +238,28 @@ pal_gic_free_irq ( { } + +/* Place holder function. Need to be + * implemented if needed in later releases + */ +UINT32 +pal_gic_request_msi ( + UINT32 bdf, + UINT32 IntID, + UINT32 msi_index + ) +{ + return 0xFFFFFFFF; +} + +/* Place holder function. Need to be + * implemented if needed in later releases + */ +VOID +pal_gic_free_msi ( + UINT32 bdf, + UINT32 IntID, + UINT32 msi_index + ) +{ +} diff --git a/platform/pal_uefi/src/pal_misc.c b/platform/pal_uefi/src/pal_misc.c index 5e414e82..21926281 100644 --- a/platform/pal_uefi/src/pal_misc.c +++ b/platform/pal_uefi/src/pal_misc.c @@ -241,15 +241,35 @@ pal_mem_free_shared() gBS->FreePool ((VOID *)gSharedMemory); } -/* Place holder function. Need to be - * implemented if needed in later releases +/** + * @brief Allocates requested buffer size in bytes in a contiguous memory + * and returns the base address of the range. + * + * @param Size allocation size in bytes + * @retval if SUCCESS pointer to allocated memory + * @retval if FAILURE NULL */ VOID * pal_mem_alloc ( UINT32 Size ) { - return NULL; + + EFI_STATUS Status; + VOID *Buffer; + + Buffer = NULL; + Status = gBS->AllocatePool (EfiBootServicesData, + Size, + (VOID **) &Buffer); + if (EFI_ERROR(Status)) + { + sbsa_print(AVS_PRINT_ERR, L"Allocate Pool failed %x \n", Status); + return NULL; + } + + return Buffer; + } /* Place holder function. Need to be @@ -287,5 +307,60 @@ pal_mem_virt_to_phys ( VOID *Va ) { - return NULL; + return Va; +} + +/** + @brief Compares two strings + + @param FirstString The pointer to a Null-terminated ASCII string. + @param SecondString The pointer to a Null-terminated ASCII string. + @param Length The maximum number of ASCII characters for compare. + + @return Zero if strings are identical, else non-zero value +**/ +UINT32 +pal_strncmp ( + CHAR8 *FirstString, + CHAR8 *SecondString, + UINT32 Length + ) +{ + return AsciiStrnCmp(FirstString, SecondString, Length); +} + +/** + Copies a source buffer to a destination buffer, and returns the destination buffer. + + @param DestinationBuffer The pointer to the destination buffer of the memory copy. + @param SourceBuffer The pointer to the source buffer of the memory copy. + @param Length The number of bytes to copy from SourceBuffer to DestinationBuffer. + + @return DestinationBuffer. + +**/ +VOID * +pal_memcpy ( + VOID *DestinationBuffer, + VOID *SourceBuffer, + UINT32 Length + ) +{ + return CopyMem (DestinationBuffer, SourceBuffer, Length); +} + +/** + Stalls the CPU for the number of microseconds specified by MicroSeconds. + + @param MicroSeconds The minimum number of microseconds to delay. + + @return The value of MicroSeconds inputted. + +**/ +UINT64 +pal_time_delay_ms ( + UINT64 MicroSeconds + ) +{ + return gBS->Stall(MicroSeconds); } diff --git a/platform/pal_uefi/src/pal_nist.c b/platform/pal_uefi/src/pal_nist.c new file mode 100644 index 00000000..0bdb3e3e --- /dev/null +++ b/platform/pal_uefi/src/pal_nist.c @@ -0,0 +1,32 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +**/ + +#include + +/** + @brief This API generates a 32 bit random number. + @param rng_buffer - Pointer to store the random data + + @return success/failure +**/ +UINT32 +pal_nist_generate_rng(UINT32 *rng_buffer) +{ + *rng_buffer = rand(); + return 0; + +} diff --git a/platform/pal_uefi/src/pal_pcie.c b/platform/pal_uefi/src/pal_pcie.c index 15da8923..15db5a58 100644 --- a/platform/pal_uefi/src/pal_pcie.c +++ b/platform/pal_uefi/src/pal_pcie.c @@ -143,7 +143,7 @@ pal_pcie_read_cfg(UINT32 Bdf, UINT32 offset, UINT32 *data) Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiPciIoProtocolGuid, NULL, &HandleCount, &HandleBuffer); if (EFI_ERROR (Status)) { sbsa_print(AVS_PRINT_INFO,L"No PCI devices found in the system\n"); - return PCIE_READ_ERR; + return PCIE_NO_MAPPING; } InputSeg = PCIE_EXTRACT_BDF_SEG(Bdf); @@ -160,11 +160,11 @@ pal_pcie_read_cfg(UINT32 Bdf, UINT32 offset, UINT32 *data) if (!EFI_ERROR (Status)) return 0; else - return PCIE_READ_ERR; + return PCIE_NO_MAPPING; } } } - return PCIE_READ_ERR; + return PCIE_NO_MAPPING; } /* Place holder function. Need to be diff --git a/platform/pal_uefi/src/pal_timer_wd.c b/platform/pal_uefi/src/pal_timer_wd.c index 2986f930..1cad590c 100644 --- a/platform/pal_uefi/src/pal_timer_wd.c +++ b/platform/pal_uefi/src/pal_timer_wd.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/platform/secure_sw/arm-tf/sbsa_acs_platform.h b/platform/secure_sw/arm-tf/sbsa_acs_platform.h index 6316ac70..db0e71ba 100644 --- a/platform/secure_sw/arm-tf/sbsa_acs_platform.h +++ b/platform/secure_sw/arm-tf/sbsa_acs_platform.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016, ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited or its affiliates. All rights reserved. * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/secure_sw/arm-tf/sbsa_avs.h b/platform/secure_sw/arm-tf/sbsa_avs.h index 0a383bef..af77c0dc 100644 --- a/platform/secure_sw/arm-tf/sbsa_avs.h +++ b/platform/secure_sw/arm-tf/sbsa_avs.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016, ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited or its affiliates. All rights reserved. * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -61,11 +61,15 @@ typedef enum { SBSA_SECURE_TEST_FINISH, SBSA_SECURE_INFRA_INIT, SBSA_SECURE_PLATFORM_ADDRESS, - SBSA_SECURE_PMBIRQ + SBSA_SECURE_PMBIRQ, + SBSA_SECURE_UPDATE_SVE_REG }SBSA_SECURE_TEST_INDEX_e; #define SBSA_SMC_INIT_SIGN 0x9abcdef9 #define SBSA_SECURE_GET_RESULT 0x9000 +#define SBSA_SVE_ZCR_LEN_MASK 0xF +#define SBSA_SVE_CPTR_EL3_EZ_MASK 0x100 +#define SBSA_SVE_CPTR_EL2_ZEN_MASK 0x30000 #define SBSA_GENERIC 0xA #define SP805 0xB diff --git a/platform/secure_sw/arm-tf/sbsa_avs_main.c b/platform/secure_sw/arm-tf/sbsa_avs_main.c index 36f9e746..6815a106 100644 --- a/platform/secure_sw/arm-tf/sbsa_avs_main.c +++ b/platform/secure_sw/arm-tf/sbsa_avs_main.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016, ARM Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited or its affiliates. All rights reserved. * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -396,6 +396,34 @@ sbsa_acs_pmbirq(int arg01) sbsa_acs_set_status(ACS_STATUS_PASS, SBSA_SMC_INIT_SIGN); return 0; } + +/** + @brief This API sets bits required for enabling access to SVE functionality +**/ +int +sbsa_acs_update_sve_reg() +{ + uint64_t data = 0; + + /* Set CPTR_EL3.EZ */ + data = read_cptr_el3(); + data |= SBSA_SVE_CPTR_EL3_EZ_MASK; + write_cptr_el3(data); + + /* Set ZCR_EL3.LEN */ + write_zcr_el3(SBSA_SVE_ZCR_LEN_MASK); + + /* Set CPTR_EL2.EZ */ + data = read_cptr_el2(); + data |= SBSA_SVE_CPTR_EL2_ZEN_MASK; + write_cptr_el2(data); + + /* Set ZCR_EL2.LEN */ + write_zcr_el2(SBSA_SVE_ZCR_LEN_MASK); + + sbsa_acs_set_status(ACS_STATUS_PASS, SBSA_SMC_INIT_SIGN); + return 0; +} /** @brief This API contains secure initialization code which SBSA test rely upon **/ @@ -481,6 +509,9 @@ uint64_t sbsa_smc_handler(uint32_t smc_fid, case SBSA_SECURE_PMBIRQ: SMC_RET1(handle, sbsa_acs_pmbirq(x2)); + case SBSA_SECURE_UPDATE_SVE_REG: + SMC_RET1(handle, sbsa_acs_update_sve_reg()); + case SBSA_SECURE_PLATFORM_ADDRESS: SMC_RET1(handle, sbsa_acs_secure_platform_address(x2)); diff --git a/test_pool/Makefile b/test_pool/Makefile index 35676d68..08996191 100644 --- a/test_pool/Makefile +++ b/test_pool/Makefile @@ -1,5 +1,5 @@ ## @file - # Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + # Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -38,7 +38,8 @@ sbsa_acs_test-objs += $(TEST_POOL)/pcie/test_p001.o \ $(TEST_POOL)/exerciser/test_e001.o $(TEST_POOL)/exerciser/test_e002.o \ $(TEST_POOL)/exerciser/test_e003.o $(TEST_POOL)/exerciser/test_e004.o \ $(TEST_POOL)/exerciser/test_e005.o $(TEST_POOL)/exerciser/test_e006.o \ - $(TEST_POOL)/exerciser/test_e007.o + $(TEST_POOL)/exerciser/test_e007.o $(TEST_POOL)/exerciser/test_e008.o \ + $(TEST_POOL)/exerciser/test_e009.o $(TEST_POOL)/exerciser/test_e010.o \ ccflags-y=-I$(PWD)/$(ACS_DIR)/.. -I$(PWD)/$(ACS_DIR)/val/ -I$(PWD)/$(ACS_DIR)/ -DTARGET_LINUX -Wall -Werror diff --git a/test_pool/exerciser/test_e001.c b/test_pool/exerciser/test_e001.c index f9f1debf..133d3b64 100644 --- a/test_pool/exerciser/test_e001.c +++ b/test_pool/exerciser/test_e001.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -34,9 +34,6 @@ payload(void) uint32_t pe_index; uint32_t data; uint32_t bdf; - uint32_t start_bus; - uint32_t start_segment; - uint32_t start_bdf; uint32_t instance; uint32_t reg_index; exerciser_data_t e_data; @@ -44,36 +41,37 @@ payload(void) pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); - /* Set start_bdf segment and bus numbers to 1st ecam region values */ - start_segment = val_pcie_get_info(PCIE_INFO_SEGMENT, 0); - start_bus = val_pcie_get_info(PCIE_INFO_START_BUS, 0); - start_bdf = PCIE_CREATE_BDF(start_segment, start_bus, 0, 0); while (instance-- != 0) { + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; + if (val_exerciser_get_data(EXERCISER_DATA_CFG_SPACE, &e_data, instance)) { val_print(AVS_PRINT_ERR, "\n Exerciser %d data read error ", instance); goto check_fail; } - bdf = val_pcie_get_bdf(EXERCISER_CLASSCODE, start_bdf); - start_bdf = val_pcie_increment_bdf(bdf); + bdf = val_exerciser_get_bdf(instance); /* Check ECAM config register read/write */ for (reg_index = 0; reg_index < TEST_REG_COUNT; reg_index++) { if (e_data.cfg_space.reg[reg_index].attribute == ACCESS_TYPE_RW) { - val_pcie_write_cfg(bdf, e_data.cfg_space.reg[reg_index].offset, e_data.cfg_space.reg[reg_index].value); - } - - if (val_pcie_read_cfg(bdf, e_data.cfg_space.reg[reg_index].offset, &data) == PCIE_READ_ERR) { - val_print(AVS_PRINT_ERR, "\n Exerciser %d cfg reg read error ", instance); - goto check_fail; - } - - if (data != e_data.cfg_space.reg[reg_index].value) { - val_print(AVS_PRINT_ERR, "\n Exerciser cfg reg read write mismatch %d ", data); - goto check_fail; + val_pcie_write_cfg(bdf, e_data.cfg_space.reg[reg_index].offset, + e_data.cfg_space.reg[reg_index].value); + + if (val_pcie_read_cfg(bdf, e_data.cfg_space.reg[reg_index].offset, &data) + == PCIE_NO_MAPPING) { + val_print(AVS_PRINT_ERR, "\n Exerciser %d cfg reg read error ", instance); + goto check_fail; + } + + if (data != e_data.cfg_space.reg[reg_index].value) { + val_print(AVS_PRINT_ERR, "\n Exerciser cfg reg read write mismatch %d", data); + goto check_fail; + } } } diff --git a/test_pool/exerciser/test_e002.c b/test_pool/exerciser/test_e002.c index f8e32323..25ad150d 100644 --- a/test_pool/exerciser/test_e002.c +++ b/test_pool/exerciser/test_e002.c @@ -46,6 +46,10 @@ payload(void) while (instance-- != 0) { + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; + /* Get BAR 0 details for this instance */ if (val_exerciser_get_data(EXERCISER_DATA_BAR0_SPACE, &e_data, instance)) { val_print(AVS_PRINT_ERR, "\n Exerciser %d data read error ", instance); diff --git a/test_pool/exerciser/test_e003.c b/test_pool/exerciser/test_e003.c index 97364c76..9271b2e5 100644 --- a/test_pool/exerciser/test_e003.c +++ b/test_pool/exerciser/test_e003.c @@ -53,9 +53,6 @@ payload(void) uint32_t dma_len; uint32_t base_index; uint32_t instance; - uint32_t start_bus; - uint32_t start_segment; - uint32_t start_bdf; uint32_t e_bdf; uint32_t smmu_index; void *dram_buf1_virt; @@ -68,16 +65,14 @@ payload(void) pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); - /* Set start_bdf segment and bus numbers to 1st ecam region values */ - start_segment = val_pcie_get_info(PCIE_INFO_SEGMENT, 0); - start_bus = val_pcie_get_info(PCIE_INFO_START_BUS, 0); - start_bdf = PCIE_CREATE_BDF(start_segment, start_bus, 0, 0); - while (instance-- != 0) { + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; + /* Get exerciser bdf */ - e_bdf = val_pcie_get_bdf(EXERCISER_CLASSCODE, start_bdf); - start_bdf = val_pcie_increment_bdf(e_bdf); + e_bdf = val_exerciser_get_bdf(instance); /* Get SMMU node index for this exerciser instance */ smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf)); @@ -110,14 +105,23 @@ payload(void) * As exerciser is not behind SMMU, IOVA is same as PA. Use PA to * program the exerciser DMA. */ - val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf1_phys, dma_len, instance); + + if (val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf1_phys, dma_len, instance)) { + val_print(AVS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + goto test_fail; + } + if (val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance)) { val_print(AVS_PRINT_ERR, "\n DMA write failure to exerciser %4x", instance); goto test_fail; } - /* READ Back from Exerciser to validate above DMA write */ - val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf2_iova, dma_len, instance); + /* READ Back from Exerciser to validate above DMA write */ + if (val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf2_iova, dma_len, instance)) { + val_print(AVS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + goto test_fail; + } + if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, instance)) { val_print(AVS_PRINT_ERR, "\n DMA read failure from exerciser %4x", instance); goto test_fail; diff --git a/test_pool/exerciser/test_e004.c b/test_pool/exerciser/test_e004.c index ebb3ba89..d701ef9d 100644 --- a/test_pool/exerciser/test_e004.c +++ b/test_pool/exerciser/test_e004.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,43 +26,19 @@ #define TEST_DESC "Generate MSI(X) interrupts " -static uint32_t instance; -static uint32_t irq_num; -static uint32_t mapped_irq_num; static uint32_t irq_pending; +static uint32_t lpi_int_id = 0x204C; static -int +void intr_handler(void) { - /* Call exerciser specific function to handle the interrupt */ - val_exerciser_ops(CLEAR_INTR, irq_num, instance); - /* Clear the interrupt pending state */ irq_pending = 0; - val_print(AVS_PRINT_DEBUG, "\n Received MSI interrupt %d ", irq_num); - return 0; -} - -/** - @brief Free memory allocated for a list of MSI(X) vectors - - @param list pointer to a list of MSI(X) vectors -**/ -static -void -free_msi_list (PERIPHERAL_VECTOR_LIST *list) -{ - PERIPHERAL_VECTOR_LIST *next_node; - PERIPHERAL_VECTOR_LIST *current_node; - - current_node = list; - while (current_node != NULL) { - next_node = current_node->next; - val_memory_free(current_node); - current_node = next_node; - } + val_print(AVS_PRINT_DEBUG, "\n Received MSI interrupt %x", lpi_int_id); + val_gic_end_of_interrupt(lpi_int_id); + return; } static @@ -73,93 +49,66 @@ payload (void) uint32_t count = val_peripheral_get_info (NUM_ALL, 0); uint32_t index = val_pe_get_index_mpid (val_pe_get_mpid()); uint32_t e_bdf = 0; - uint32_t start_bus; - uint32_t start_segment; - uint32_t start_bdf; - uint32_t irq_offset; uint32_t timeout; - uint32_t ret_val; - PERIPHERAL_VECTOR_LIST *e_mvec; - PERIPHERAL_VECTOR_LIST *temp_mvec; + uint32_t status; + uint32_t instance; + uint32_t num_cards; + uint32_t msi_index = 0; if(!count) { - val_set_status (index, RESULT_SKIP (g_sbsa_level, TEST_NUM, 3)); + val_set_status (index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 3)); return; } /* Read the number of excerciser cards */ - instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); - - /* Set start_bdf segment and bus numbers to 1st ecam region values */ - start_segment = val_pcie_get_info(PCIE_INFO_SEGMENT, 0); - start_bus = val_pcie_get_info(PCIE_INFO_START_BUS, 0); - start_bdf = PCIE_CREATE_BDF(start_segment, start_bus, 0, 0); + num_cards = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); - while (instance-- != 0) { + for (instance = 0; instance < num_cards; num_cards++) { /* Get the exerciser BDF */ - e_bdf = val_pcie_get_bdf(EXERCISER_CLASSCODE, start_bdf); - start_bdf = val_pcie_increment_bdf(e_bdf); - - e_mvec = NULL; - - /* Read the MSI vectors for this exerciser instance */ - if (val_get_msi_vectors(e_bdf, &e_mvec)) { - - temp_mvec = e_mvec; + e_bdf = val_exerciser_get_bdf(instance); - while (e_mvec) { + status = val_gic_request_msi(e_bdf, lpi_int_id, msi_index); - for (irq_offset = 0; irq_offset < e_mvec->vector.vector_n_irqs; irq_offset++) { - - irq_num = e_mvec->vector.vector_irq_base + irq_offset; - mapped_irq_num = e_mvec->vector.vector_mapped_irq_base + irq_offset; - - /* Register the interrupt handler */ - ret_val = val_gic_request_irq(irq_num, mapped_irq_num, intr_handler); - if (ret_val) { - val_print(AVS_PRINT_ERR, "\n IRQ registration failed for instance %4x", instance); - val_set_status(index, RESULT_FAIL (g_sbsa_level, TEST_NUM, 02)); - free_msi_list(temp_mvec); - return; - } - - /* Set the interrupt trigger status to pending */ - irq_pending = 1; - - /* Trigger the interrupt */ - val_exerciser_ops(GENERATE_MSI, irq_num, instance); + if (status) { + val_print(AVS_PRINT_ERR, "\n MSI Assignment failed for bdf : 0x%x", e_bdf); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } - /* PE busy polls to check the completion of interrupt service routine */ - timeout = TIMEOUT_LARGE; - while ((--timeout > 0) && irq_pending); + status = val_gic_install_isr(lpi_int_id, intr_handler); - if (timeout == 0) { - val_print(AVS_PRINT_ERR, "\n Interrupt trigger failed for instance %4x ", instance); - val_set_status(index, RESULT_FAIL (g_sbsa_level, TEST_NUM, 02)); - val_gic_free_irq(irq_num, mapped_irq_num); - free_msi_list(temp_mvec); - return; - } + if (status) { + val_print(AVS_PRINT_ERR, "\n Intr handler registration failed for Interrupt : 0x%x", lpi_int_id); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } - /* Return the interrupt */ - val_gic_free_irq(irq_num, mapped_irq_num); - } + /* Set the interrupt trigger status to pending */ + irq_pending = 1; - e_mvec = e_mvec->next; - } + /* Trigger the interrupt */ + val_exerciser_ops(GENERATE_MSI, msi_index, instance); - /* Return this instance dynamic memory to the heap manager */ - free_msi_list(temp_mvec); + /* PE busy polls to check the completion of interrupt service routine */ + timeout = TIMEOUT_LARGE; + while ((--timeout > 0) && irq_pending); - } else { - val_print(AVS_PRINT_ERR, "\n Failed to get MSI vectors for instance %4x", instance); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + if (timeout == 0) { + val_print(AVS_PRINT_ERR, "\n Interrupt trigger failed for Interrupt : 0x%x ", lpi_int_id); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + val_gic_free_msi(e_bdf, lpi_int_id, msi_index); return; } + /* Clear Interrupt and Mappings */ + val_gic_free_msi(e_bdf, lpi_int_id, msi_index); + } + /* Pass Test */ + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + } uint32_t diff --git a/test_pool/exerciser/test_e005.c b/test_pool/exerciser/test_e005.c index 027f2ec0..ec144c7f 100644 --- a/test_pool/exerciser/test_e005.c +++ b/test_pool/exerciser/test_e005.c @@ -51,9 +51,6 @@ payload(void) uint32_t e_valid_cnt; uint32_t e_pasid; uint64_t e_pasid_support; - uint32_t start_bus; - uint32_t start_segment; - uint32_t start_bdf; uint32_t dma_len; uint32_t smmu_index; void *src_buf_virt; @@ -66,16 +63,10 @@ payload(void) pe_index = val_pe_get_index_mpid (val_pe_get_mpid()); instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); - /* Set start_bdf segment and bus numbers to 1st ecam region values */ - start_segment = val_pcie_get_info(PCIE_INFO_SEGMENT, 0); - start_bus = val_pcie_get_info(PCIE_INFO_START_BUS, 0); - start_bdf = PCIE_CREATE_BDF(start_segment, start_bus, 0, 0); - while (instance-- != 0) { /* Get exerciser bdf */ - e_bdf = val_pcie_get_bdf(EXERCISER_CLASSCODE, start_bdf); - start_bdf = val_pcie_increment_bdf(e_bdf); + e_bdf = val_exerciser_get_bdf(instance); /* Check if exerciser and it's root port have PASID TLP Prefix support */ val_exerciser_get_param(PASID_ATTRIBUTES, &e_bdf, &e_pasid_support, instance); diff --git a/test_pool/exerciser/test_e006.c b/test_pool/exerciser/test_e006.c index be93fc24..f19d8414 100644 --- a/test_pool/exerciser/test_e006.c +++ b/test_pool/exerciser/test_e006.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -25,11 +25,11 @@ #define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 6) #define TEST_DESC "Generate PCIe legacy interrupts " -#define LEGACY_INTR_PIN_COUNT 4 +#define LEGACY_INTR_PIN_COUNT 1 static uint32_t instance; static uint32_t e_intr_line; -static uint32_t e_intr_pending; +static volatile uint32_t e_intr_pending; static void intr_handler(void) { @@ -39,9 +39,10 @@ static void intr_handler(void) /* Clear the interrupt pending state */ e_intr_pending = 0; - val_print(AVS_PRINT_DEBUG, "\n Received legacy interrupt %d", e_intr_line); -} + val_print(AVS_PRINT_INFO, " \n Received legacy interrupt %d", e_intr_line); + val_gic_end_of_interrupt(e_intr_line); +} static void @@ -49,109 +50,81 @@ payload (void) { uint32_t pe_index; - uint8_t status; uint32_t e_bdf; - uint32_t erp_bdf; - uint32_t start_segment; - uint32_t start_bus; - uint32_t start_bdf; uint32_t ret_val; uint32_t timeout; uint32_t e_intr_pin; - uint32_t pin_index; - PERIPHERAL_IRQ_MAP *erp_intr_map; + uint32_t status; + PERIPHERAL_IRQ_MAP *e_intr_map; - status = 0; pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); - /* Read the number of excerciser cards */ - instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); - - /* Set start_bdf segment and bus numbers to 1st ecam region values */ - start_segment = val_pcie_get_info(PCIE_INFO_SEGMENT, 0); - start_bus = val_pcie_get_info(PCIE_INFO_START_BUS, 0); - start_bdf = PCIE_CREATE_BDF(start_segment, start_bus, 0, 0); - - /* Allocate memory for interrupt mappings */ - erp_intr_map = val_memory_alloc(sizeof(PERIPHERAL_IRQ_MAP)); - if (!erp_intr_map) { +/* Allocate memory for interrupt mappings */ + e_intr_map = val_memory_alloc(sizeof(PERIPHERAL_IRQ_MAP)); + if (!e_intr_map) { val_print (AVS_PRINT_ERR, "\n Memory allocation error", 00); val_set_status(pe_index, RESULT_FAIL (g_sbsa_level, TEST_NUM, 02)); return; } + /* Read the number of excerciser cards */ + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + while (instance-- != 0) { + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; + /* Get the exerciser BDF */ - e_bdf = val_pcie_get_bdf(EXERCISER_CLASSCODE, start_bdf); - start_bdf = val_pcie_increment_bdf(e_bdf); - - for (pin_index = 1; pin_index <= LEGACY_INTR_PIN_COUNT; pin_index++) { - - /* Write to exerciser Interrupt Pin register. A value of 00h - * indicates that the function uses no legacy interrupt - * Message(s). Writing a value of 01h indicates, exerciser - * supports legacy interrupt message INTA; Writing a value - * of 02h indicates support for INTB; and so forth. - */ - val_pcie_read_cfg(e_bdf, PCIE_INTERRUPT_LINE, &e_intr_pin); - e_intr_pin = (e_intr_pin & (~0xFF00)) | (pin_index << 8); - val_pcie_write_cfg(e_bdf, PCIE_INTERRUPT_LINE, e_intr_pin); - - /* Derive exerciser root port (ERP) bdf */ - erp_bdf = e_bdf; - if (val_pcie_get_root_port_bdf(&erp_bdf)) { - val_print(AVS_PRINT_ERR, "\n ERP %x BDF fetch error", instance); - val_set_status(pe_index, RESULT_FAIL (g_sbsa_level, TEST_NUM, 02)); - val_memory_free(erp_intr_map); - return; - } + e_bdf = val_exerciser_get_bdf(instance); - /* Read ERP legacy interrupt mappings */ - status = val_pci_get_legacy_irq_map(erp_bdf, erp_intr_map); - if (!status) { + val_pcie_read_cfg(e_bdf, PCIE_INTERRUPT_LINE, &e_intr_pin); + val_print (AVS_PRINT_DEBUG, " e_intr_pin %x", e_intr_pin); - e_intr_line = erp_intr_map->legacy_irq_map[pin_index].irq_list[0]; + if (((e_intr_pin >> 8) == 0) || ((e_intr_pin >> 8) > 4)) + continue; - /* Register an interrupt handler to verify legacy interrupt functionality */ - ret_val = val_gic_install_isr(e_intr_line, intr_handler); - if (ret_val) - goto test_fail; + status = val_pci_get_legacy_irq_map(e_bdf, e_intr_map); + if(!status) { - /* Set the interrupt trigger status to pending */ - e_intr_pending = 1; + e_intr_pending = 1; + e_intr_line = e_intr_map->legacy_irq_map[0].irq_list[0]; - /* Trigger the legacy interrupt */ - val_exerciser_ops(GENERATE_L_INTR, e_intr_line, instance); + /* Register an interrupt handler to verify legacy interrupt functionality */ + ret_val = val_gic_install_isr(e_intr_line, intr_handler); + if (ret_val) + goto test_fail; - /* PE busy polls to check the completion of interrupt service routine */ - timeout = TIMEOUT_LARGE; - while ((--timeout > 0) && e_intr_pending); + /* Trigger the legacy interrupt */ + val_exerciser_ops(GENERATE_L_INTR, e_intr_line, instance); - if (timeout == 0) { - val_gic_free_irq(e_intr_line, 0); - val_print(AVS_PRINT_ERR, "\n Interrupt trigger failed for instance %4x ", instance); - goto test_fail; - } + /* PE busy polls to check the completion of interrupt service routine */ + timeout = TIMEOUT_LARGE; + while ((--timeout > 0) && e_intr_pending); - /* Return the interrupt */ + if (timeout == 0) { val_gic_free_irq(e_intr_line, 0); - - } else { - val_print (AVS_PRINT_ERR, "\n Legacy interrupt mapping Read error", status); + val_print(AVS_PRINT_ERR, "\n Interrupt trigger failed for bdf %lx ", e_bdf); goto test_fail; } - } + /* Return the interrupt */ + val_gic_free_irq(e_intr_line, 0); - } + } else { + val_print (AVS_PRINT_ERR, "\n Legacy interrupt mapping Read error", status); + goto test_fail; + } + } - val_memory_free(erp_intr_map); + val_memory_free(e_intr_map); val_set_status (pe_index, RESULT_PASS (g_sbsa_level, TEST_NUM, 01)); + return; test_fail: val_set_status(pe_index, RESULT_FAIL (g_sbsa_level, TEST_NUM, 02)); - val_memory_free(erp_intr_map); + val_memory_free(e_intr_map); return; } diff --git a/test_pool/exerciser/test_e007.c b/test_pool/exerciser/test_e007.c index 6582aaa6..6a3c698b 100644 --- a/test_pool/exerciser/test_e007.c +++ b/test_pool/exerciser/test_e007.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -153,9 +153,6 @@ payload (void) uint32_t pe_index; uint32_t instance; uint32_t e_bdf; - uint32_t start_segment; - uint32_t start_bus; - uint32_t start_bdf; uint32_t smmu_index; void *dram_buf1_virt; void *dram_buf1_phys; @@ -168,16 +165,10 @@ payload (void) /* Read the number of excerciser cards */ instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); - /* Set start_bdf segment and bus numbers to 1st ecam region values */ - start_segment = val_pcie_get_info(PCIE_INFO_SEGMENT, 0); - start_bus = val_pcie_get_info(PCIE_INFO_START_BUS, 0); - start_bdf = PCIE_CREATE_BDF(start_segment, start_bus, 0, 0); - while (instance-- != 0) { /* Get the exerciser BDF */ - e_bdf = val_pcie_get_bdf(EXERCISER_CLASSCODE, start_bdf); - start_bdf = val_pcie_increment_bdf(e_bdf); + e_bdf = val_exerciser_get_bdf(instance); /* Find SMMU node index for this exerciser instance */ smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf)); @@ -200,7 +191,7 @@ payload (void) /* Get a WB, outer shareable DDR Buffer of size TEST_DATA_BLK_SIZE */ dram_buf1_virt = val_memory_alloc_coherent(e_bdf, TEST_DATA_BLK_SIZE, dram_buf1_phys); if (!dram_buf1_virt) { - val_print(AVS_PRINT_ERR, "\n WB and OSH mem alloc failure %x", 02); + val_print(AVS_PRINT_ERR, "\n WB and OSH mem alloc failure %x", 02); val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); return; } diff --git a/test_pool/exerciser/test_e008.c b/test_pool/exerciser/test_e008.c new file mode 100644 index 00000000..f0230679 --- /dev/null +++ b/test_pool/exerciser/test_e008.c @@ -0,0 +1,187 @@ +/** @file + * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie_enumeration.h" +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_exerciser.h" + +#define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 8) +#define TEST_DESC "Check BME functionality of RP " + +#define TEST_DMA_SIZE (4*1024) + +static void *branch_to_test; + +/* + * Execption is not expected in this test scenario. + * The handler is present just as a fail-safe mechanism. + */ +static +void +esr(uint64_t interrupt_type, void *context) +{ + + /* Update the ELR to return to test specified address */ + val_pe_update_elr(context, (uint64_t)branch_to_test); + + val_print(AVS_PRINT_INFO, "\n Received exception of type: %d", interrupt_type); +} + + + +static +void +payload(void) +{ + + uint32_t pe_index; + uint32_t e_bdf; + uint32_t erp_bdf; + uint32_t instance; + uint64_t bar_base; + uint32_t fail_cnt; + uint32_t smmu_index; + uint32_t dma_len; + void *dram_buf_virt; + void *dram_buf_phys; + void *dram_buf_iova; + + fail_cnt = 0; + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + + /* Install sync and async handlers to handle exceptions.*/ + val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr); + val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); + branch_to_test = &&exception_return; + + /* Create a buffer of size TEST_DMA_SIZE in DRAM */ + dram_buf_virt = val_memory_alloc(TEST_DMA_SIZE); + if (!dram_buf_virt) + { + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + + dram_buf_phys = val_memory_virt_to_phys(dram_buf_virt); + dma_len = TEST_DMA_SIZE; + + while (instance-- != 0) { + + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; + + e_bdf = val_exerciser_get_bdf(instance); + + /* Skip this exerciser if it doesn't have mmio BAR */ + val_pcie_get_mmio_bar(e_bdf, &bar_base); + if (!bar_base) + continue; + + /* + * Disable Bus Master Enable bit in Exierciser upstream Root + * Port Command Register. This bit controls forwarding of + * Memory Requests by a Root Port in the Upstream direction. + * When this bit is 0b, Memory Requests received at a Root Port + * must be handled as Unsupported Requests (UR). + */ + if (!val_pcie_get_rootport(e_bdf, &erp_bdf)) + val_pcie_disable_bme(erp_bdf); + else + continue; + + /* Disable error reporting of Exerciser upstream Root Port */ + val_pcie_disable_eru(erp_bdf); + + /* + * Clear unsupported request detected bit in Exerciser upstream + * Rootport's Device Status Register to clear any pending urd status. + */ + val_pcie_clear_urd(erp_bdf); + + /* + * Get SMMU node index for this exerciser instance to convert + * the dram physical addresses to IOVA addresses for DMA purposes. + */ + smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf)); + if (smmu_index == AVS_INVALID_INDEX) + dram_buf_iova = dram_buf_phys; + else + dram_buf_iova = (void *) val_smmu_pa2iova(smmu_index, (uint64_t)dram_buf_phys); + + /* + * Issue a Memory Read request from exerciser to cause unsupported + * request detected bit set in exercise's Device Status Register. + * Based on platform configuration, this may even cause a + * sync/async exception. + */ + val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf_iova, dma_len, instance); + val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance); + +exception_return: + /* Check if UR detected bit isn't set in the Root Port */ + if (val_pcie_is_urd(erp_bdf)) + { + /* Clear urd bit in Device Status Register */ + val_pcie_clear_urd(erp_bdf); + } else + { + val_print(AVS_PRINT_ERR, "\n BDF 0x%x BME functionality failure", erp_bdf); + fail_cnt++; + } + + /* Restore Rootport Bus Master Enable */ + val_pcie_enable_bme(erp_bdf); + + } + + /* Return the buffer to the heap manager */ + val_memory_free(dram_buf_virt); + + if (fail_cnt) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, fail_cnt)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + + return; + +} + +uint32_t +e008_entry(void) +{ + uint32_t num_pe = 1; + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* Get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/exerciser/test_e009.c b/test_pool/exerciser/test_e009.c new file mode 100644 index 00000000..4a8c359b --- /dev/null +++ b/test_pool/exerciser/test_e009.c @@ -0,0 +1,102 @@ +/** @file + * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie_enumeration.h" +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_exerciser.h" + +#define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 9) +#define TEST_DESC "Check RP Sec Bus transactions are TYPE0" + + +static +void +payload(void) +{ + + uint32_t pe_index; + uint32_t e_bdf; + uint32_t erp_bdf; + uint32_t reg_value; + uint32_t instance; + uint32_t fail_cnt; + uint64_t header_type; + + fail_cnt = 0; + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + + while (instance-- != 0) + { + + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; + + e_bdf = val_exerciser_get_bdf(instance); + + /* Check if exerciser is child of one of the rootports */ + if (val_pcie_parent_is_rootport(e_bdf, &erp_bdf)) + continue; + /* + * Generate a config request from PE to the Secondary bus + * of the exerciser's root port. Exerciser should see this + * request as a Type 0 Request. + */ + val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance); + val_pcie_read_cfg(e_bdf, TYPE01_VIDR, ®_value); + val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance); + val_exerciser_get_param(CFG_TXN_ATTRIBUTES, (uint64_t *)&header_type, 0, instance); + if (header_type != TYPE0) + { + val_print(AVS_PRINT_ERR, "\n BDF 0x%x Sec Bus Transaction failure", erp_bdf); + fail_cnt++; + } + } + + if (fail_cnt) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, fail_cnt)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + + return; + +} + +uint32_t +e009_entry(void) +{ + uint32_t num_pe = 1; + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* Get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/exerciser/test_e010.c b/test_pool/exerciser/test_e010.c new file mode 100644 index 00000000..f395cae2 --- /dev/null +++ b/test_pool/exerciser/test_e010.c @@ -0,0 +1,190 @@ +/** @file + * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie_enumeration.h" +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_exerciser.h" + +#define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 10) +#define TEST_DESC "Check RP Sub Bus transactions are TYPE1" + +#define MAX_BUS 255 +#define BUS_SHIFT 8 +#define BUS_MASK 0xff + +uint8_t +get_rp_right_sibling(uint32_t rp_bdf, uint32_t *rs_bdf) +{ + + uint32_t dp_type; + uint32_t tbl_bdf; + uint32_t tbl_index; + uint32_t tbl_reg_value; + uint32_t rp_reg_value; + pcie_device_bdf_table *bdf_tbl_ptr; + + tbl_index = 0; + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + while (tbl_index < bdf_tbl_ptr->num_entries) + { + tbl_bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + dp_type = val_pcie_device_port_type(tbl_bdf); + + if (tbl_bdf != rp_bdf && dp_type == RP) + { + /* + * Check if the secondary bus of the root port + * corresponding to tbl_bdf is one gretaer than + * the suborinate bus number of the input root + * port. If equal, tbl_bdf must be right sibling + * of rp_bdf. + */ + val_pcie_read_cfg(rp_bdf, TYPE1_PBN, &rp_reg_value); + val_pcie_read_cfg(tbl_bdf, TYPE1_PBN, &tbl_reg_value); + if (((tbl_reg_value >> SECBN_SHIFT) & SECBN_MASK) == + (((rp_reg_value >> SUBBN_SHIFT) & SUBBN_MASK) + 1)) + { + *rs_bdf = tbl_bdf; + return 0; + } + } + } + + /* Return failure if No right sibling */ + *rs_bdf = 0; + return 1; +} + +static +void +payload(void) +{ + + uint32_t pe_index; + uint32_t rs_flag; + uint32_t e_bdf; + uint32_t e_bus; + uint32_t erp_bdf; + uint32_t erp_rs_bdf; + uint32_t reg_value; + uint32_t erp_sub_bus; + uint32_t erp_reg_value; + uint32_t erp_rs_reg_value; + uint32_t instance; + uint32_t fail_cnt; + uint64_t header_type; + + fail_cnt = 0; + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + + while (instance-- != 0) + { + rs_flag = 0; + + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; + + e_bdf = val_exerciser_get_bdf(instance); + + /* Check if exerciser is child of one of the rootports */ + if (val_pcie_parent_is_rootport(e_bdf, &erp_bdf)) + continue; + + /* Find right sibling of the exerciser rootport */ + if (!get_rp_right_sibling(erp_bdf, &erp_rs_bdf)) + { + /* + * Save exerciser right sibling sec and sub bus numbers. + * Program those bus numbers with invalid range so that + * the right sibling doesn't receive any transactions. + */ + rs_flag = 1; + val_pcie_read_cfg(erp_rs_bdf, TYPE1_PBN, &erp_rs_reg_value); + reg_value = erp_rs_reg_value & (~(SECBN_MASK << SECBN_SHIFT)); + reg_value = reg_value & (~(SUBBN_MASK << SUBBN_SHIFT)); + reg_value = reg_value | (MAX_BUS << SECBN_SHIFT); + reg_value = reg_value | ((MAX_BUS-1) << SUBBN_SHIFT); + val_pcie_write_cfg(erp_rs_bdf, TYPE1_PBN, reg_value); + } + + /* Increase Subordinate bus register of exerciser rootport by one */ + val_pcie_read_cfg(erp_bdf, TYPE1_PBN, &erp_reg_value); + erp_sub_bus = (erp_reg_value >> SUBBN_SHIFT) & SUBBN_MASK; + reg_value = reg_value & (~(SUBBN_MASK << SUBBN_SHIFT)); + reg_value = reg_value | ((erp_sub_bus + 1) << SUBBN_SHIFT); + + /* Increment bus number in e_bdf variable */ + e_bus = (e_bdf >> BUS_SHIFT) & BUS_MASK; + e_bdf = e_bdf & (~(BUS_MASK << BUS_SHIFT)); + e_bdf = e_bdf | ((e_bus + 1) << BUS_SHIFT); + + /* + * Generate a config request from PE to the Subordinate bus + * of the exerciser. Exerciser should see this request as a + * Type 1 Request. + */ + val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance); + val_pcie_read_cfg(e_bdf, TYPE01_VIDR, ®_value); + val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance); + val_exerciser_get_param(CFG_TXN_ATTRIBUTES, (uint64_t *)&header_type, 0, instance); + if (header_type != TYPE1) + { + val_print(AVS_PRINT_ERR, "\n BDF 0x%x Sub Bus Transaction failure", erp_bdf); + fail_cnt++; + } + + /* Restore Exerciser rootport and it's right sibling subordinate bus registers */ + val_pcie_write_cfg(erp_bdf, TYPE1_PBN, erp_reg_value); + if (rs_flag) + val_pcie_write_cfg(erp_rs_bdf, TYPE1_PBN, erp_rs_reg_value); + } + + if (fail_cnt) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, fail_cnt)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + + return; + +} + +uint32_t +e010_entry(void) +{ + uint32_t num_pe = 1; + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* Get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/nist_sts/SbsaNistLib.inf b/test_pool/nist_sts/SbsaNistLib.inf new file mode 100644 index 00000000..bda9ebab --- /dev/null +++ b/test_pool/nist_sts/SbsaNistLib.inf @@ -0,0 +1,78 @@ +## @file +# Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SbsaNistLib + FILE_GUID = 27cb25d8-396b-4088-9d31-905ed0be3390 + MODULE_TYPE = UEFI_APPLICATION + VERSION_STRING = 1.0 + LIBRARY_CLASS = SbsaNistLib|UEFI_APPLICATION UEFI_DRIVER + +[Sources.common] + sts-2.1.2/sts-2.1.2/src/approximateEntropy.c + sts-2.1.2/sts-2.1.2/src/assess.c + sts-2.1.2/sts-2.1.2/src/blockFrequency.c + sts-2.1.2/sts-2.1.2/src/cephes.c + sts-2.1.2/sts-2.1.2/src/cusum.c + sts-2.1.2/sts-2.1.2/src/dfft.c + sts-2.1.2/sts-2.1.2/src/discreteFourierTransform.c + sts-2.1.2/sts-2.1.2/src/frequency.c + sts-2.1.2/sts-2.1.2/src/generators.c + sts-2.1.2/sts-2.1.2/src/genutils.c + sts-2.1.2/sts-2.1.2/src/linearComplexity.c + sts-2.1.2/sts-2.1.2/src/longestRunOfOnes.c + sts-2.1.2/sts-2.1.2/src/matrix.c + sts-2.1.2/sts-2.1.2/src/nonOverlappingTemplateMatchings.c + sts-2.1.2/sts-2.1.2/src/overlappingTemplateMatchings.c + sts-2.1.2/sts-2.1.2/src/randomExcursions.c + sts-2.1.2/sts-2.1.2/src/randomExcursionsVariant.c + sts-2.1.2/sts-2.1.2/src/rank.c + sts-2.1.2/sts-2.1.2/src/runs.c + sts-2.1.2/sts-2.1.2/src/serial.c + sts-2.1.2/sts-2.1.2/src/universal.c + sts-2.1.2/sts-2.1.2/src/utilities.c + +[Packages] + StdLib/StdLib.dec + MdePkg/MdePkg.dec + ShellPkg/ShellPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + EdkCompatibilityPkg/EdkCompatibilityPkg.dec + SecurityPkg/SecurityPkg.dec + +[LibraryClasses] + LibC + LibStdLib + LibStdio + LibMath + DevShell + SbsaValNistLib + SbsaPalNistLib + BaseLib + IoLib + UefiLib + ShellLib + DebugLib + BaseMemoryLib + ShellCEntryLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + +[BuildOptions] + GCC:*_*_*_ASM_FLAGS = -march=armv8.2-a diff --git a/test_pool/nist_sts/test_n001.c b/test_pool/nist_sts/test_n001.c new file mode 100755 index 00000000..d61b2f67 --- /dev/null +++ b/test_pool/nist_sts/test_n001.c @@ -0,0 +1,275 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include +#include +#include +#include + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" +#include "val/include/sbsa_avs_nist.h" + +#define TEST_NUM (AVS_NIST_TEST_NUM_BASE + 1) +#define TEST_DESC "NIST Statistical Test Suite \n " + +#define BUFFER_SIZE 1000 +#define RND_FILE_SIZE 36428 +#define REQ_OPEN_FILES 30 +#define ALL_NIST_TEST 0xFFFE +#define NIST_SUITE_1 0xFE +#define NIST_SUITE_2 0xDE00 /* Test 1 - 7 */ +#define MIN_NIST_TEST 0x0000 /* Test 9 - 12, 13 - 14 */ + +extern int main(int argc, char *argv[]); + +/*Enabling all NIST test suites(test 1 - 15) by default */ +uint32_t test_select = ALL_NIST_TEST; + +static +int32_t +check_prerequisite_nist(void) +{ + FILE *fp[REQ_OPEN_FILES]; + char file_name[REQ_OPEN_FILES][20]; + int32_t i; + uint32_t status = AVS_STATUS_PASS; + char result_file[] = "experiments/AlgorithmTesting/finalAnalysisReport.txt"; + + /* Check the max # of opened file requiremnt for + * executing NIST test suite. + */ + for (i = 0; i < REQ_OPEN_FILES; i++) { + sprintf(file_name[i], "tmp_%d.txt", i); + fp[i] = fopen(file_name[i], "wb"); + if (fp[i] == NULL) { + val_print(AVS_PRINT_ERR, "\nMax # of opened files has been reached. " + "NIST prerequistite failed: %d", i); + status = AVS_STATUS_FAIL; + break; + } + } + + for (i = i - 1; i >= 0; i--) + { + fclose(fp[i]); + remove(file_name[i]); + } + + remove(result_file); + val_print(AVS_PRINT_INFO, "\nAll NIST Prerequistite were met", 0); + return status; +} + +static +int32_t +print_nist_result(void) +{ + FILE *fptr; + char buffer[BUFFER_SIZE]; + int32_t totalRead = 0; + char filename[] = "experiments/AlgorithmTesting/finalAnalysisReport.txt"; + + // Open report file + fptr = fopen(filename, "r"); + if (fptr == NULL) + { + val_print(AVS_PRINT_ERR, "Cannot open file \n", 0); + return AVS_STATUS_FAIL; + } + + while (fgets(buffer, BUFFER_SIZE, fptr) != NULL) + { + /* Total character read count */ + totalRead = strlen(buffer); + + /* Trim new line character from last if exists */ + buffer[totalRead - 1] = buffer[totalRead - 1] == '\n' + ? '\0' + : buffer[totalRead - 1]; + + /* Print line read on cosole*/ + //ToDo: Print using val_print + //val_print(AVS_PRINT_TEST, "%s\n", buffer); + printf("%s\n", buffer); + } + + fclose(fptr); + return AVS_STATUS_PASS; +} + +static +int32_t +create_random_file(void) +{ + uint32_t buffer, status = AVS_STATUS_FAIL; + FILE *fp; + char str[] = "data.txt"; + int32_t i, j, k, noofr = RND_FILE_SIZE; + char one = '1', zero = '0'; + + fp = fopen(str, "wb"); + if (fp == NULL) + { + val_print(AVS_PRINT_ERR, "\n Unable to create file", 0); + return AVS_STATUS_FAIL; + } + + for (i = 0; i < noofr; i++) + { + /* Get a 32-bit random number */ + status = val_nist_generate_rng(&buffer); + if (status != AVS_STATUS_PASS) { + val_print(AVS_PRINT_ERR, "\n Random number generation failed", 0); + fclose(fp); + return AVS_STATUS_FAIL; + } + + /* Convert decimal random number to binary value and + * write it as ASCII value in the file + */ + for (j = 31; j >= 0; j--) { + k = buffer >> j; + if (k & 1) + fwrite(&one, sizeof(char), 1, fp); + else + fwrite(&zero, sizeof(char), 1, fp); + } + } + + fclose(fp); + val_print(AVS_PRINT_INFO, "\nA random file with sequence of ASCII 0's and 1's created", 0); + return AVS_STATUS_PASS; +} +static +void +payload() +{ + int32_t status, i, argc = 2; + char *argv[] = {"data.txt", "100000"}; + char *dirname = "experiments"; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint32_t test_list[] = {NIST_SUITE_1, NIST_SUITE_2}; + size_t test_listsize = sizeof(test_list) / sizeof(test_list[0]); + + status = check_prerequisite_nist(); + if (status != AVS_STATUS_PASS) { + /* Omitting tests 8, 9 and 13 */ + test_select = MIN_NIST_TEST; + val_print(AVS_PRINT_INFO, "\nSkipping test 8, 9 and 13 of NIST test suite", 0); + } + + /* Generate a Random file with binary ASCII values */ + status = create_random_file(); + if (status != AVS_STATUS_PASS) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Create the directories required for NIST test suite */ + status = mkdir(dirname, 0777); + dirname = "experiments/AlgorithmTesting"; + status |= mkdir(dirname, 0777); + dirname = "experiments/AlgorithmTesting/ApproximateEntropy"; + status |= mkdir(dirname, 0777); + dirname = "experiments/AlgorithmTesting/BlockFrequency"; + status |= mkdir(dirname, 0777); + dirname = "experiments/AlgorithmTesting/CumulativeSums"; + status |= mkdir(dirname, 0777); + dirname = "experiments/AlgorithmTesting/FFT"; + status |= mkdir(dirname, 0777); + dirname = "experiments/AlgorithmTesting/Frequency"; + status |= mkdir(dirname, 0777); + dirname = "experiments/AlgorithmTesting/LinearComplexity"; + status |= mkdir(dirname, 0777); + dirname = "experiments/AlgorithmTesting/LongestRun"; + status |= mkdir(dirname, 0777); + dirname = "experiments/AlgorithmTesting/NonOverlappingTemplate"; + status |= mkdir(dirname, 0777); + dirname = "experiments/AlgorithmTesting/OverlappingTemplate"; + status |= mkdir(dirname, 0777); + dirname = "experiments/AlgorithmTesting/RandomExcursions"; + status |= mkdir(dirname, 0777); + dirname = "experiments/AlgorithmTesting/RandomExcursionsVariant"; + status |= mkdir(dirname, 0777); + dirname = "experiments/AlgorithmTesting/Rank"; + status |= mkdir(dirname, 0777); + dirname = "experiments/AlgorithmTesting/Runs"; + status |= mkdir(dirname, 0777); + dirname = "experiments/AlgorithmTesting/Serial"; + status |= mkdir(dirname, 0777); + dirname = "experiments/AlgorithmTesting/Universal"; + status |= mkdir(dirname, 0777); + if (status != AVS_STATUS_PASS) { + val_print(AVS_PRINT_ERR, "\n Directory not created", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + else + val_print(AVS_PRINT_INFO, "\n Directory created", 0); + + if (test_select == MIN_NIST_TEST) { + /* Run the NIST test suite 1 and 2 as the prerequisite conditions + * were not satisfied. + */ + for (i = 0; i < test_listsize; i++) { + test_select = test_list[i]; + status = main(argc, argv); // NIST STS + if (status == AVS_STATUS_NIST_PASS) { + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + } else { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + } + } + else { + /* Run all the NIST test suite as the as the prerequisite conditions + * were satisfied. + */ + status = main(argc, argv); // NIST STS + if (status == AVS_STATUS_NIST_PASS) { + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + } else { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + } + + print_nist_result(); + return; +} + +uint32_t +n001_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This NIST test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ +// status = val_check_for_error(TEST_NUM, num_pe); + +// val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p003.c b/test_pool/pcie/test_p003.c old mode 100755 new mode 100644 index 4faf492e..3d1e0b6d --- a/test_pool/pcie/test_p003.c +++ b/test_pool/pcie/test_p003.c @@ -67,7 +67,7 @@ payload(void) bdf = PCIE_CREATE_BDF(segment, bus, 0, 0); ret = val_pcie_read_cfg(bdf, PCIE_VENDOR_ID_REG_OFFSET, &data); - if (data == 0xFFFFFFFF) { + if (data == PCIE_UNKNOWN_RESPONSE) { val_print(AVS_PRINT_ERR, "\n First device in a ECAM space is not a valid device", 0); val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, (bus << 8))); return; @@ -81,7 +81,7 @@ payload(void) ret = val_pcie_read_cfg(bdf, PCIE_VENDOR_ID_REG_OFFSET, &data); //If this is really PCIe CFG space, Device ID and Vendor ID cannot be 0 or 0xFFFF - if (ret == PCIE_READ_ERR || (data == 0) || ((data != 0xFFFFFFFF) && ((data & 0xFFFF) == 0xFFFF))) { + if (ret == PCIE_NO_MAPPING || (data == 0) || ((data & 0xFFFF) == 0xFFFF)) { val_print(AVS_PRINT_ERR, "\n Incorrect data at ECAM Base %4x ", data); val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, (bus_index << 8)|dev_index)); return; @@ -90,7 +90,7 @@ payload(void) ret = val_pcie_read_cfg(bdf, PCIE_CACHE_LINE_SIZE_REG_OFFSET, &data); //If this really is PCIe CFG, Header type[6:0] must be 01 or 00 - if (ret == PCIE_READ_ERR || ((data != 0xFFFFFFFF) && (((data >> 16) & 0x7F) > 01))) { + if (ret == PCIE_NO_MAPPING || (((data >> 16) & 0x7F) > 01)) { val_print(AVS_PRINT_ERR, "\n Incorrect PCIe CFG Hdr type %4x ", data); val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, (bus_index << 8)|dev_index)); return; diff --git a/test_pool/pcie/test_p008.c b/test_pool/pcie/test_p008.c index 51c3be29..c090013f 100644 --- a/test_pool/pcie/test_p008.c +++ b/test_pool/pcie/test_p008.c @@ -142,28 +142,36 @@ payload (void) if (check_msi_status (count - 1)) { /* Get BDF of a device */ current_dev_bdf = val_peripheral_get_info (ANY_BDF, count - 1); - val_print (AVS_PRINT_INFO, " Checking PCI device with BDF %4X\n", current_dev_bdf); - /* Read MSI(X) vectors */ - if (val_get_msi_vectors (current_dev_bdf, ¤t_dev_mvec)) { - /* Pull other PCI devices left in the devices list */ - while (count_next > 0 && !status) { - if (check_msi_status (count_next - 1)) { - /* Get BDF of a device */ - next_dev_bdf = val_peripheral_get_info (ANY_BDF, count_next - 1); - /* Read MSI(X) vectors */ - if (val_get_msi_vectors (next_dev_bdf, &next_dev_mvec)) { - /* Compare two lists of MSI(X) vectors */ - if (check_list_duplicates (current_dev_mvec, next_dev_mvec)) { - val_print (AVS_STATUS_ERR, "\n Allocated MSIs are not unique", 0); - val_set_status (index, RESULT_FAIL (g_sbsa_level, TEST_NUM, 02)); - status = 1; + if (current_dev_bdf) { + val_print (AVS_PRINT_INFO, " Checking PCI device with BDF %4X\n", current_dev_bdf); + /* Read MSI(X) vectors */ + if (val_get_msi_vectors (current_dev_bdf, ¤t_dev_mvec)) { + + /* Pull other PCI devices left in the devices list */ + while (count_next > 0 && !status) { + if (check_msi_status (count_next - 1)) { + /* Get BDF of a device */ + next_dev_bdf = val_peripheral_get_info (ANY_BDF, count_next - 1); + /* Read MSI(X) vectors */ + if (val_get_msi_vectors (next_dev_bdf, &next_dev_mvec)) { + /* Compare two lists of MSI(X) vectors */ + if(check_list_duplicates (current_dev_mvec, next_dev_mvec)) { + val_print (AVS_STATUS_ERR, "\n Allocated MSIs are not unique", 0); + val_set_status (index, RESULT_FAIL (g_sbsa_level, TEST_NUM, 02)); + status = 1; + } + clean_msi_list (next_dev_mvec); } - clean_msi_list (next_dev_mvec); } + count_next--; } - count_next--; + + clean_msi_list (current_dev_mvec); } - clean_msi_list (current_dev_mvec); + } else { + val_print (AVS_STATUS_ERR, "\n Failed to get address of PCI device", 0); + val_set_status (index, RESULT_FAIL (g_sbsa_level, TEST_NUM, 01)); + status = 1; } } count--; diff --git a/test_pool/pcie/test_p020.c b/test_pool/pcie/test_p020.c new file mode 100644 index 00000000..7662bb61 --- /dev/null +++ b/test_pool/pcie/test_p020.c @@ -0,0 +1,67 @@ +/** @file + * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "test_p020_data.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 20) +#define TEST_DESC "Check Type 0/1 common config rules" + +static +void +payload(void) +{ + + uint32_t pe_index; + uint32_t ret; + uint32_t table_entries; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + table_entries = sizeof(bf_info_table20)/sizeof(bf_info_table20[0]); + ret = val_pcie_register_bitfields_check((void *)&bf_info_table20, table_entries); + + if (ret == AVS_STATUS_SKIP) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else if (ret) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, ret)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + +} + +uint32_t +p020_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p020_data.h b/test_pool/pcie/test_p020_data.h new file mode 100644 index 00000000..01e8de3d --- /dev/null +++ b/test_pool/pcie/test_p020_data.h @@ -0,0 +1,207 @@ +/** @file + * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_pcie.h" + +/** +* The test table covers bit-field entries for registers +* which are common in both type0 and type1 header +**/ + +pcie_cfgreg_bitfield_entry bf_info_table20[] = { + + // Bit-field entry 1: Command register, bit[3] = Special Cycle Enable + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x04, // Offset from ECAM base + PCIe_ALL, // Applicable to all PCIe Functions + 3, // Start bit position + 3, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "CR SCE value mismatch", // SCE invalid configured value + "CR SCE attribute mismatch" // SCE invalid attribute + }, + + // Bit-field entry 2: Command register, bit[4] = Memory Write and Invalidate + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x04, // Offset from ECAM base + PCIe_ALL, // Applicable to all PCIe Functions + 4, // Start bit position + 4, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "CR MWI value mismatch", // MWI invalid configured value + "CR MWI attribute mismatch" // MWI invalid attribute + }, + + // Bit-field entry 3: Command register, bit[5] = VGA Palette Snoop + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x04, // Offset from ECAM base + PCIe_ALL, // Applicable to all PCIe Functions + 5, // Start bit position + 5, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "CR VPS cfg value mismatch", // VPS invalid configured value + "CR VPS attribute mismatch" // VPS invalid attribute + }, + + // Bit-field entry 4: Command register, bit[7] = IDSEL Stepping/Wait Cycle Control + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x04, // Offset from ECAM base + PCIe_ALL, // Applicable to all PCIe Functions + 7, // Start bit position + 7, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "CR IDSEL value mismatch", // IDSEL invalid configured value + "CR IDSEL attribute mismatch" // IDSEL invalid attribute + }, + + // Bit-field entry 5: Command register, bit[9] = Fast Back-to-Back Transaction Enable + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x04, // Offset from ECAM base + PCIe_ALL, // Applicable to all PCIe Functions + 9, // Start bit position + 9, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "CR FBBTE value mismatch", // FBBTE invalid configured value + "CR FBBTE attribute mismatch" // FBBTE invalid attribute + }, + + // Bit-field entry 6: Command register, bit[10] = interrupt disable + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x04, // Offset from ECAM base + (iEP_RP | iEP_EP), // Applicable to integrated endpoint pair + 10, // Start bit position + 10, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "CR ID value mismatch", // Interrupt disable invalid configured value + "CR ID attribute mismatch" // Interrupt disable invalid attribute + }, + + // Bit-field entry 7: Status register, bit[3] = Interrupt Status + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x06, // Offset from ECAM base + (iEP_RP | iEP_EP), // Applicable to integrated endpoint pair + 3, // Start bit position + 3, // End bit position + 0, // Hardwired to 1b + READ_ONLY, // Attribute is Read-only + "SR IS value mismatch", // Interrupt Status invalid configured value + "SR IS attribute mismatch" // Interrupt Status invalid attribute + }, + + // Bit-field entry 8: Status register, bit[4] = Capabilities List + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x06, // Offset from ECAM base + PCIe_ALL, // Applicable to all PCIe Functions + 4, // Start bit position + 4, // End bit position + 1, // Hardwired to 1b + READ_ONLY, // Attribute is Read-only + "SR CL value mismatch", // Capabilities List invalid configured value + "SR CL attribute mismatch" // Capabilities List invalid attribute + }, + + // Bit-field entry 9: Status register, bit[5] = 66 MHz Capable + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x06, // Offset from ECAM base + PCIe_ALL, // Applicable to all PCIe Functions + 5, // Start bit position + 5, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "SR 66MHz capable value mismatch", // 66MHz Capable invalid configured value + "SR 66MHz capable attribute mismatch" // 66MHz Capable invalid attribute + }, + + // Bit-field entry 10: Status register, bit[7] = Fast Back-to-Back Transactions Capable + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x06, // Offset from ECAM base + PCIe_ALL, // Applicable to all PCIe Functions + 7, // Start bit position + 7, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "SR FBBTC value mismatch", // FBBTC invalid configured value + "SR FBBTC attribute mismatch" // FBBTC invalid attribute + }, + + // Bit-field entry 11: Status register, bit[9:10] = DEVSEL timing + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x06, // Offset from ECAM base + PCIe_ALL, // Applicable to all PCIe Functions + 9, // Start bit position + 10, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "SR DT value mismatch", // DEVSEL Timing invalid configured value + "SR DT attribute mismatch" // DEVSEL Timing invalid attribute + }, + + // Bit-field entry 12: Latency Timer register, bit[0:7] = latency timer register + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x0D, // Offset from ECAM base + PCIe_ALL, // Applicable to all PCIe Functions + 0, // Start bit position + 7, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "LTR value mismatch", // Latency Timer invalid configured value + "LTR attribute mismatch" // Latency Timer invalid attribute + }, + +}; diff --git a/test_pool/pcie/test_p021.c b/test_pool/pcie/test_p021.c new file mode 100644 index 00000000..39ff953b --- /dev/null +++ b/test_pool/pcie/test_p021.c @@ -0,0 +1,67 @@ +/** @file + * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "test_p021_data.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 21) +#define TEST_DESC "Check Type 0 config header rules " + +static +void +payload(void) +{ + + uint32_t pe_index; + uint32_t ret; + uint32_t table_entries; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + table_entries = sizeof(bf_info_table21)/sizeof(bf_info_table21[0]); + ret = val_pcie_register_bitfields_check((void *)&bf_info_table21, table_entries); + + if (ret == AVS_STATUS_SKIP) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else if (ret) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, ret)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + +} + +uint32_t +p021_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p021_data.h b/test_pool/pcie/test_p021_data.h new file mode 100644 index 00000000..8c938f16 --- /dev/null +++ b/test_pool/pcie/test_p021_data.h @@ -0,0 +1,71 @@ +/** @file + * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_pcie.h" + +/** +* The test table covers bit-field entries for registers +* which are applicable for only type0 header +**/ + +pcie_cfgreg_bitfield_entry bf_info_table21[] = { + + // Bit-field entry 1: CardBus CIS Pointer, bit[0:31] = cardbus cis pointer + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x28, // Offset from ECAM base + (RCiEP | RCEC | iEP_EP), // Applicable to Endpoints and RCEC Functions + 0, // Start bit position + 31, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "CCP value mismatch", // CardBus CIS pointer invalid configured value + "CCP attribute mismatch" // CardBus CIS pointer invalid attribute + }, + + // Bit-field entry 2: Min Grant, bit[0:7] = Min Gnt + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x3E, // Offset from ECAM base + (RCiEP | RCEC | EP | iEP_EP), // Applicable to Endpoints and RCEC Functions + 0, // Start bit position + 7, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "MinGnt value mismatch", // MinGnt invalid configured value + "MinGnt attribute mismatch" // MinGnt invalid attribute + }, + + // Bit-field entry 3: Max Latency, bit[0:7] = Max latency + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x3F, // Offset from ECAM base + (RCiEP | RCEC | EP | iEP_EP), // Applicable to Endpoints and RCEC Functions + 0, // Start bit position + 7, // End bit position + 0, // Hardwired to 0b + RSVDP_RO, // Attribute is Read-only + "Max latency value mismatch", // Max latency invalid configured value + "Max latency attribute mismatch" // Max latency invalid attribute + }, +}; diff --git a/test_pool/pcie/test_p022.c b/test_pool/pcie/test_p022.c new file mode 100644 index 00000000..81af76a6 --- /dev/null +++ b/test_pool/pcie/test_p022.c @@ -0,0 +1,67 @@ +/** @file + * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "test_p022_data.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 22) +#define TEST_DESC "Check Type 1 config header rules " + +static +void +payload(void) +{ + + uint32_t pe_index; + uint32_t ret; + uint32_t table_entries; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + table_entries = sizeof(bf_info_table22)/sizeof(bf_info_table22[0]); + ret = val_pcie_register_bitfields_check((void *)&bf_info_table22, table_entries); + + if (ret == AVS_STATUS_SKIP) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else if (ret) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, ret)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + +} + +uint32_t +p022_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p022_data.h b/test_pool/pcie/test_p022_data.h new file mode 100644 index 00000000..9d55f9d8 --- /dev/null +++ b/test_pool/pcie/test_p022_data.h @@ -0,0 +1,176 @@ +/** @file + * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_pcie.h" + +/** +* The test table covers bit-field entries for registers +* which are applicable only for type1 header +**/ + +pcie_cfgreg_bitfield_entry bf_info_table22[] = { + + // Bit-field entry 1: Secondary Latency Timer, bit[0:7] + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x1B, // Offset from ECAM base + (RP | iEP_RP), // Applicable to Rootports + 0, // Start bit position + 7, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "SLT value mismatch", // SLT invalid configured value + "SLT attribute mismatch" // SLT invalid attribute + }, + + // Bit-field entry 2: Secondary Status Register, bit[5] 66 Mhz capable + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x1E, // Offset from ECAM base + (RP | iEP_RP), // Applicable to Rootports + 5, // Start bit position + 5, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "SSR 66Mhz value mismatch", // SSR 66Mhz invalid configured value + "SSR 66Mhz attribute mismatch" // SSR 66Mhz invalid attribute + }, + + // Bit-field entry 3: Secondary Status Register, bit[7] Fast Back-to-back transactions capable + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x1E, // Offset from ECAM base + (RP | iEP_RP), // Applicable to Rootports + 7, // Start bit position + 7, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "SSR FBBTC value mismatch", // SSR FBBTC invalid configured value + "SSR FBBTC attribute mismatch" // SSR FBBTC invalid attribute + }, + + // Bit-field entry 4: Secondary Status Register, bit[9:10] DEVSEL timing + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x1E, // Offset from ECAM base + (RP | iEP_RP), // Applicable to Rootports + 9, // Start bit position + 10, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "SSR DEVSEL value mismatch", // DEVSEL Timing invalid configured value + "SSR DEVSEL attribute mismatch" // DEVSEL Timing invalid attribute + }, + + // Bit-field entry 5: Bridge Control Register, bit[5] Master Abort Mode + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x3E, // Offset from ECAM base + (RP | iEP_RP), // Applicable to Rootports + 5, // Start bit position + 5, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "BCR MAM value mismatch", // MAM invalid configured value + "BCR MAM attribute mismatch" // MAM invalid attribute + }, + + // Bit-field entry 6: Bridge Control Register, bit[7] Fast Back-to-Back Transactions Enable + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x3E, // Offset from ECAM base + (RP | iEP_RP), // Applicable to Rootports + 7, // Start bit position + 7, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "BCR FBBTE value mismatch", // FBBTE invalid configured value + "BCR FBBTE attribute mismatch" // FBBTE invalid attribute + }, + + // Bit-field entry 7: Bridge Control Register, bit[8] Primary Discard Timer + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x3E, // Offset from ECAM base + (RP | iEP_RP), // Applicable to Rootports + 8, // Start bit position + 8, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "BCR PDT value mismatch", // PDT invalid configured value + "BCR PDT attribute mismatch" // PDT invalid attribute + }, + + // Bit-field entry 8: Bridge Control Register, bit[9] Secondary Discard Timer + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x3E, // Offset from ECAM base + (RP | iEP_RP), // Applicable to Rootports + 9, // Start bit position + 9, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "BCR SDT value mismatch", // SDT invalid configured value + "BCR SDT attribute mismatch" // SDT invalid attribute + }, + + // Bit-field entry 9: Bridge Control Register, bit[10] Discard Timer Status + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x3E, // Offset from ECAM base + (RP | iEP_RP), // Applicable to Rootports + 10, // Start bit position + 10, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "BCR DTS value mismatch", // DTS invalid configured value + "BCR DTS attribute mismatch" // DTS invalid attribute + }, + + // Bit-field entry 10: Bridge Control Register, bit[11] Discard Timer SERR Enable + { + HEADER, // Part of Header type register + 0, // Not applicable + 0, // Not applicable + 0x3E, // Offset from ECAM base + (RP | iEP_RP), // Applicable to Rootports + 11, // Start bit position + 11, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "BCR DTSE value mismatch", // DTSE invalid configured value + "BCR DTSE attribute mismatch" // DTSE invalid attribute + }, +}; diff --git a/test_pool/pcie/test_p023.c b/test_pool/pcie/test_p023.c new file mode 100644 index 00000000..c4d13384 --- /dev/null +++ b/test_pool/pcie/test_p023.c @@ -0,0 +1,67 @@ +/** @file + * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "test_p023_data.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 23) +#define TEST_DESC "Check PCIe capability rules " + +static +void +payload(void) +{ + + uint32_t pe_index; + uint32_t ret; + uint32_t table_entries; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + table_entries = sizeof(bf_info_table23)/sizeof(bf_info_table23[0]); + ret = val_pcie_register_bitfields_check((void *)&bf_info_table23, table_entries); + + if (ret == AVS_STATUS_SKIP) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else if (ret) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, ret)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + +} + +uint32_t +p023_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p023_data.h b/test_pool/pcie/test_p023_data.h new file mode 100644 index 00000000..9b71bfde --- /dev/null +++ b/test_pool/pcie/test_p023_data.h @@ -0,0 +1,41 @@ +/** @file + * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_pcie.h" + +/** +* The test table covers bit-field entries for PCIe capabilities register +* belonging to capability id 10h (PCIe capability structure) +**/ + +pcie_cfgreg_bitfield_entry bf_info_table23[] = { + + // Bit-field entry 1: PCI Express Capabilities Register, bit[8] Slot Implemented + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x02, // Offset from capability id base + iEP_RP, // Applicable to Rootports + 8, // Start bit position + 8, // End bit position + 0, // Hardwired to 0b + HW_INIT, // Attribute is HW_INIT + "SI value mismatch", // SI invalid configured value + "SI attribute mismatch" // SI invalid attribute + }, +}; diff --git a/test_pool/pcie/test_p024.c b/test_pool/pcie/test_p024.c new file mode 100644 index 00000000..3a40420c --- /dev/null +++ b/test_pool/pcie/test_p024.c @@ -0,0 +1,67 @@ +/** @file + * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "test_p024_data.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 24) +#define TEST_DESC "Check Device capabilites reg rules" + +static +void +payload(void) +{ + + uint32_t pe_index; + uint32_t ret; + uint32_t table_entries; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + table_entries = sizeof(bf_info_table24)/sizeof(bf_info_table24[0]); + ret = val_pcie_register_bitfields_check((void *)&bf_info_table24, table_entries); + + if (ret == AVS_STATUS_SKIP) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else if (ret) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, ret)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + +} + +uint32_t +p024_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p024_data.h b/test_pool/pcie/test_p024_data.h new file mode 100644 index 00000000..09769f96 --- /dev/null +++ b/test_pool/pcie/test_p024_data.h @@ -0,0 +1,147 @@ +/** @file + * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_pcie.h" + +/** +* The test table covers bit-field entries for device capabilities register +* belonging to capability id 10h (PCIe capability structure) +**/ + +pcie_cfgreg_bitfield_entry bf_info_table24[] = { + + // Bit-field entry 1: Device Capabilities Register, bit[3:4] Phantom Functions Supported + // WARNING + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x04, // Offset from capability id base + (RCEC | RCiEP | iEP_EP | iEP_RP), // Applicable to Endpoints and RCEC Functions + 3, // Start bit position + 4, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "WARNING : PFS value mismatch", // PFS invalid configured value + "WARNING : PFS attribute mismatch" // PFS invalid attribute + }, + + // Bit-field entry 2: Device Capabilities Register, bit[5] Extended tag field support + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x04, // Offset from capability id base + (RCEC | RCiEP | iEP_EP | iEP_RP), // Applicable to Endpoints and RCEC Functions + 5, // Start bit position + 5, // End bit position + 1, // Hardwired to 1b + READ_ONLY, // Attribute is Read-only + "ETFS value mismatch", // ETFS invalid configured value + "ETFS attribute mismatch" // ETFS invalid attribute + }, + + // Bit-field entry 3: Device Capabilities Register, bit[6:8] Endpoint L0S Acceptable Latency + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x04, // Offset from capability id base + (RCEC | RCiEP | iEP_EP | iEP_RP | RP), // Applicable to all onchip peripherals and RCEC + 6, // Start bit position + 8, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "ELAL value mismatch", // ELAL invalid configured value + "ELAL attribute mismatch" // ELAL invalid attribute + }, + + // Bit-field entry 4: Device Capabilities Register, bit[9:11] Endpoint L1 Acceptable Latency + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x04, // Offset from capability id base + (RCEC | RCiEP | iEP_EP | iEP_RP | RP), // Applicable to all onchip peripherals and RCEC + 9, // Start bit position + 11, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "ELAL value mismatch", // ELAL invalid configured value + "ELAL attribute mismatch" // ELAL invalid attribute + }, + + // Bit-field entry 5: Device Capabilities Register, bit[15] Role based error reporting + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x04, // Offset from capability id base + (RCEC | RCiEP | iEP_EP | iEP_RP), // Applicable to all onchip peripherals + 15, // Start bit position + 15, // End bit position + 1, // Hardwired to 1b + READ_ONLY, // Attribute is Read-only + "RBER value mismatch", // RBER invalid configured value + "RBER attribute mismatch" // RBER invalid attribute + }, + + // Bit-field entry 6: Device Capabilities Register, bit[18:25] Captured Slot Power Limit Value + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x04, // Offset from capability id base + (RCEC | RCiEP | iEP_EP | iEP_RP), // Applicable to all onchip peripherals + 18, // Start bit position + 25, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "CSPLV value mismatch", // CSPLV invalid configured value + "CSPLV attribute mismatch" // CSPLV invalid attribute + }, + + // Bit-field entry 7: Device Capabilities Register, bit[26:27] Captured Slot Power Limit Scale + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x04, // Offset from capability id base + (RCEC | RCiEP | iEP_EP | iEP_RP), // Applicable to all onchip peripherals + 26, // Start bit position + 27, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "CSPLS value mismatch", // CSPLS invalid configured value + "CSPLS attribute mismatch" // CSPLS invalid attribute + }, + + // Bit-field entry 8: Device Capabilities Register, bit[28] Functions Level Reset Capability + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x04, // Offset from capability id base + (iEP_RP | RP), // Applicable to Rootports + 28, // Start bit position + 28, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "FLRC value mismatch", // FLRC invalid configured value + "FLRC attribute mismatch" // FLRC invalid attribute + }, +}; diff --git a/test_pool/pcie/test_p025.c b/test_pool/pcie/test_p025.c new file mode 100644 index 00000000..663baefd --- /dev/null +++ b/test_pool/pcie/test_p025.c @@ -0,0 +1,67 @@ +/** @file + * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "test_p025_data.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 25) +#define TEST_DESC "Check Device Control register rule" + +static +void +payload(void) +{ + + uint32_t pe_index; + uint32_t ret; + uint32_t table_entries; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + table_entries = sizeof(bf_info_table25)/sizeof(bf_info_table25[0]); + ret = val_pcie_register_bitfields_check((void *)&bf_info_table25, table_entries); + + if (ret == AVS_STATUS_SKIP) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else if (ret) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, ret)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + +} + +uint32_t +p025_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p025_data.h b/test_pool/pcie/test_p025_data.h new file mode 100644 index 00000000..97115365 --- /dev/null +++ b/test_pool/pcie/test_p025_data.h @@ -0,0 +1,88 @@ +/** @file + * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_pcie.h" + +/** +* The test table covers bit-field entries for device control register +* belonging to capability id 10h (PCIe capability structure) +**/ + +pcie_cfgreg_bitfield_entry bf_info_table25[] = { + + // Bit-field entry 1: Device Control Register, bit[9] Phantom Functions Enable + // WARNING + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x08, // Offset from capability id base + (RCEC | RCiEP | iEP_EP | iEP_RP), // Applicable to onchip peripherals + 9, // Start bit position + 9, // End bit position + 0, // Hardwired to 0b + READ_WRITE, // Attribute is Read-Write + "WARNING PFE value mismatch", // PFE invalid configured value + "WARNING PFE attribute mismatch" // PFE invalid attribute + }, + + // Bit-field entry 2: Device Control Register, bit[10] Aux power PM Enable + // WARNING + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x08, // Offset from capability id base + (RCEC | RCiEP | iEP_EP | iEP_RP), // Applicable to onchip peripherals + 10, // Start bit position + 10, // End bit position + 0, // Hardwired to 0b + STICKY_RW, // Attribute is Read-Write + "WARNING APPE value mismatch", // APPE invalid configured value + "WARNING APPE attribute mismatch" // APPE invalid attribute + }, + + // Bit-field entry 3: Device Control Register, bit[11] Enable No Snoop + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x08, // Offset from capability id base + RCEC, // Applicable to RCEC + 11, // Start bit position + 11, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-Only + "ENS value mismatch", // ENS invalid configured value + "ENS attribute mismatch" // ENS invalid attribute + }, + + // Bit-field entry 4: Device Control Register, bit[15] Initiate FLR + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x08, // Offset from capability id base + (iEP_RP | RP), // Applicable to Rootports + 15, // Start bit position + 15, // End bit position + 0, // Hardwired to 0b + RSVDP_RO, // Attribute is rsvdp + "IFLR value mismatch", // IFLR invalid configured value + "IFLR attribute mismatch" // IFLR invalid attribute + }, +}; diff --git a/test_pool/pcie/test_p026.c b/test_pool/pcie/test_p026.c new file mode 100644 index 00000000..858d2722 --- /dev/null +++ b/test_pool/pcie/test_p026.c @@ -0,0 +1,67 @@ +/** @file + * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "test_p026_data.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 26) +#define TEST_DESC "Check Device cap 2 register rules " + +static +void +payload(void) +{ + + uint32_t pe_index; + uint32_t ret; + uint32_t table_entries; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + table_entries = sizeof(bf_info_table26)/sizeof(bf_info_table26[0]); + ret = val_pcie_register_bitfields_check((void *)&bf_info_table26, table_entries); + + if (ret == AVS_STATUS_SKIP) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else if (ret) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, ret)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + +} + +uint32_t +p026_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p026_data.h b/test_pool/pcie/test_p026_data.h new file mode 100644 index 00000000..5971c38d --- /dev/null +++ b/test_pool/pcie/test_p026_data.h @@ -0,0 +1,274 @@ +/** @file + * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_pcie.h" + +/** +* The test table covers bit-field entries for device capabilities 2 register +* belonging to capability id 10h (PCIe capability structure) +**/ + +pcie_cfgreg_bitfield_entry bf_info_table26[] = { + + // Bit-field entry 1: Device Capabilities Register 2, bit[5] ARI Forwarding Support + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x24, // Offset from capability id base + (RCEC | RCiEP | iEP_EP | EP), // Applicable to Endpoints, RCEC and RCiEP + 5, // Start bit position + 5, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "AFS value mismatch", // AFS invalid configured value + "AFS attribute mismatch" // AFS invalid attribute + }, + + // Bit-field entry 2: Device Capabilities Register 2, bit[5] ARI Forwarding Support + // WARNING + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x24, // Offset from capability id base + iEP_RP, // Applicable to iEP_RP + 5, // Start bit position + 5, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "WARNING AFS value mismatch", // AFS invalid configured value + "WARNING AFS attribute mismatch" // AFS invalid attribute + }, + + // Bit-field entry 3: Device Capabilities Register 2, bit[6] AtomicOp Routing Supported + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x24, // Offset from capability id base + (RCEC | RCiEP | iEP_EP), // Applicable to integrated Endpoints, RCEC + 6, // Start bit position + 6, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "ARS value mismatch", // ARS invalid configured value + "ARS attribute mismatch" // ARS invalid attribute + }, + + // Bit-field entry 4: Device Capabilities Register 2, bit[6] AtomicOp Routing Supported + // WARNING + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x24, // Offset from capability id base + iEP_RP, // Applicable to iEP_RP + 6, // Start bit position + 6, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is Read-only + "WARNING ARS value mismatch", // ARS invalid configured value + "WARNING ARS attribute mismatch" // ARS invalid attribute + }, + + // Bit-field entry 5: Device Capabilities Register 2, bit[10] No RO-enabled PR-PR passing + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x24, // Offset from capability id base + (RCEC | RCiEP | iEP_EP | EP), // Applicable to integrated endpoint pair + 10, // Start bit position + 10, // End bit position + 0, // Hardwired to 0b + HW_INIT, // Attribute is HW INIT + "NREPP value mismatch", // NREPP invalid configured value + "NREPP attribute mismatch" // NREPP invalid attribute + }, + + + // Bit-field entry 6: Device Capabilities Register 2, bit[14:15] LN System CLS + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x24, // Offset from capability id base + (RCiEP | iEP_EP | EP), // Applicable to RCiEP, iEP_EP and EP + 14, // Start bit position + 15, // End bit position + 0, // Hardwired to 0b + HW_INIT, // Attribute is HW INIT + "LSC value mismatch", // LSC invalid configured value + "LSC attribute mismatch" // LSC invalid attribute + }, + + // Bit-field entry 7: Device Capabilities Register 2, bit[16] 10-bit tag completer supported + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x24, // Offset from capability id base + iEP_RP, // Applicable to iEP_RP + 16, // Start bit position + 16, // End bit position + 1, // Hardwired to 1b + HW_INIT, // Attribute is HW INIT + "TCS value mismatch", // TCS invalid configured value + "TCS attribute mismatch" // TCS invalid attribute + }, + + // Bit-field entry 8: Device Capabilities Register 2, bit[17] 10-bit tag requester supported + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x24, // Offset from capability id base + (iEP_RP | iEP_EP), // Applicable to integrated pair + 17, // Start bit position + 17, // End bit position + 1, // Hardwired to 1b + HW_INIT, // Attribute is HW INIT + "TRS value mismatch", // TRS invalid configured value + "TRS attribute mismatch" // TRS invalid attribute + }, + + // Bit-field entry 9: Device Capabilities Register 2, bit[20] Extended Fmt Field Supported + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x24, // Offset from capability id base + (iEP_RP | iEP_EP), // Applicable to integrated pair + 20, // Start bit position + 20, // End bit position + 1, // Hardwired to 1b + READ_ONLY, // Attribute is READ_ONLY + "EFFS value mismatch", // EFFS invalid configured value + "EFFS attribute mismatch" // EFFS invalid attribute + }, + + // Bit-field entry 10: Device Capabilities Register 2, bit[20] Extended Fmt Field Supported + // WARNING + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x24, // Offset from capability id base + (RCiEP | RCEC), // Applicable to RCEC and RCiEP + 20, // Start bit position + 20, // End bit position + 1, // Hardwired to 1b + READ_ONLY, // Attribute is READ_ONLY + "WARNING EFFS value mismatch", // EFFS invalid configured value + "WARNING EFFS attribute mismatch" // EFFS invalid attribute + }, + + // Bit-field entry 11: Device Capabilities Register 2, bit[21] End-End TLP Prefix Supported + // WARNING + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x24, // Offset from capability id base + RCEC, // Applicable to RCEC + 21, // Start bit position + 21, // End bit position + 0, // Hardwired to 0b + HW_INIT, // Attribute is HW_INIT + "WARNING ETPS value mismatch", // ETPS invalid configured value + "WARNING ETPS attribute mismatch" // ETPS invalid attribute + }, + + // Bit-field entry 12: Device Capabilities Register 2, bit[22:23] Max End-End TLP Prefixes + // WARNING + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x24, // Offset from capability id base + RCEC, // Applicable to RCEC + 22, // Start bit position + 23, // End bit position + 0, // Hardwired to 0b + RSVDP_RO, // Attribute is RSVDP + "WARNING METP value mismatch", // METP invalid configured value + "WARNING METP attribute mismatch" // METP invalid attribute + }, + + // Bit-field entry 13: Device Cap Register 2, bit[24:25] Emergency power reduction supported + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x24, // Offset from capability id base + iEP_RP, // Applicable to iEP_RP + 24, // Start bit position + 25, // End bit position + 0, // Hardwired to 0b + RSVDP_RO, // Attribute is RSVDP + "EPRS value mismatch", // EPRS invalid configured value + "EPRS attribute mismatch" // EPRS invalid attribute + }, + + // Bit-field entry 14: Device Cap Register 2, bit[24:25] Emergency power reduction supported + // WARNING + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x24, // Offset from capability id base + iEP_EP, // Applicable to iEP_EP + 24, // Start bit position + 25, // End bit position + 0, // Hardwired to 0b + RSVDP_RO, // Attribute is RSVDP + "WARNING EPRS value mismatch", // EPRS invalid configured value + "WARNING EPRS attribute mismatch" // EPRS invalid attribute + }, + + // Bit-field entry 15: Device Cap Register 2, bit[26] Emergency power reduction init required + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x24, // Offset from capability id base + iEP_RP, // Applicable to iEP_RP + 26, // Start bit position + 26, // End bit position + 0, // Hardwired to 0b + RSVDP_RO, // Attribute is RSVDP + "EPRIR value mismatch", // EPRIR invalid configured value + "EPRIR attribute mismatch" // EPRIR invalid attribute + }, + + // Bit-field entry 16: Device Cap Register 2, bit[26] Emergency power reduction init required + // WARNING + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x24, // Offset from capability id base + iEP_EP, // Applicable to iEP_EP + 26, // Start bit position + 26, // End bit position + 0, // Hardwired to 0b + RSVDP_RO, // Attribute is RSVDP + "WARNING EPRIR value mismatch", // EPRIR invalid configured value + "WARNING EPRIR attribute mismatch" // EPRIR invalid attribute + }, +}; diff --git a/test_pool/pcie/test_p027.c b/test_pool/pcie/test_p027.c new file mode 100644 index 00000000..0004be71 --- /dev/null +++ b/test_pool/pcie/test_p027.c @@ -0,0 +1,67 @@ +/** @file + * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "test_p027_data.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 27) +#define TEST_DESC "Check Device control 2 reg rules " + +static +void +payload(void) +{ + + uint32_t pe_index; + uint32_t ret; + uint32_t table_entries; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + table_entries = sizeof(bf_info_table27)/sizeof(bf_info_table27[0]); + ret = val_pcie_register_bitfields_check((void *)&bf_info_table27, table_entries); + + if (ret == AVS_STATUS_SKIP) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else if (ret) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, ret)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + +} + +uint32_t +p027_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p027_data.h b/test_pool/pcie/test_p027_data.h new file mode 100644 index 00000000..fba3c4c0 --- /dev/null +++ b/test_pool/pcie/test_p027_data.h @@ -0,0 +1,101 @@ +/** @file + * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_pcie.h" + +/** +* The test table covers bit-field entries for device control 2 register +* belonging to capability id 10h (PCIe capability structure) +**/ + +pcie_cfgreg_bitfield_entry bf_info_table27[] = { + + // Bit-field entry 1: Device Control Register 2, bit[5] ARI Forwarding Enable + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x28, // Offset from capability id base + (RCEC | RCiEP | iEP_EP), // Applicable to RCEC, RCiEP and iEP_EP + 5, // Start bit position + 5, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is READ_ONLY + "AFI value mismatch", // AFE invalid configured value + "AFI attribute mismatch" // AFE invalid attribute + }, + + // Bit-field entry 2: Device Control Register 2, bit[7] Atomicop Egress Blocking + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x28, // Offset from capability id base + (RCEC | RCiEP | iEP_EP), // Applicable to RCEC, RCiEP and iEP_EP + 7, // Start bit position + 7, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is READ_ONLY + "AEB value mismatch", // AEB invalid configured value + "AEB attribute mismatch" // AEB invalid attribute + }, + + // Bit-field entry 3: Device Control Register 2, bit[8] IDO request Enable + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x28, // Offset from capability id base + RCEC, // Applicable to RCEC + 8, // Start bit position + 8, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is READ_ONLY + "IRE value mismatch", // IRE invalid configured value + "IRE attribute mismatch" // IRE invalid attribute + }, + + // Bit-field entry 4: Device Control Register 2, bit[9] IDO Completer Enable + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x28, // Offset from capability id base + RCEC, // Applicable to RCEC + 9, // Start bit position + 9, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is READ_ONLY + "ICE value mismatch", // ICE invalid configured value + "ICE attribute mismatch" // ICE invalid attribute + }, + + // Bit-field entry 5: Device Control Register 2, bit[11] Emergency Power Reduction request + { + PCIE_CAP, // Part of PCIe capability register + 0x10, // Capability id + 0, // Not applicable + 0x28, // Offset from capability id base + (RCEC | RCiEP | iEP_RP | iEP_EP), // Applicable to RCEC, RCiEP, iEP_RP, iEP_EP + 11, // Start bit position + 11, // End bit position + 0, // Hardwired to 0b + RSVDP_RO, // Attribute is RSDVP + "EPPR value mismatch", // EPPR invalid configured value + "EPPR attribute mismatch" // EPPR invalid attribute + }, +}; diff --git a/test_pool/pcie/test_p028.c b/test_pool/pcie/test_p028.c new file mode 100644 index 00000000..b53b1f4a --- /dev/null +++ b/test_pool/pcie/test_p028.c @@ -0,0 +1,67 @@ +/** @file + * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "test_p028_data.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 28) +#define TEST_DESC "Check Power management cap rules " + +static +void +payload(void) +{ + + uint32_t pe_index; + uint32_t ret; + uint32_t table_entries; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + table_entries = sizeof(bf_info_table28)/sizeof(bf_info_table28[0]); + ret = val_pcie_register_bitfields_check((void *)&bf_info_table28, table_entries); + + if (ret == AVS_STATUS_SKIP) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else if (ret) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, ret)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + +} + +uint32_t +p028_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p028_data.h b/test_pool/pcie/test_p028_data.h new file mode 100644 index 00000000..1eaf06b4 --- /dev/null +++ b/test_pool/pcie/test_p028_data.h @@ -0,0 +1,57 @@ +/** @file + * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_pcie.h" + +/** +* The test table covers bit-field entries for power management capabilities +* register belonging to capability id 01h (PCI power management capability +* structure) +**/ + +pcie_cfgreg_bitfield_entry bf_info_table28[] = { + + // Bit-field entry 1: Power Management Capabilities Register, bit[19] PME Clock + { + PCIE_CAP, // Part of PCIe capability register + 0x01, // Capability id + 0, // Not applicable + 0, // Offset from capability id base + PCIe_ALL, // Applicable to all PCIe devices + 19, // Start bit position + 19, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is READ_ONLY + "PME Clock value mismatch", // PME Clock invalid configured value + "PME Clock attribute mismatch" // PME Clock invalid attribute + }, + + // Bit-field entry 2: Power Management Capabilities Register, bit[22:24] Aux Current + { + PCIE_CAP, // Part of PCIe capability register + 0x01, // Capability id + 0, // Not applicable + 0, // Offset from capability id base + (RCiEP | RCEC | iEP_EP | iEP_RP), // Applicable to onchip peripherals + 22, // Start bit position + 24, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is READ_ONLY + "Aux Current value mismatch", // Aux Current invalid configured value + "Aux Current attribute mismatch" // Aux Current invalid attribute + }, +}; diff --git a/test_pool/pcie/test_p029.c b/test_pool/pcie/test_p029.c new file mode 100644 index 00000000..e6b09c9b --- /dev/null +++ b/test_pool/pcie/test_p029.c @@ -0,0 +1,67 @@ +/** @file + * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "test_p029_data.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 29) +#define TEST_DESC "Check Power management/status rule" + +static +void +payload(void) +{ + + uint32_t pe_index; + uint32_t ret; + uint32_t table_entries; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + table_entries = sizeof(bf_info_table29)/sizeof(bf_info_table29[0]); + ret = val_pcie_register_bitfields_check((void *)&bf_info_table29, table_entries); + + if (ret == AVS_STATUS_SKIP) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else if (ret) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, ret)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + +} + +uint32_t +p029_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p029_data.h b/test_pool/pcie/test_p029_data.h new file mode 100644 index 00000000..9f398e4f --- /dev/null +++ b/test_pool/pcie/test_p029_data.h @@ -0,0 +1,59 @@ +/** @file + * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_pcie.h" + +/** +* The test table covers bit-field entries for power management control/status +* register belonging to capability id 01h (PCI power management capability +* structure) +**/ + +pcie_cfgreg_bitfield_entry bf_info_table29[] = { + + // Bit-field entry 1: Power Management Capabilities/Status Register, bit[9:12] Data Select + // WARNING + { + PCIE_CAP, // Part of PCIe capability register + 0x01, // Capability id + 0, // Not applicable + 0x04, // Offset from capability id base + (RCiEP | RCEC | iEP_EP | iEP_RP), // Applicable to onchip peripherals + 9, // Start bit position + 12, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is READ_ONLY + "WARNING Data Select value mismatch", // Data Select invalid configured value + "WARNING Data Select attribute mismatch" // Data Select invalid attribute + }, + + // Bit-field entry 2: Power Management Capabilities/Status Register, bit[13:14] Data Scale + // WARNING + { + PCIE_CAP, // Part of PCIe capability register + 0x01, // Capability id + 0, // Not applicable + 0x04, // Offset from capability id base + (RCiEP | RCEC | iEP_EP | iEP_RP), // Applicable to onchip peripherals + 13, // Start bit position + 14, // End bit position + 0, // Hardwired to 0b + READ_ONLY, // Attribute is READ_ONLY + "WARNING Data Scale value mismatch", // Data Scale invalid configured value + "WARNING Data Scale attribute mismatch" // Data Scale invalid attribute + }, +}; diff --git a/test_pool/pcie/test_p030.c b/test_pool/pcie/test_p030.c new file mode 100644 index 00000000..ebc7db07 --- /dev/null +++ b/test_pool/pcie/test_p030.c @@ -0,0 +1,166 @@ +/** @file + * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 30) +#define TEST_DESC "Check Cmd Reg memory space enable " + +static void *branch_to_test; + +static +void +esr(uint64_t interrupt_type, void *context) +{ + uint32_t pe_index; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + /* Update the ELR to return to test specified address */ + val_pe_update_elr(context, (uint64_t)branch_to_test); + + val_print(AVS_PRINT_INFO, "\n Received exception of type: %d", interrupt_type); + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t dsf_bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t bar_data; + uint32_t test_fails; + uint64_t bar_base; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + /* Install sync and async handlers to handle exceptions.*/ + val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr); + val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); + branch_to_test = &&exception_return; + + bar_data = 0; + tbl_index = 0; + test_fails = 0; + + while (tbl_index < bdf_tbl_ptr->num_entries) + { + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + + /* + * For a Function with type 0 config space header, obtain + * base address of its Memory mapped BAR. For Function with + * Type 1 config space header, obtain base address of the + * downstream function memory mapped BAR. If there is no + * downstream Function exist, obtain its own BAR address. + */ + if ((val_pcie_function_header_type(bdf) == TYPE1_HEADER) && + (!val_pcie_get_downstream_function(bdf, &dsf_bdf))) + val_pcie_get_mmio_bar(dsf_bdf, &bar_base); + else + val_pcie_get_mmio_bar(bdf, &bar_base); + + /* Skip this function if it doesn't have mmio BAR */ + if (!bar_base) + continue; + + /* Disable error reporting of this function to the Upstream */ + val_pcie_disable_eru(bdf); + + /* + * Clear unsupported request detected bit in Device + * Status Register to clear any pending urd status. + */ + val_pcie_clear_urd(bdf); + + /* + * Disable BAR memory space access to cause address + * decode failures. With memory space aceess disable, + * all received memory space accesses are handled as + * Unsupported Requests by the pcie function. + */ + val_pcie_disable_msa(bdf); + + /* Set test status as FAIL, update to PASS in exception handler */ + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + + /* + * Read memory mapped BAR to cause unsupported request + * detected bit set in Device Status Register of the pcie + * Function. Based on platform configuration, this may + * even cause an sync/async exception. + */ + bar_data = val_mmio_read((addr_t)(bar_base)); + +exception_return: + /* + * Check if unsupported request detected bit isn't set + * and if either of UR response or abort isn't received. + */ + if ((val_pcie_is_urd(bdf)) && + (IS_TEST_PASS(val_get_status(pe_index)) || (bar_data == PCIE_UNKNOWN_RESPONSE))) + { + /* Clear urd bit in Device Status Register */ + val_pcie_clear_urd(bdf); + } else + { + val_print(AVS_PRINT_ERR, "\n BDF %x MSE functionality failure", bdf); + test_fails++; + } + + /* Enable memory space access to decode BAR addresses */ + val_pcie_enable_msa(bdf); + + /* Reset the loop variables */ + bar_data = 0; + } + + if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p030_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p031.c b/test_pool/pcie/test_p031.c new file mode 100644 index 00000000..8de94ce9 --- /dev/null +++ b/test_pool/pcie/test_p031.c @@ -0,0 +1,92 @@ +/** @file + * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 31) +#define TEST_DESC "Check Type0/1 BIST Register rule " + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t reg_value; + uint32_t test_fails; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + tbl_index = 0; + test_fails = 0; + + while (tbl_index < bdf_tbl_ptr->num_entries) + { + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + + /* Read 32-bits from Cache Line Size register offset */ + val_pcie_read_cfg(bdf, TYPE01_CLSR, ®_value); + + /* Extract BIST register value */ + reg_value = VAL_EXTRACT_BITS(reg_value, BIST_REG_START, BIST_REG_END); + + /* + * If BIST Capable bit[7] is clear Completion Code[0:3] and Start Bist[6] + * must be hardwired to 0b + */ + if (((reg_value & BIST_BC_MASK) == 0x00) && + (((reg_value & BIST_CC_MASK) != 0x00) || ((reg_value & BIST_SB_MASK) != 0x00))) + { + val_print(AVS_PRINT_ERR, "\n BDF 0x%x", bdf); + val_print(AVS_PRINT_ERR, " BIST Reg Value : %d", reg_value); + test_fails++; + } + } + + if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p031_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p032.c b/test_pool/pcie/test_p032.c new file mode 100644 index 00000000..6f7b16ea --- /dev/null +++ b/test_pool/pcie/test_p032.c @@ -0,0 +1,89 @@ +/** @file + * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 32) +#define TEST_DESC "Check HDR CapPtr Register rule " + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t reg_value; + uint32_t cap_ptr_value; + uint32_t test_fails; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + tbl_index = 0; + test_fails = 0; + + while (tbl_index < bdf_tbl_ptr->num_entries) + { + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + + /* Read 32-bits from Capabilities pointer register offset */ + val_pcie_read_cfg(bdf, TYPE01_CPR, ®_value); + + /* Extract Capabilities Pointer register value */ + cap_ptr_value = (reg_value >> TYPE01_CPR_SHIFT) & TYPE01_CPR_MASK; + + /* Check Capabilities Pointer is not NULL and is between 40h and FCh */ + if (!((cap_ptr_value != 0x00) && ((cap_ptr_value >= 0x40) && (cap_ptr_value <= 0xFC)))) + { + val_print(AVS_PRINT_ERR, "\n BDF 0x%x", bdf); + val_print(AVS_PRINT_ERR, " Cap Ptr Value: 0x%x", cap_ptr_value); + test_fails++; + } + } + + if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p032_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p033.c b/test_pool/pcie/test_p033.c new file mode 100644 index 00000000..76a2a823 --- /dev/null +++ b/test_pool/pcie/test_p033.c @@ -0,0 +1,93 @@ +/** @file + * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 33) +#define TEST_DESC "Check Max payload size supported " + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t reg_value; + uint32_t max_payload_value; + uint32_t test_fails; + uint32_t cap_base; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + tbl_index = 0; + test_fails = 0; + + while (tbl_index < bdf_tbl_ptr->num_entries) + { + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + + /* Retrieve the addr of PCI express capability (10h) */ + val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cap_base); + + /* Read Device Capabilities register(04h) present in PCIE capability struct(10h) */ + val_pcie_read_cfg(bdf, cap_base + DCAPR_OFFSET, ®_value); + + /* Extract Max payload Size Supported value */ + max_payload_value = (reg_value >> DCAPR_MPSS_SHIFT) & DCAPR_MPSS_MASK; + + /* Valid payload size between 000b (129-bytes) to 101b (4096 bytes) */ + if (!((max_payload_value >= 0x00) && (max_payload_value <= 0x05))) + { + val_print(AVS_PRINT_ERR, "\n BDF 0x%x", bdf); + val_print(AVS_PRINT_ERR, " Cap Ptr Value: 0x%x", max_payload_value); + test_fails++; + } + } + + if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p033_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p034.c b/test_pool/pcie/test_p034.c new file mode 100644 index 00000000..eaa313d0 --- /dev/null +++ b/test_pool/pcie/test_p034.c @@ -0,0 +1,130 @@ +/** @file + * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 34) +#define TEST_DESC "Check BAR memory space & Type rule" + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t reg_value; + uint32_t hdr_type; + uint32_t max_bar; + uint32_t addr_type; + uint32_t bar_index; + uint32_t dp_type; + uint32_t test_fails; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + tbl_index = 0; + test_fails = 0; + + /* Check for all the function present in bdf table */ + while (tbl_index < bdf_tbl_ptr->num_entries) + { + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + dp_type = val_pcie_device_port_type(bdf); + + /* Check for RCiEP and iEP */ + if (dp_type == RCiEP || dp_type == iEP_EP) + { + /* Read 32-bits from CacheLine Size regsiter offset */ + val_pcie_read_cfg(bdf, TYPE01_CLSR, ®_value); + + /* Extract Hdr Type */ + hdr_type = (reg_value >> TYPE01_HTR_SHIFT) & TYPE01_HTR_MASK; + val_print(AVS_PRINT_INFO, "\n HDR TYPE 0x%x ", hdr_type); + + max_bar = 0; + /* For Type0 header max bars 6, type1 header max bars 2 */ + if (hdr_type == TYPE0_HEADER) + max_bar = TYPE0_MAX_BARS; + else if (hdr_type == TYPE1_HEADER) + max_bar = TYPE1_MAX_BARS; + val_print(AVS_PRINT_INFO, "\n MAX BARS 0x%x ", max_bar); + + for (bar_index = 0; bar_index < max_bar; bar_index++) + { + /* Read BAR0 register */ + val_pcie_read_cfg(bdf, TYPE01_BAR + (bar_index * BAR_BASE_SHIFT), ®_value); + + /* If BAR not in use skip the BAR */ + if (reg_value == 0) + continue; + + /* Check type[1:2] should be 32-bit or 64-bit */ + addr_type = (reg_value >> BAR_MDT_SHIFT) & BAR_MDT_MASK; + if ((addr_type != BITS_32) && (addr_type != BITS_64)) + { + val_print(AVS_PRINT_ERR, "\n BDF 0x%x ", bdf); + val_print(AVS_PRINT_ERR, " Addr Type: 0x%x", addr_type); + test_fails++; + continue; + } + + /* if BAR is 64 bit move index to next BAR */ + if (addr_type == BITS_64) + bar_index++; + + /* Check BAR should be MMIO */ + if (reg_value & BAR_MIT_MASK) + { + val_print(AVS_PRINT_ERR, "\n BDF 0x%x Not MMIO", 0); + test_fails++; + } + } + } + } + if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p034_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p035.c b/test_pool/pcie/test_p035.c new file mode 100644 index 00000000..c58cb78f --- /dev/null +++ b/test_pool/pcie/test_p035.c @@ -0,0 +1,177 @@ +/** @file + * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 35) +#define TEST_DESC "Check Function level reset rule " + +uint32_t is_flr_failed(uint32_t bdf) +{ + uint32_t reg_value; + uint32_t index; + uint32_t check_failed; + + check_failed = 0; + /* Check BAR base address is cleared */ + for (index = 0; index < TYPE0_MAX_BARS; index++) + { + val_pcie_read_cfg(bdf, TYPE01_BAR + (index * BAR_BASE_SHIFT), ®_value); + if ((reg_value >> BAR_BASE_SHIFT) != 0) + { + val_print(AVS_PRINT_ERR, "\n BAR%d base addr not cleared", 0); + check_failed++; + } + } + + /* Check the Bus Master Enable bit is cleared */ + val_pcie_read_cfg(bdf, TYPE01_CR, ®_value); + if (((reg_value >> CR_BME_SHIFT) & CR_BME_MASK) != 0) + { + val_print(AVS_PRINT_ERR, "\n BME is not cleared", 0); + check_failed++; + } + + /* Check the Memory Space Enable bit is cleared */ + val_pcie_read_cfg(bdf, TYPE01_CR, ®_value); + if (((reg_value >> CR_MSE_SHIFT) & CR_MSE_MASK) != 0) + { + val_print(AVS_PRINT_ERR, "\n MSE is not cleared", 0); + check_failed++; + } + + return check_failed; +} + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t reg_value; + uint32_t dp_type; + uint32_t cap_base; + uint32_t flr_cap; + uint32_t test_fails; + addr_t config_space_addr; + void *func_config_space; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + tbl_index = 0; + test_fails = 0; + + /* Check for all the function present in bdf table */ + while (tbl_index < bdf_tbl_ptr->num_entries) + { + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + dp_type = val_pcie_device_port_type(bdf); + + /* Check entry is RCiEP or iEP endpoint or normal EP */ + if ((dp_type == RCiEP) || (dp_type == iEP_EP) || (dp_type == EP)) + { + /* Read FLR capability bit value */ + val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cap_base); + val_pcie_read_cfg(bdf, cap_base + DCAPR_OFFSET, ®_value); + flr_cap = (reg_value >> DCAPR_FLRC_SHIFT) & DCAPR_FLRC_MASK; + + /* If FLR capability is not set, move to next entry */ + if (!flr_cap) + continue; + + /* Allocate 4KB of space for saving function configuration space */ + func_config_space = NULL; + func_config_space = val_memory_alloc(PCIE_CFG_SIZE); + + /* If memory allocation fail, fail the test */ + if (func_config_space == NULL) + { + val_print(AVS_PRINT_ERR, "\n Memory allocation fail", 0); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + return; + } + + /* Get function configuration space address */ + config_space_addr = val_pcie_get_bdf_config_addr(bdf); + val_print(AVS_PRINT_INFO, "\n BDF 0x%x ", bdf); + val_print(AVS_PRINT_INFO, "config space addr 0x%x", config_space_addr); + + /* Save the function config space to restore after FLR */ + val_memcpy(func_config_space, (void *)config_space_addr, PCIE_CFG_SIZE); + + /* Initiate FLR by setting the FLR bit */ + val_pcie_read_cfg(bdf, cap_base + DCTLR_OFFSET, ®_value); + reg_value = reg_value | DCTLR_FLR_SET; + val_pcie_write_cfg(bdf, cap_base + DCTLR_OFFSET, reg_value); + + /* Wait for 100 ms */ + val_time_delay_ms(100 * ONE_MILLISECOND); + + /* Vendor Id should not be 0xFF after max FLR period */ + val_pcie_read_cfg(bdf, 0, ®_value); + if ((reg_value & TYPE01_VIDR_MASK) == TYPE01_VIDR_MASK) + { + val_print(AVS_PRINT_ERR, "\n BDF 0x%x not present", bdf); + test_fails++; + val_memory_free(func_config_space); + continue; + } + + if (is_flr_failed(bdf)) + test_fails++; + + /* Initialize the function config space */ + val_memcpy((void *)config_space_addr, func_config_space, PCIE_CFG_SIZE); + val_memory_free(func_config_space); + } + } + + if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p035_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p036.c b/test_pool/pcie/test_p036.c new file mode 100644 index 00000000..08c194e3 --- /dev/null +++ b/test_pool/pcie/test_p036.c @@ -0,0 +1,102 @@ +/** @file + * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 36) +#define TEST_DESC "Check ARI forwarding support rule " + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t rp_bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t reg_value; + uint32_t dp_type; + uint32_t cap_base; + uint32_t ari_frwd_support; + uint32_t test_fails; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + test_fails = 0; + + /* Check for all the function present in bdf table */ + for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++) + { + bdf = bdf_tbl_ptr->device[tbl_index].bdf; + dp_type = val_pcie_device_port_type(bdf); + + /* Check entry is iEP */ + if (dp_type == iEP_EP) + { + /* Check ARI capability support */ + if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ARICS, &cap_base) == + PCIE_CAP_NOT_FOUND) + continue; + + /* Get the rootport of ARI device */ + rp_bdf = bdf_tbl_ptr->device[tbl_index].rp_bdf; + + /* Read the ARI forwarding bit */ + val_pcie_find_capability(rp_bdf, PCIE_CAP, CID_PCIECS, &cap_base); + val_pcie_read_cfg(rp_bdf, cap_base + DCAP2R_OFFSET, ®_value); + ari_frwd_support = (reg_value >> DCAP2R_AFS_SHIFT) & DCAP2R_AFS_MASK; + + /* If root port not support ARI forwarding, fail the test */ + if (!ari_frwd_support) + test_fails++; + + } + } + + if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p036_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p037.c b/test_pool/pcie/test_p037.c new file mode 100644 index 00000000..30ba404c --- /dev/null +++ b/test_pool/pcie/test_p037.c @@ -0,0 +1,108 @@ +/** @file + * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 37) +#define TEST_DESC "Check OBFF supported rule " + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t rp_bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t reg_value; + uint32_t dp_type; + uint32_t cap_base; + uint32_t ep_obff_support; + uint32_t rp_obff_support; + uint32_t test_fails; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + test_fails = 0; + + /* Check for all the function present in bdf table */ + for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++) + { + bdf = bdf_tbl_ptr->device[tbl_index].bdf; + dp_type = val_pcie_device_port_type(bdf); + + /* Check entry is iEP endpoint */ + if (dp_type == iEP_EP) + { + /* Read endpoint OBFF supported bit value */ + val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cap_base); + val_pcie_read_cfg(bdf, cap_base + DCAP2R_OFFSET, ®_value); + ep_obff_support = (reg_value >> DCAP2R_OBFF_SHIFT) & DCAP2R_OBFF_MASK; + + /* Get the rootport of ARI device */ + rp_bdf = bdf_tbl_ptr->device[tbl_index].rp_bdf; + + /* Read rootport OBFF supported bit value */ + val_pcie_find_capability(rp_bdf, PCIE_CAP, CID_PCIECS, &cap_base); + val_pcie_read_cfg(rp_bdf, cap_base + DCAP2R_OFFSET, ®_value); + rp_obff_support = (reg_value >> DCAP2R_OBFF_SHIFT) & DCAP2R_OBFF_MASK; + + /* As per SBSA spec iRP must have same value as of iEP */ + if (ep_obff_support != rp_obff_support) + { + val_print(AVS_PRINT_DEBUG, "\n iEP 0x%x", bdf); + val_print(AVS_PRINT_DEBUG, " OBFF support %d", ep_obff_support); + val_print(AVS_PRINT_DEBUG, "\n iRP 0x%x", rp_bdf); + val_print(AVS_PRINT_DEBUG, " OBFF support %d", rp_obff_support); + test_fails++; + } + } + } + + if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p037_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p038.c b/test_pool/pcie/test_p038.c new file mode 100644 index 00000000..9a584cf6 --- /dev/null +++ b/test_pool/pcie/test_p038.c @@ -0,0 +1,108 @@ +/** @file + * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 38) +#define TEST_DESC "Check CTRS and CTDS rule " + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t reg_value; + uint32_t dp_type; + uint32_t cap_base; + uint32_t ctrs_value; + uint32_t ctds_value; + uint32_t test_fails; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + tbl_index = 0; + test_fails = 0; + + /* Check for all the function present in bdf table */ + while (tbl_index < bdf_tbl_ptr->num_entries) + { + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + dp_type = val_pcie_device_port_type(bdf); + + /* Check entry is iRP endpoint */ + if (dp_type == iEP_RP) + { + /* If rootport invovled in transaction forwarding, move to next */ + if (val_pcie_get_rp_transaction_frwd_support(bdf)) + continue; + + /* Read rootport Completion Timeout Ranges supported bit value */ + val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cap_base); + val_pcie_read_cfg(bdf, cap_base + DCAP2R_OFFSET, ®_value); + ctrs_value = (reg_value >> DCAP2R_CTRS_SHIFT) & DCAP2R_CTRS_MASK; + + /* Read rootport Completion Timeout Disable supported bit value */ + val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cap_base); + val_pcie_read_cfg(bdf, cap_base + DCAP2R_OFFSET, ®_value); + ctds_value = (reg_value >> DCAP2R_CTDS_SHIFT) & DCAP2R_CTDS_MASK; + + /* CTRS and CTDS bit is handwired to 0, if transaction forwarding not support */ + if ((ctrs_value != 0) || (ctds_value !=0)) + { + val_print(AVS_PRINT_DEBUG, "\n BDF 0x%x", bdf); + val_print(AVS_PRINT_DEBUG, " ctrs %d", ctrs_value); + val_print(AVS_PRINT_DEBUG, " ctds %d", ctds_value); + test_fails++; + } + } + } + + if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p038_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p039.c b/test_pool/pcie/test_p039.c new file mode 100644 index 00000000..5e28c823 --- /dev/null +++ b/test_pool/pcie/test_p039.c @@ -0,0 +1,123 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 39) +#define TEST_DESC "Check i-EP atomicop rule " + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t rp_bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t reg_value; + uint32_t dp_type; + uint32_t cap_base; + uint32_t atomicop_32_cap; + uint32_t atomicop_64_cap; + uint32_t atomicop_128_cap; + uint32_t rp_routing_cap; + uint32_t rp_requester_cap; + uint32_t ep_requester_cap; + uint32_t test_fails; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + tbl_index = 0; + test_fails = 0; + + /* Check for all the function present in bdf table */ + for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++) + { + bdf = bdf_tbl_ptr->device[tbl_index].bdf; + dp_type = val_pcie_device_port_type(bdf); + + /* Check entry is i-EP */ + if (dp_type == iEP_EP) + { + /* Read iEP atomicop completer bits */ + val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cap_base); + val_pcie_read_cfg(bdf, cap_base + DCAP2R_OFFSET, ®_value); + atomicop_32_cap = (reg_value >> DCAP2R_A32C_SHIFT) & DCAP2R_A32C_MASK; + atomicop_64_cap = (reg_value >> DCAP2R_A64C_SHIFT) & DCAP2R_A64C_MASK; + atomicop_128_cap = (reg_value >> DCAP2R_A128C_SHIFT) & DCAP2R_A128C_MASK; + + /* Read RP atomicop routing capability */ + rp_bdf = bdf_tbl_ptr->device[tbl_index].rp_bdf; + val_pcie_find_capability(rp_bdf, PCIE_CAP, CID_PCIECS, &cap_base); + val_pcie_read_cfg(rp_bdf, cap_base + DCAP2R_OFFSET, ®_value); + rp_routing_cap = (reg_value >> DCAP2R_ARS_SHIFT) & DCAP2R_ARS_MASK; + + rp_requester_cap = val_pcie_get_atomicop_requester_capable(rp_bdf); + + /* if iEP is atomicop completer capable, RP should be routing or requester capable */ + if ((atomicop_32_cap || atomicop_64_cap || atomicop_128_cap) && + ((rp_routing_cap == 0) && (rp_requester_cap == 0))) + { + val_print(AVS_PRINT_DEBUG, " BDF 0x%x atomicop completer fail", bdf); + test_fails++; + } + + ep_requester_cap = val_pcie_get_atomicop_requester_capable(bdf); + + /* if iEP is atomicop requester capable, RP should be routing or completer capable */ + if ((ep_requester_cap) && + ((rp_routing_cap == 0) && (rp_requester_cap == 0))) + { + val_print(AVS_PRINT_DEBUG, " BDF 0x%x atomicop requester fail", bdf); + test_fails++; + } + } + } + + if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p039_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p040.c b/test_pool/pcie/test_p040.c new file mode 100644 index 00000000..f1c24651 --- /dev/null +++ b/test_pool/pcie/test_p040.c @@ -0,0 +1,89 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 40) +#define TEST_DESC "Check Rootport ATS and PRI rule " + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t dp_type; + uint32_t cap_base; + uint32_t test_fails; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + test_fails = 0; + + /* Check for all the function present in bdf table */ + for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++) + { + bdf = bdf_tbl_ptr->device[tbl_index].bdf; + dp_type = val_pcie_device_port_type(bdf); + + /* Check entry is rootport */ + if ((dp_type == RP) || (dp_type == iEP_RP)) + { + /* If ATS capability support for RP, test fails */ + if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ATS, &cap_base) == PCIE_SUCCESS) + test_fails++; + + /* If PRI capability support for RP, test fails */ + if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_PRI, &cap_base) == PCIE_SUCCESS) + test_fails++; + } + } + + if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p040_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p041.c b/test_pool/pcie/test_p041.c new file mode 100644 index 00000000..6f974af5 --- /dev/null +++ b/test_pool/pcie/test_p041.c @@ -0,0 +1,86 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 41) +#define TEST_DESC "Check MSI and MSI-X support rule " + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t dp_type; + uint32_t cap_base; + uint32_t test_fails; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + test_fails = 0; + + /* Check for all the function present in bdf table */ + for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++) + { + bdf = bdf_tbl_ptr->device[tbl_index].bdf; + dp_type = val_pcie_device_port_type(bdf); + + /* Check entry is endpoint or rciep */ + if ((dp_type == iEP_EP) || (dp_type == RCiEP)) + { + /* If MSI or MSI-X not supported, test fails */ + if ((val_pcie_find_capability(bdf, PCIE_CAP, CID_MSI, &cap_base) == PCIE_CAP_NOT_FOUND) && + (val_pcie_find_capability(bdf, PCIE_CAP, CID_MSIX, &cap_base) == PCIE_CAP_NOT_FOUND)) + test_fails++; + } + } + + if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p041_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p042.c b/test_pool/pcie/test_p042.c new file mode 100644 index 00000000..49088d82 --- /dev/null +++ b/test_pool/pcie/test_p042.c @@ -0,0 +1,85 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 42) +#define TEST_DESC "Check Power Management rules " + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t dp_type; + uint32_t cap_base; + uint32_t test_fails; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + test_fails = 0; + + /* Check for all the function present in bdf table */ + for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++) + { + bdf = bdf_tbl_ptr->device[tbl_index].bdf; + dp_type = val_pcie_device_port_type(bdf); + + /* Check entry is onchip peripherals */ + if ((dp_type == iEP_EP) || (dp_type == RCiEP) || (dp_type == iEP_RP)) + { + /* If Power Management capability not supported, test fails */ + if (val_pcie_find_capability(bdf, PCIE_CAP, CID_PMC, &cap_base) == PCIE_CAP_NOT_FOUND) + test_fails++; + } + } + + if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p042_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p043.c b/test_pool/pcie/test_p043.c new file mode 100644 index 00000000..8c6a013e --- /dev/null +++ b/test_pool/pcie/test_p043.c @@ -0,0 +1,124 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 43) +#define TEST_DESC "Check ARI forwarding enable rule " + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t dp_type; + uint32_t cap_base; + uint32_t ari_frwd_enable; + uint32_t seg_num; + uint32_t dev_num; + uint32_t dev_bdf; + uint32_t sec_bus; + uint32_t sub_bus; + uint32_t test_fails; + uint32_t reg_value; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + test_fails = 0; + + /* Check for all the function present in bdf table */ + for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++) + { + bdf = bdf_tbl_ptr->device[tbl_index].bdf; + dp_type = val_pcie_device_port_type(bdf); + + /* Check entry is Downstream port or RP */ + if ((dp_type == DP) || (dp_type == iEP_RP) || (dp_type == RP)) + { + /* Read the ARI forwarding enable bit */ + val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cap_base); + val_pcie_read_cfg(bdf, cap_base + DCTL2R_OFFSET, ®_value); + ari_frwd_enable = (reg_value >> DCTL2R_AFE_SHIFT) & DCTL2R_AFE_MASK; + + /* If ARI forwarding enable set, skip the entry */ + if (ari_frwd_enable != 0) + continue; + + val_pcie_read_cfg(bdf, TYPE1_PBN, ®_value); + sec_bus = ((reg_value >> SECBN_SHIFT) & SECBN_MASK); + sub_bus = ((reg_value >> SUBBN_SHIFT) & SUBBN_MASK); + + /* Skip the port, if switch is present below it */ + if (sec_bus != sub_bus) + continue; + + /* Configuration Requests specifying Device Numbers (1-31) must be terminated by the + * Downstream Port or the Root Port with an Unsupported Request Completion Status + */ + + for (dev_num = 1; dev_num < PCIE_MAX_DEV; dev_num++) + { + seg_num = PCIE_EXTRACT_BDF_SEG(bdf); + + /* Create bdf for Dev 1 to 31 below the RP */ + dev_bdf = PCIE_CREATE_BDF(seg_num, sec_bus, dev_num, 0); + val_pcie_read_cfg(dev_bdf, TYPE01_VIDR, ®_value); + if (reg_value != PCIE_UNKNOWN_RESPONSE) + { + test_fails++; + val_print(AVS_PRINT_ERR, "\n Dev 0x%x found under", dev_bdf); + val_print(AVS_PRINT_ERR, " RP bdf 0x%x", bdf); + } + } + } + } + + if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p043_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p044.c b/test_pool/pcie/test_p044.c new file mode 100644 index 00000000..c7b334af --- /dev/null +++ b/test_pool/pcie/test_p044.c @@ -0,0 +1,142 @@ +/** @file + * Copyright (c) 2020 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 44) +#define TEST_DESC "Check device under RP in same ECAM" + + +uint8_t func_ecam_is_rp_ecam(uint32_t dsf_bdf) +{ + + uint8_t dsf_bus; + uint32_t bdf; + uint32_t dp_type; + uint32_t tbl_index; + uint32_t reg_value; + uint32_t ecam_cc; + uint32_t pciio_proto_cc; + addr_t ecam_base; + pcie_device_bdf_table *bdf_tbl_ptr; + + tbl_index = 0; + dsf_bus = PCIE_EXTRACT_BDF_BUS(dsf_bdf); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + while (tbl_index < bdf_tbl_ptr->num_entries) + { + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + dp_type = val_pcie_device_port_type(bdf); + + /* Check if this table entry is a Root Port */ + if (dp_type == RP || dp_type == iEP_RP) + { + /* Check if the entry's bus range covers down stream function */ + val_pcie_read_cfg(bdf, TYPE1_PBN, ®_value); + if ((dsf_bus >= ((reg_value >> SECBN_SHIFT) & SECBN_MASK)) && + (dsf_bus <= ((reg_value >> SUBBN_SHIFT) & SUBBN_MASK))) + { + ecam_base = val_pcie_get_ecam_base(bdf); + + /* Read Function's Class Code through ECAM method */ + ecam_cc = val_mmio_read(ecam_base + + dsf_bus * PCIE_MAX_DEV * PCIE_MAX_FUNC * PCIE_CFG_SIZE + + PCIE_EXTRACT_BDF_DEV(dsf_bdf) * PCIE_MAX_FUNC * PCIE_CFG_SIZE + + PCIE_EXTRACT_BDF_FUNC(dsf_bdf) * PCIE_CFG_SIZE + + TYPE01_RIDR); + + /* Read Function's Class Code through Pciio Protocol method */ + val_pcie_io_read_cfg(dsf_bdf, TYPE01_RIDR, &pciio_proto_cc); + + /* Return success if both methods read same Class Code */ + if (ecam_cc == pciio_proto_cc) + return 0; + else + return 1; + } + } + } + + return 1; +} + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t dp_type; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t fail_cnt; + pcie_device_bdf_table *bdf_tbl_ptr; + + fail_cnt = 0; + tbl_index = 0; + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + while (tbl_index < bdf_tbl_ptr->num_entries) + { + /* + * If a function is in the hierarchy domain + * originated by a Root Port, check its ECAM + * is same as its RootPort ECAM. + */ + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + dp_type = val_pcie_device_port_type(bdf); + if (dp_type == EP || dp_type == iEP_EP || + dp_type == UP || dp_type == DP) + if (func_ecam_is_rp_ecam(bdf)) + { + val_print(AVS_PRINT_ERR, "\n bdf: 0x%x ", bdf); + val_print(AVS_PRINT_ERR, "dp_type: 0x%x ", dp_type); + fail_cnt++; + } + } + + if (fail_cnt) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, fail_cnt)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p044_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p045.c b/test_pool/pcie/test_p045.c new file mode 100644 index 00000000..238a9df8 --- /dev/null +++ b/test_pool/pcie/test_p045.c @@ -0,0 +1,100 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 45) +#define TEST_DESC "Check all RP in HB is in same ECAM" + + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t dp_type; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t ecam_index; + uint32_t ecam_base; + uint32_t reg_value; + uint16_t vendor_id; + uint32_t device_id; + pcie_device_bdf_table *bdf_tbl_ptr; + + tbl_index = 0; + ecam_index = 0; + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + while (ecam_index < val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0)) + { + ecam_base = val_pcie_get_info(PCIE_INFO_ECAM, ecam_index); + val_print(AVS_PRINT_ERR, "\n WARNING: RPs under ECAM Base 0x%x :", ecam_base); + + while (tbl_index < bdf_tbl_ptr->num_entries) + { + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + + dp_type = val_pcie_device_port_type(bdf); + if (dp_type == RP || dp_type == iEP_RP) + { + if (ecam_base == val_pcie_get_ecam_base(bdf)) + { + val_pcie_read_cfg(bdf, TYPE01_VIDR, ®_value); + device_id = (reg_value >> TYPE01_DIDR_SHIFT) & TYPE01_DIDR_MASK; + vendor_id = (reg_value >> TYPE01_VIDR_SHIFT) & TYPE01_VIDR_MASK; + + val_print(AVS_PRINT_ERR, "\n BDF: 0x%x ", bdf); + val_print(AVS_PRINT_ERR, "Dev ID: 0x%x ", device_id); + val_print(AVS_PRINT_ERR, "Vendor ID: 0x%x", vendor_id); + } + } + + } + + ecam_index++; + } + + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p045_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/peripherals/test_d001.c b/test_pool/peripherals/test_d001.c index f83ecad8..0c762940 100755 --- a/test_pool/peripherals/test_d001.c +++ b/test_pool/peripherals/test_d001.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -44,11 +44,11 @@ payload() bdf = val_peripheral_get_info(USB_BDF, count - 1); ret = val_pcie_read_cfg(bdf, 0x8, &interface); interface = (interface >> 8) & 0xFF; - if (ret == PCIE_READ_ERR || (interface < 0x20) || (interface == 0xFF)) { + if (ret == PCIE_NO_MAPPING || (interface < 0x20) || (interface == 0xFF)) { val_print(AVS_PRINT_WARN, "\n WARN: USB CTRL ECAM access failed 0x%x ", interface); val_print(AVS_PRINT_WARN, "\n Re-checking USB CTRL using PciIo protocol ", 0); ret = val_pcie_io_read_cfg(bdf, 0x8, &interface); - if (ret == PCIE_READ_ERR) { + if (ret == PCIE_NO_MAPPING) { val_print(AVS_PRINT_ERR, "\n Reading device class code using PciIo protocol failed ", 0); val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); return; diff --git a/test_pool/peripherals/test_d002.c b/test_pool/peripherals/test_d002.c index 03252198..ee5e2513 100755 --- a/test_pool/peripherals/test_d002.c +++ b/test_pool/peripherals/test_d002.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -44,11 +44,11 @@ payload() bdf = val_peripheral_get_info(SATA_BDF, count - 1); ret = val_pcie_read_cfg(bdf, 0x8, &interface); interface = (interface >> 8) & 0xFF; - if (ret == PCIE_READ_ERR || interface != 0x01) { + if (ret == PCIE_NO_MAPPING || interface != 0x01) { val_print(AVS_PRINT_WARN, "\n WARN: SATA CTRL ECAM access failed %x ", interface); val_print(AVS_PRINT_WARN, "\n Re-checking SATA CTRL using PciIo protocol ", 0); ret = val_pcie_io_read_cfg(bdf, 0x8, &interface); - if (ret == PCIE_READ_ERR) { + if (ret == PCIE_NO_MAPPING) { val_print(AVS_PRINT_ERR, "\n Reading device class code using PciIo protocol failed ", 0); val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); return; diff --git a/test_pool/timer_wd/test_w002.c b/test_pool/timer_wd/test_w002.c index 48c6e0f2..295b0afd 100755 --- a/test_pool/timer_wd/test_w002.c +++ b/test_pool/timer_wd/test_w002.c @@ -71,6 +71,12 @@ payload() val_gic_install_isr(int_id, isr); + /* Set Interrupt Type Edge/Level Trigger */ + if (val_wd_get_info(wd_num, WD_INFO_IS_EDGE)) + val_gic_set_intr_trigger(int_id, INTR_TRIGGER_INFO_EDGE_RISING); + else + val_gic_set_intr_trigger(int_id, INTR_TRIGGER_INFO_LEVEL_HIGH); + val_wd_set_ws0(wd_num, timer_expire_ticks); while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))); diff --git a/tools/scripts/avsbuild.sh b/tools/scripts/avsbuild.sh old mode 100755 new mode 100644 index c89ec3f5..b789e471 --- a/tools/scripts/avsbuild.sh +++ b/tools/scripts/avsbuild.sh @@ -1,4 +1,3 @@ - if [ -v $GCC49_AARCH64_PREFIX ] then echo "GCC49_AARCH64_PREFIX is not set" @@ -6,5 +5,56 @@ then return 0 fi -build -a AARCH64 -t GCC49 -p ShellPkg/ShellPkg.dsc -m AppPkg/Applications/sbsa-acs/uefi_app/SbsaAvs.inf +NISTStatus=1; + +function build_with_NIST() +{ + if [ ! -f "sts-2_1_2.zip" ]; then + wget https://csrc.nist.gov/CSRC/media/Projects/Random-Bit-Generation/documents/sts-2_1_2.zip + status=$? + if [ $status -ne 0 ]; then + echo "wget failed for NIST. Building sbsa without NIST" + return $status + fi + fi + + if [ ! -d "AppPkg/Applications/sbsa-acs/test_pool/nist_sts/sts-2.1.2/" ]; then + /usr/bin/unzip sts-2_1_2.zip -d AppPkg/Applications/sbsa-acs/test_pool/nist_sts/. + status=$? + if [ $status -ne 0 ]; then + echo "unzip failed for NIST. Building sbsa without NIST" + return $status + fi + fi + + cd AppPkg/Applications/sbsa-acs/test_pool/nist_sts/sts-2.1.2/ + if ! patch -R -p1 -s -f --dry-run < ../../../patches/nist_sbsa_sts.diff; then + patch -p1 < ../../../patches/nist_sbsa_sts.diff + status=$? + if [ $status -ne 0 ]; then + echo "patch failed for NIST. Building sbsa without NIST" + return $status + fi + fi + cd - + + build -a AARCH64 -t GCC49 -p ShellPkg/ShellPkg.dsc -m AppPkg/Applications/sbsa-acs/uefi_app/SbsaAvsNist.inf -D ENABLE_NIST + status=$? + if [ $status -ne 0 ]; then + echo "Build failed for NIST. Building sbsa without NIST" + return $status + fi + + return $status +} + + +if [ "$1" == "NIST" ]; then + build_with_NIST + NISTStatus=$? +fi + +if [ $NISTStatus -ne 0 ]; then + build -a AARCH64 -t GCC49 -p ShellPkg/ShellPkg.dsc -m AppPkg/Applications/sbsa-acs/uefi_app/SbsaAvs.inf +fi diff --git a/uefi_app/SbsaAvs.h b/uefi_app/SbsaAvs.h index bdb64916..3ed5aea1 100755 --- a/uefi_app/SbsaAvs.h +++ b/uefi_app/SbsaAvs.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -21,9 +21,9 @@ #define SBSA_ACS_MAJOR_VER 2 - #define SBSA_ACS_MINOR_VER 3 + #define SBSA_ACS_MINOR_VER 4 - #define G_SBSA_LEVEL 3 + #define G_SBSA_LEVEL 4 #define SBSA_MAX_LEVEL_SUPPORTED 5 #define G_PRINT_LEVEL AVS_PRINT_TEST @@ -36,5 +36,9 @@ #define PERIPHERAL_INFO_TBL_SZ 1024 /*Supports maximum 20 PCIe EPs (USB and SATA controllers only) */ #define PCIE_INFO_TBL_SZ 512 /*Supports maximum 20 RC's*/ + #ifdef _AARCH64_BUILD_ + unsigned long __stack_chk_guard = 0xBAAAAAAD; + unsigned long __stack_chk_fail = 0xBAAFAAAD; + #endif #endif diff --git a/uefi_app/SbsaAvs.inf b/uefi_app/SbsaAvs.inf old mode 100755 new mode 100644 index 514dcffe..2a9d1474 --- a/uefi_app/SbsaAvs.inf +++ b/uefi_app/SbsaAvs.inf @@ -1,5 +1,5 @@ ## @file -# Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -78,7 +78,32 @@ ../test_pool/timer_wd/test_w002.c ../test_pool/pcie/test_p001.c ../test_pool/pcie/test_p002.c - ../test_pool/pcie/test_p003.c + ../test_pool/pcie/test_p020.c + ../test_pool/pcie/test_p021.c + ../test_pool/pcie/test_p022.c + ../test_pool/pcie/test_p023.c + ../test_pool/pcie/test_p024.c + ../test_pool/pcie/test_p025.c + ../test_pool/pcie/test_p026.c + ../test_pool/pcie/test_p027.c + ../test_pool/pcie/test_p028.c + ../test_pool/pcie/test_p029.c + ../test_pool/pcie/test_p030.c + ../test_pool/pcie/test_p031.c + ../test_pool/pcie/test_p032.c + ../test_pool/pcie/test_p033.c + ../test_pool/pcie/test_p034.c + ../test_pool/pcie/test_p035.c + ../test_pool/pcie/test_p036.c + ../test_pool/pcie/test_p037.c + ../test_pool/pcie/test_p038.c + ../test_pool/pcie/test_p039.c + ../test_pool/pcie/test_p040.c + ../test_pool/pcie/test_p041.c + ../test_pool/pcie/test_p042.c + ../test_pool/pcie/test_p043.c + ../test_pool/pcie/test_p044.c + ../test_pool/pcie/test_p045.c ../test_pool/io_virt/test_i001.c ../test_pool/io_virt/test_i002.c ../test_pool/io_virt/test_i003.c @@ -99,8 +124,12 @@ ../test_pool/exerciser/test_e005.c ../test_pool/exerciser/test_e006.c ../test_pool/exerciser/test_e007.c + ../test_pool/exerciser/test_e008.c + ../test_pool/exerciser/test_e009.c + ../test_pool/exerciser/test_e010.c [Packages] + StdLib/StdLib.dec EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec diff --git a/uefi_app/SbsaAvsMain.c b/uefi_app/SbsaAvsMain.c old mode 100755 new mode 100644 index ca235b34..806da0eb --- a/uefi_app/SbsaAvsMain.c +++ b/uefi_app/SbsaAvsMain.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -31,8 +31,10 @@ UINT32 g_sbsa_level; +UINT32 g_enable_pcie_tests; UINT32 g_print_level; UINT32 g_execute_secure; +UINT32 g_execute_nist; UINT32 g_skip_test_num[3] = {10000, 10000, 10000}; UINT32 g_sbsa_tests_total; UINT32 g_sbsa_tests_pass; @@ -238,7 +240,7 @@ HelpMsg ( VOID ) { - Print (L"\nUsage: Sbsa.efi [-v ] | [-l ] | [-f ] | [-s] | [-skip ]\n" + Print (L"\nUsage: Sbsa.efi [-v ] | [-l ] | [-f ] | [-s] | [-skip ] | [-nist] | [-p ]\n" "Options:\n" "-v Verbosity of the Prints\n" " 1 shows all prints, 5 shows Errors\n" @@ -250,6 +252,9 @@ HelpMsg ( " Refer to section 4 of SBSA_ACS_User_Guide\n" " To skip a module, use Model_ID as mentioned in user guide\n" " To skip a particular test within a module, use the exact testcase number\n" + "-nist Enable the NIST Statistical test suite\n" + "-p Enable/disable PCIe SBSA 6.0 (RCiEP) compliance tests\n" + " 1 - enables PCIe tests, 0 - disables PCIe tests\n" ); } @@ -261,10 +266,11 @@ STATIC CONST SHELL_PARAM_ITEM ParamList[] = { {L"-skip" , TypeValue}, // -skip # test(s) to skip execution {L"-help" , TypeFlag}, // -help # help : info about commands {L"-h" , TypeFlag}, // -h # help : info about commands + {L"-nist" , TypeFlag}, // -nist # Binary Flag to enable the execution of NIST STS + {L"-p" , TypeValue}, // -p # Enable/disable PCIe SBSA 6.0 (RCiEP) compliance tests. {NULL , TypeMax} }; - /*** SBSA Compliance Suite Entry Point. @@ -275,7 +281,7 @@ STATIC CONST SHELL_PARAM_ITEM ParamList[] = { ***/ INTN EFIAPI -ShellAppMain ( +ShellAppMainsbsa ( IN UINTN Argc, IN CHAR16 **Argv ) @@ -301,30 +307,25 @@ ShellAppMain ( return SHELL_INVALID_PARAMETER; } - for (i=1 ; i= 4) + g_enable_pcie_tests = 1; + else + g_enable_pcie_tests = 0; + } else { + g_enable_pcie_tests = StrDecimalToUintn(CmdLineArg); + if (g_enable_pcie_tests != 1 && g_enable_pcie_tests != 0) { + Print(L"Invalid PCIe option.\nEnter \"-p 1\" to enable or \"-p 0\" to disable PCIe SBSA 6.0 (RCiEP) tests\n", g_enable_pcie_tests); + return 0; + } + } + // // Initialize global counters // @@ -377,7 +400,6 @@ ShellAppMain ( Print(L"\n\n SBSA Architecture Compliance Suite \n"); Print(L" Version %d.%d \n", SBSA_ACS_MAJOR_VER, SBSA_ACS_MINOR_VER); - Print(L"\n Starting tests for level %2d (Print level is %2d)\n\n", g_sbsa_level, g_print_level); @@ -422,7 +444,7 @@ ShellAppMain ( Status |= val_wd_execute_tests(g_sbsa_level, val_pe_get_num()); Print(L"\n *** Starting PCIe tests *** \n"); - Status |= val_pcie_execute_tests(g_sbsa_level, val_pe_get_num()); + Status |= val_pcie_execute_tests(g_enable_pcie_tests, g_sbsa_level, val_pe_get_num()); Print(L"\n *** Starting Power and Wakeup semantic tests *** \n"); Status |= val_wakeup_execute_tests(g_sbsa_level, val_pe_get_num()); @@ -436,6 +458,13 @@ ShellAppMain ( Print(L"\n *** Starting PCIe Exerciser tests *** \n"); Status |= val_exerciser_execute_tests(g_sbsa_level); + #ifdef ENABLE_NIST + if (g_execute_nist == TRUE) { + Print(L"\n *** Starting NIST statistical tests*** \n"); + Status |= val_nist_execute_tests(g_sbsa_level, val_pe_get_num()); + } + #endif + print_test_status: val_print(AVS_PRINT_TEST, "\n ------------------------------------------------------- \n", 0); val_print(AVS_PRINT_TEST, " Total Tests run = %4d;", g_sbsa_tests_total); @@ -455,3 +484,24 @@ ShellAppMain ( return(0); } + +#ifndef ENABLE_NIST +/*** + SBSA Compliance Suite Entry Point. This function is to + support compilation of SBSA without NIST changes in edk2 + + Call the Entry points of individual modules. + + @retval 0 The application exited normally. + @retval Other An error occurred. +***/ +INTN +EFIAPI +ShellAppMain( + IN UINTN Argc, + IN CHAR16 **Argv + ) +{ + return ShellAppMainsbsa(Argc, Argv); +} +#endif diff --git a/uefi_app/SbsaAvsNist.inf b/uefi_app/SbsaAvsNist.inf new file mode 100644 index 00000000..1cf15b04 --- /dev/null +++ b/uefi_app/SbsaAvsNist.inf @@ -0,0 +1,164 @@ +## @file +# Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +## + + +[Defines] + INF_VERSION = 0x00010006 + BASE_NAME = Sbsa + FILE_GUID = a912f198-7f0e-4803-b908-b757b806ec83 + MODULE_TYPE = UEFI_APPLICATION + VERSION_STRING = 0.1 + ENTRY_POINT = ShellCEntryLib + +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources.AARCH64] + ../ + SbsaAvsMain.c + ../test_pool/secure/test_s001.c + ../test_pool/secure/test_s002.c + ../test_pool/secure/test_s003.c + ../test_pool/pe/test_c001.c + ../test_pool/pe/test_c002.c + ../test_pool/pe/test_c003.c + ../test_pool/pe/test_c004.c + ../test_pool/pe/test_c005.c + ../test_pool/pe/test_c006.c + ../test_pool/pe/test_c007.c + ../test_pool/pe/test_c008.c + ../test_pool/pe/test_c009.c + ../test_pool/pe/test_c010.c + ../test_pool/pe/test_c011.c + ../test_pool/pe/test_c012.c + ../test_pool/pe/test_c013.c + ../test_pool/pe/test_c014.c + ../test_pool/pe/test_c015.c + ../test_pool/pe/test_c016.c + ../test_pool/pe/test_c017.c + ../test_pool/pe/test_c018.c + ../test_pool/pe/test_c019.c + ../test_pool/pe/test_c020.c + ../test_pool/pe/test_c021.c + ../test_pool/pe/test_c022.c + ../test_pool/pe/test_c023.c + ../test_pool/pe/test_c024.c + ../test_pool/pe/test_c025.c + ../test_pool/pe/test_c026.c + ../test_pool/pe/test_c027.c + ../test_pool/pe/test_c028.c + ../test_pool/gic/test_g001.c + ../test_pool/gic/test_g002.c + ../test_pool/gic/test_g003.c + ../test_pool/gic/test_g004.c + ../test_pool/timer_wd/test_t001.c + ../test_pool/timer_wd/test_t002.c + ../test_pool/timer_wd/test_t003.c + ../test_pool/timer_wd/test_t004.c + ../test_pool/timer_wd/test_t005.c + ../test_pool/timer_wd/test_t006.c + ../test_pool/timer_wd/test_t007.c + ../test_pool/timer_wd/test_t008.c + ../test_pool/timer_wd/test_w001.c + ../test_pool/timer_wd/test_w002.c + ../test_pool/pcie/test_p001.c + ../test_pool/pcie/test_p002.c + ../test_pool/pcie/test_p020.c + ../test_pool/pcie/test_p021.c + ../test_pool/pcie/test_p022.c + ../test_pool/pcie/test_p023.c + ../test_pool/pcie/test_p024.c + ../test_pool/pcie/test_p025.c + ../test_pool/pcie/test_p026.c + ../test_pool/pcie/test_p027.c + ../test_pool/pcie/test_p028.c + ../test_pool/pcie/test_p029.c + ../test_pool/pcie/test_p030.c + ../test_pool/pcie/test_p031.c + ../test_pool/pcie/test_p032.c + ../test_pool/pcie/test_p033.c + ../test_pool/pcie/test_p034.c + ../test_pool/pcie/test_p035.c + ../test_pool/pcie/test_p036.c + ../test_pool/pcie/test_p037.c + ../test_pool/pcie/test_p038.c + ../test_pool/pcie/test_p039.c + ../test_pool/pcie/test_p040.c + ../test_pool/pcie/test_p041.c + ../test_pool/pcie/test_p042.c + ../test_pool/pcie/test_p043.c + ../test_pool/pcie/test_p044.c + ../test_pool/pcie/test_p045.c + ../test_pool/io_virt/test_i001.c + ../test_pool/io_virt/test_i002.c + ../test_pool/io_virt/test_i003.c + ../test_pool/io_virt/test_i004.c + ../test_pool/io_virt/test_i005.c + ../test_pool/io_virt/test_i006.c + ../test_pool/power_wakeup/test_u001.c + ../test_pool/power_wakeup/test_u002.c + ../test_pool/peripherals/test_d001.c + ../test_pool/peripherals/test_d002.c + ../test_pool/peripherals/test_d003.c + ../test_pool/peripherals/test_m001.c + ../test_pool/peripherals/test_m002.c + ../test_pool/exerciser/test_e001.c + ../test_pool/exerciser/test_e002.c + ../test_pool/exerciser/test_e003.c + ../test_pool/exerciser/test_e004.c + ../test_pool/exerciser/test_e005.c + ../test_pool/exerciser/test_e006.c + ../test_pool/exerciser/test_e007.c + ../test_pool/exerciser/test_e008.c + ../test_pool/exerciser/test_e009.c + ../test_pool/exerciser/test_e010.c + ../test_pool/nist_sts/test_n001.c + +[Packages] + StdLib/StdLib.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ShellPkg/ShellPkg.dec + EdkCompatibilityPkg/EdkCompatibilityPkg.dec + +[LibraryClasses] + SbsaNistLib + SbsaValNistLib + SbsaPalNistLib + UefiLib + ShellLib + DebugLib + BaseMemoryLib + ShellCEntryLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + +[Protocols] + gEfiAcpiTableProtocolGuid ## CONSUMES + gHardwareInterruptProtocolGuid ## CONSUMES + gEfiCpuArchProtocolGuid ## CONSUMES + gEfiPciIoProtocolGuid ## CONSUMES + gEfiLoadedImageProtocolGuid ## CONSUMES + +[Guids] + gEfiAcpi20TableGuid + gEfiAcpiTableGuid + +[BuildOptions] + GCC:*_*_*_ASM_FLAGS = -march=armv8.1-a diff --git a/val/SbsaValLib.inf b/val/SbsaValLib.inf index d34aa3f0..956a9a5d 100644 --- a/val/SbsaValLib.inf +++ b/val/SbsaValLib.inf @@ -1,5 +1,5 @@ ## @file -# Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/val/SbsaValNistLib.inf b/val/SbsaValNistLib.inf new file mode 100644 index 00000000..2fc26eb6 --- /dev/null +++ b/val/SbsaValNistLib.inf @@ -0,0 +1,64 @@ +## @file +# Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SbsaValNistLib + FILE_GUID = cdd4fb8f-06c5-4a28-8cb8-7f5b664e278c + MODULE_TYPE = UEFI_APPLICATION + VERSION_STRING = 1.0 + LIBRARY_CLASS = SbsaValNistLib|UEFI_APPLICATION UEFI_DRIVER + +[Sources.common] + src/AArch64/PeRegSysSupport.S + src/AArch64/PeTestSupport.S + src/AArch64/ArchTimerSupport.S + src/AArch64/GicSupport.S + src/avs_status.c + src/avs_pe.c + src/avs_pe_infra.c + src/avs_gic.c + src/avs_gic_support.c + src/avs_pcie.c + src/avs_iovirt.c + src/avs_smmu.c + src/avs_test_infra.c + src/avs_timer.c + src/avs_timer_support.c + src/avs_wd.c + src/avs_wakeup.c + src/avs_peripherals.c + src/avs_secure.c + src/avs_memory.c + src/avs_exerciser.c + src/avs_nist.c + + [Packages] + StdLib/StdLib.dec + + [LibraryClasses] + LibC + LibStdLib + LibStdio + LibMath + DevShell + +[Packages] + MdePkg/MdePkg.dec + +[BuildOptions] + GCC:*_*_*_ASM_FLAGS = -march=armv8.2-a diff --git a/val/include/pal_interface.h b/val/include/pal_interface.h old mode 100755 new mode 100644 index b2d227db..11edae85 --- a/val/include/pal_interface.h +++ b/val/include/pal_interface.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,7 +40,12 @@ #define TIMEOUT_MEDIUM 0x100000 #define TIMEOUT_SMALL 0x1000 -#define PCIE_READ_ERR -1 +#define ONE_MILLISECOND 1000 + +#define PCIE_SUCCESS 0x00000000 /* Operation completed successfully */ +#define PCIE_NO_MAPPING 0x10000001 /* A mapping to a Function does not exist */ +#define PCIE_CAP_NOT_FOUND 0x10000010 /* The specified capability was not found */ +#define PCIE_UNKNOWN_RESPONSE 0xFFFFFFFF /* Function not found or UR response from completer */ /** PE Test related Definitions **/ @@ -138,7 +143,8 @@ void pal_gic_end_of_interrupt(uint32_t int_id); uint32_t pal_gic_request_irq(unsigned int irq_num, unsigned int mapped_irq_num, void *isr); void pal_gic_free_irq(unsigned int irq_num, unsigned int mapped_irq_num); uint32_t pal_gic_set_intr_trigger(uint32_t int_id, INTR_TRIGGER_INFO_TYPE_e trigger_type); - +uint32_t pal_gic_request_msi(uint32_t bdf, uint32_t IntID, uint32_t msi_index); +void pal_gic_free_msi(uint32_t bdf, uint32_t IntID, uint32_t msi_index); /** Timer tests related definitions **/ @@ -508,8 +514,8 @@ void pal_memory_unmap(void *addr); /* Common Definitions */ void pal_print(char8_t *string, uint64_t data); void pal_print_raw(uint64_t addr, char8_t *string, uint64_t data); - - +uint32_t pal_strncmp(char8_t *str1, char8_t *str2, uint32_t len); +void *pal_memcpy(void *dest_buffer, void *src_buffer, uint32_t len); void *pal_mem_alloc(uint32_t size); void *pal_mem_alloc_coherent(uint32_t bdf, uint32_t size, void *pa); void pal_mem_free(void *buffer); @@ -518,6 +524,7 @@ void pal_mem_set(void *buf, uint32_t size, uint8_t value); void pal_mem_free_coherent(uint32_t bdf, unsigned int size, void *va, void *pa); void *pal_mem_virt_to_phys(void *va); +uint64_t pal_time_delay_ms(uint64_t time_ms); void pal_mem_allocate_shared(uint32_t num_pe, uint32_t sizeofentry); void pal_mem_free_shared(void); uint64_t pal_mem_get_shared_addr(void); @@ -535,23 +542,21 @@ void pal_pe_data_cache_ops_by_va(uint64_t addr, uint32_t type); #define INVALIDATE 0x3 /* Exerciser definitions */ -#define EXERCISER_CLASSCODE 0x010203 #define MAX_ARRAY_SIZE 32 #define TEST_REG_COUNT 10 #define TEST_DDR_REGION_CNT 16 -typedef struct { - uint64_t buf[MAX_ARRAY_SIZE]; -} EXERCISER_INFO_BLOCK; +#define EXERCISER_ID 0xED0113B5 //device id + vendor id -typedef struct { - uint32_t num_exerciser_cards; - EXERCISER_INFO_BLOCK info[]; //Array of information blocks - per stimulus generation controller -} EXERCISER_INFO_TABLE; +typedef enum { + TYPE0 = 0x0, + TYPE1 = 0x1, +} EXERCISER_CFG_HEADER_TYPE; typedef enum { - EXERCISER_NUM_CARDS = 0x1 -} EXERCISER_INFO_TYPE; + CFG_READ = 0x0, + CFG_WRITE = 0x1, +} EXERCISER_CFG_TXN_ATTR; typedef enum { EDMA_NO_SUPPORT = 0x0, @@ -567,7 +572,8 @@ typedef enum { MSIX_ATTRIBUTES = 0x3, DMA_ATTRIBUTES = 0x4, P2P_ATTRIBUTES = 0x5, - PASID_ATTRIBUTES = 0x6 + PASID_ATTRIBUTES = 0x6, + CFG_TXN_ATTRIBUTES = 0x7 } EXERCISER_PARAM_TYPE; typedef enum { @@ -587,7 +593,9 @@ typedef enum { PASID_TLP_START = 0x7, PASID_TLP_STOP = 0x8, NO_SNOOP_CLEAR_TLP_START = 0x9, - NO_SNOOP_CLEAR_TLP_STOP = 0xa + NO_SNOOP_CLEAR_TLP_STOP = 0xa, + START_TXN_MONITOR = 0xb, + STOP_TXN_MONITOR = 0xc } EXERCISER_OPS; typedef enum { @@ -638,14 +646,13 @@ typedef enum { } EXERCISER_DATA_TYPE; -void pal_exerciser_create_info_table(EXERCISER_INFO_TABLE *exerciser_info_table); -uint32_t pal_exerciser_get_info(EXERCISER_INFO_TYPE type, uint32_t instance); -uint32_t pal_exerciser_set_param(EXERCISER_PARAM_TYPE type, uint64_t value1, uint64_t value2, uint32_t instance); -uint32_t pal_exerciser_get_param(EXERCISER_PARAM_TYPE type, uint64_t *value1, uint64_t *value2, uint32_t instance); -uint32_t pal_exerciser_set_state(EXERCISER_STATE state, uint64_t *value, uint32_t instance); -uint32_t pal_exerciser_get_state(EXERCISER_STATE state, uint64_t *value, uint32_t instance); +uint32_t pal_exerciser_set_param(EXERCISER_PARAM_TYPE type, uint64_t value1, uint64_t value2, uint32_t bdf); +uint32_t pal_exerciser_get_param(EXERCISER_PARAM_TYPE type, uint64_t *value1, uint64_t *value2, uint32_t bdf); +uint32_t pal_exerciser_set_state(EXERCISER_STATE state, uint64_t *value, uint32_t bdf); +uint32_t pal_exerciser_get_state(EXERCISER_STATE *state, uint32_t bdf); uint32_t pal_exerciser_ops(EXERCISER_OPS ops, uint64_t param, uint32_t instance); -uint32_t pal_exerciser_get_data(EXERCISER_DATA_TYPE type, exerciser_data_t *data, uint32_t instance); +uint32_t pal_exerciser_get_data(EXERCISER_DATA_TYPE type, exerciser_data_t *data, uint32_t bdf, uint64_t ecam); +uint32_t pal_nist_generate_rng(uint32_t *rng_buffer); #endif diff --git a/val/include/sbsa_avs_common.h b/val/include/sbsa_avs_common.h old mode 100755 new mode 100644 index efe0cf65..5be65600 --- a/val/include/sbsa_avs_common.h +++ b/val/include/sbsa_avs_common.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -35,16 +35,18 @@ #define AVS_SMMU_TEST_NUM_BASE 700 #define AVS_EXERCISER_TEST_NUM_BASE 800 #define AVS_SECURE_TEST_NUM_BASE 900 +#define AVS_NIST_TEST_NUM_BASE 1000 #define STATE_BIT 28 #define STATE_MASK 0xF - //These are the states a test can be in */ - #define TEST_START_VAL 0x1 - #define TEST_END_VAL 0x2 - #define TEST_PASS_VAL 0x4 - #define TEST_FAIL_VAL 0x8 - #define TEST_SKIP_VAL 0x9 - #define TEST_PENDING_VAL 0xA + +//These are the states a test can be in */ +#define TEST_START_VAL 0x1 +#define TEST_END_VAL 0x2 +#define TEST_PASS_VAL 0x4 +#define TEST_FAIL_VAL 0x8 +#define TEST_SKIP_VAL 0x9 +#define TEST_PENDING_VAL 0xA #define CPU_NUM_BIT 32 #define CPU_NUM_MASK 0xFFFFFFFF @@ -52,9 +54,10 @@ #define LEVEL_BIT 24 #define LEVEL_MASK 0xF -#define TEST_NUM_BIT 16 -#define TEST_NUM_MASK 0xFF +#define STATUS_MASK 0xFFF +#define TEST_NUM_BIT 12 +#define TEST_NUM_MASK 0xFFF /* TEST start and Stop defines */ diff --git a/val/include/sbsa_avs_exerciser.h b/val/include/sbsa_avs_exerciser.h index fc0787b8..ca899438 100644 --- a/val/include/sbsa_avs_exerciser.h +++ b/val/include/sbsa_avs_exerciser.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -18,16 +18,39 @@ #ifndef __SBSA_AVS_EXERCISER_H__ #define __SBSA_AVS_EXERCISER_H__ -void val_exerciser_create_info_table(EXERCISER_INFO_TABLE *exerciser_info_table); + +#define MAX_EXERCISER_CARDS 20 +#define BUS_MEM_EN_MASK 0x06 + +/* PCIe Config space Offset */ +#define COMMAND_REG_OFFSET 0x04 + +typedef struct { + uint32_t bdf; + uint32_t initialized; +} EXERCISER_INFO_BLOCK; + +typedef struct { + uint32_t num_exerciser; + EXERCISER_INFO_BLOCK e_info[MAX_EXERCISER_CARDS]; +} EXERCISER_INFO_TABLE; + +typedef enum { + EXERCISER_NUM_CARDS = 0x1 +} EXERCISER_INFO_TYPE; + + +void val_exerciser_create_info_table(void); +uint32_t val_exerciser_init(uint32_t instance); uint32_t val_exerciser_get_info(EXERCISER_INFO_TYPE type, uint32_t instance); uint32_t val_exerciser_set_param(EXERCISER_PARAM_TYPE type, uint64_t value1, uint64_t value2, uint32_t instance); uint32_t val_exerciser_get_param(EXERCISER_PARAM_TYPE type, uint64_t *value1, uint64_t *value2, uint32_t instance); uint32_t val_exerciser_set_state(EXERCISER_STATE state, uint64_t *value, uint32_t instance); -uint32_t val_exerciser_get_state(EXERCISER_STATE state, uint64_t *value, uint32_t instance); +uint32_t val_exerciser_get_state(EXERCISER_STATE *state, uint32_t instance); uint32_t val_exerciser_ops(EXERCISER_OPS ops, uint64_t param, uint32_t instance); uint32_t val_exerciser_get_data(EXERCISER_DATA_TYPE type, exerciser_data_t *data, uint32_t instance); uint32_t val_exerciser_execute_tests(uint32_t level); - +uint32_t val_exerciser_get_bdf(uint32_t instance); uint32_t e001_entry(void); uint32_t e002_entry(void); @@ -36,5 +59,8 @@ uint32_t e004_entry(void); uint32_t e005_entry(void); uint32_t e006_entry(void); uint32_t e007_entry(void); +uint32_t e008_entry(void); +uint32_t e009_entry(void); +uint32_t e010_entry(void); #endif diff --git a/val/include/sbsa_avs_nist.h b/val/include/sbsa_avs_nist.h new file mode 100644 index 00000000..1be56f90 --- /dev/null +++ b/val/include/sbsa_avs_nist.h @@ -0,0 +1,40 @@ +/** @file + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SBSA_AVS_NIST_H__ +#define __SBSA_AVS_NIST_H__ + +extern uint32_t test_select; + +uint32_t n001_entry(uint32_t num_pe); +double erf(double x); +double erfc(double x); +#endif diff --git a/val/include/sbsa_avs_pcie.h b/val/include/sbsa_avs_pcie.h index d64fef63..244717cd 100644 --- a/val/include/sbsa_avs_pcie.h +++ b/val/include/sbsa_avs_pcie.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -18,6 +18,8 @@ #ifndef __SBSA_AVS_PCIE_H__ #define __SBSA_AVS_PCIE_H__ +#include "sbsa_avs_pcie_spec.h" + #define PCIE_EXTRACT_BDF_SEG(bdf) ((bdf >> 24) & 0xFF) #define PCIE_EXTRACT_BDF_BUS(bdf) ((bdf >> 16) & 0xFF) #define PCIE_EXTRACT_BDF_DEV(bdf) ((bdf >> 8) & 0xFF) @@ -29,6 +31,8 @@ #define PCIE_MAX_DEV 32 #define PCIE_MAX_FUNC 8 +#define PCIE_CFG_SIZE 4096 + #define PCIE_INTERRUPT_LINE 0x3c #define PCIE_INTERRUPT_PIN 0x3d @@ -41,9 +45,101 @@ #define PCI_EXT_CAPID_ACS 0x0D /* Access Control Services */ #define PCI_CAPID_ACS 0x04 /* ACS Capability Register */ +#define WORD_ALIGN_MASK 0x3 +#define BITS_IN_BYTE 0x8 + +#define REG_MASK(end, start) (((~(uint32_t)0 << (start)) & \ + (((uint32_t)1 << ((end)+1)) - 1)) >> (start)) +#define REG_SHIFT(alignment_byte_cnt, start) (((alignment_byte_cnt)*BITS_IN_BYTE) + start) + +#define MAX_BITFIELD_ENTRIES 100 +#define ERR_STRING_SIZE 64 + +/* Allows storage of 2048 valid BDFs */ +#define PCIE_DEVICE_BDF_TABLE_SZ 8192 + +typedef enum { + HEADER = 0, + PCIE_CAP = 1, + PCIE_ECAP = 2 +} BITFIELD_REGISTER_TYPE; + +typedef enum { + HW_INIT = 0, + READ_ONLY = 1, + STICKY_RO = 2, + RSVDP_RO = 3, + RSVDZ_RO = 4, + READ_WRITE = 5, + STICKY_RW = 6 +} BITFIELD_ATTR_TYPE; + +/** + @brief Structure describes bit-field representation of PCIe config registers + @reg_type Bit-filed can be part of one of the following registers: + 0: PCIe header register + 1: PCIe capability register + 2: PCie extended capability register + @icap_id Applicable only to PCIe capability register type + @ecap_id Applicable only to PCIe extended cabality register type + @reg_offset Offset is from one of the following memory mapped base addresses: + ECAM base address for reg_type = 0 + ECAM cap_id structure base address for reg_type = 1 + ECAM ecap_id structure base address for reg_type = 2 + @dev_port_bitmask Bitmask containing the type of PCIe device/port to which this + bf is applicable. Can take one of values in DEVICE_BITSMASK enum. + @start Bit-field start position within a register + @end Bit-field end position in a register + @cfg_value Bit-field configured value + @attr Bit-field configured attribute + @err_str1 Error string related to lost config value + @err_str2 Error string related to lost attribute +**/ + +typedef struct { + BITFIELD_REGISTER_TYPE reg_type; + uint16_t cap_id; + uint16_t ecap_id; + uint16_t reg_offset; + uint16_t dev_port_bitmask; + uint8_t start; + uint8_t end; + uint32_t cfg_value; + BITFIELD_ATTR_TYPE attr; + char err_str1[ERR_STRING_SIZE]; + char err_str2[ERR_STRING_SIZE]; +} pcie_cfgreg_bitfield_entry; + +typedef enum { + MMIO = 0, + IO = 1 +} MEM_INDICATOR_TYPE; + +typedef enum { + BITS_32 = 0, + BITS_64 = 2 +} MEM_DECODE_TYPE; + +typedef enum { + NON_PREFETCHABLE = 0, + PREFETCHABLE = 1 +} MEM_TYPE; + +typedef struct { + uint32_t bdf; + uint32_t rp_bdf; +} pcie_device_attr; + +typedef struct { + uint32_t num_entries; + pcie_device_attr device[]; ///< in the format of Segment/Bus/Dev/Func +} pcie_device_bdf_table; + void val_pcie_write_cfg(uint32_t bdf, uint32_t offset, uint32_t data); uint32_t val_pcie_read_cfg(uint32_t bdf, uint32_t offset, uint32_t *data); uint32_t val_get_msi_vectors (uint32_t bdf, PERIPHERAL_VECTOR_LIST **mvector); +uint32_t val_pcie_get_bdf_config_addr(uint32_t bdf); + typedef enum { PCIE_INFO_NUM_ECAM = 1, @@ -81,6 +177,12 @@ val_pcie_get_dma_coherent(uint32_t bdf); uint32_t val_pcie_io_read_cfg(uint32_t bdf, uint32_t offset, uint32_t *data); +uint32_t +val_pcie_get_rp_transaction_frwd_support(uint32_t bdf); + +uint32_t +val_pcie_get_atomicop_requester_capable(uint32_t bdf); + uint32_t p001_entry(uint32_t num_pe); @@ -137,4 +239,82 @@ p018_entry (uint32_t num_pe); uint32_t p019_entry (uint32_t num_pe); + +uint32_t +p020_entry(uint32_t num_pe); + +uint32_t +p021_entry(uint32_t num_pe); + +uint32_t +p022_entry(uint32_t num_pe); + +uint32_t +p023_entry(uint32_t num_pe); + +uint32_t +p024_entry(uint32_t num_pe); + +uint32_t +p025_entry(uint32_t num_pe); + +uint32_t +p026_entry(uint32_t num_pe); + +uint32_t +p027_entry(uint32_t num_pe); + +uint32_t +p028_entry(uint32_t num_pe); + +uint32_t +p029_entry(uint32_t num_pe); + +uint32_t +p030_entry(uint32_t num_pe); + +uint32_t +p031_entry(uint32_t num_pe); + +uint32_t +p032_entry(uint32_t num_pe); + +uint32_t +p033_entry(uint32_t num_pe); + +uint32_t +p034_entry(uint32_t num_pe); + +uint32_t +p035_entry(uint32_t num_pe); + +uint32_t +p036_entry(uint32_t num_pe); + +uint32_t +p037_entry(uint32_t num_pe); + +uint32_t +p038_entry(uint32_t num_pe); + +uint32_t +p039_entry(uint32_t num_pe); + +uint32_t +p040_entry(uint32_t num_pe); + +uint32_t +p041_entry(uint32_t num_pe); + +uint32_t +p042_entry(uint32_t num_pe); + +uint32_t +p043_entry(uint32_t num_pe); + +uint32_t +p044_entry(uint32_t num_pe); + +uint32_t +p045_entry(uint32_t num_pe); #endif diff --git a/val/include/sbsa_avs_pcie_spec.h b/val/include/sbsa_avs_pcie_spec.h new file mode 100644 index 00000000..6708a87c --- /dev/null +++ b/val/include/sbsa_avs_pcie_spec.h @@ -0,0 +1,225 @@ +/** @file + * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#ifndef __SBSA_AVS_PCIE_SPEC_H__ +#define __SBSA_AVS_PCIE_SPEC_H__ + +/* TYPE 0/1 Cmn Cfg reg offsets */ +#define TYPE01_VIDR 0x0 +#define TYPE01_CR 0x4 +#define TYPE01_RIDR 0x8 +#define TYPE01_CLSR 0xc +#define TYPE01_BAR 0x10 +#define TYPE01_CPR 0x34 +#define TYPE01_ILR 0x3c + +/* TYPE 0/1 Cmn Cfg reg shifts and masks */ +#define TYPE01_VIDR_SHIFT 0 +#define TYPE01_VIDR_MASK 0xffff +#define TYPE01_DIDR_SHIFT 16 +#define TYPE01_DIDR_MASK 0xffff +#define TYPE01_CCR_SHIFT 8 +#define TYPE01_CCR_MASK 0xffffff +#define TYPE01_CPR_SHIFT 0 +#define TYPE01_CPR_MASK 0xff +#define TYPE01_HTR_SHIFT 16 +#define TYPE01_HTR_MASK 0xff + +#define TYPE0_HEADER 0 +#define TYPE1_HEADER 1 + +/* Command register shifts */ +#define CR_MSE_SHIFT 1 +#define CR_BME_SHIFT 2 +#define CR_SCE_SHIFT 3 +#define CR_MWI_SHIFT 4 +#define CR_VPS_SHIFT 5 +#define CR_IDSEL_SHIFT 7 +#define CR_SERRE_SHIFT 8 +#define CR_FBTE_SHIFT 9 +#define CR_ID_SHIFT 10 + +/* Command register masks */ +#define CR_MSE_MASK 0x1 +#define CR_BME_MASK 0x1 +#define CR_SCE_MASK 0x1 +#define CR_MWI_MASK 0x1 +#define CR_VPS_MASK 0x1 +#define CR_IDSEL_MASK 0x1 +#define CR_SERRE_MASK 0x1 +#define CR_FBTE_MASK 0x1 +#define CR_ID_MASK 0x1 + +/* BIST register masks */ +#define BIST_REG_START 24 +#define BIST_REG_END 31 +#define BIST_BC_MASK 0x80 +#define BIST_SB_MASK 0x40 +#define BIST_CC_MASK 0x07 + +/* Header type reg shifts and masks */ +#define HTR_HL_SHIFT 0x0 +#define HTR_HL_MASK 0x3f + +/* BAR register shifts */ +#define BAR_MIT_SHIFT 0 +#define BAR_MDT_SHIFT 1 +#define BAR_MT_SHIFT 3 +#define BAR_BASE_SHIFT 4 + +/* BAR registrer masks */ +#define BAR_MIT_MASK 0x1 +#define BAR_MDT_MASK 0x3 +#define BAR_MT_MASK 0x1 +#define BAR_BASE_MASK 0xfffffff + +#define TYPE0_MAX_BARS 6 +#define TYPE1_MAX_BARS 2 + +/* Type 1 Cfg reg offsets */ +#define TYPE1_PBN 0x18 + +/* Bus Number reg shifts */ +#define SECBN_SHIFT 8 +#define SUBBN_SHIFT 16 + +/* Bus Number reg masks */ +#define SECBN_MASK 0xff +#define SUBBN_MASK 0xff + +/* Capability header reg shifts */ +#define PCIE_CIDR_SHIFT 0 +#define PCIE_NCPR_SHIFT 8 +#define PCIE_ECAP_CIDR_SHIFT 0 +#define PCIE_ECAP_NCPR_SHIFT 20 + +/* Capability header reg masks */ +#define PCIE_CIDR_MASK 0xff +#define PCIE_NCPR_MASK 0xff +#define PCIE_ECAP_CIDR_MASK 0xffff +#define PCIE_ECAP_NCPR_MASK 0xfff + +#define PCIE_CAP_START 0x40 +#define PCIE_CAP_END 0xFC +#define PCIE_ECAP_START 0x100 + +/* Capability Structure IDs */ +#define CID_PCIECS 0x10 +#define CID_MSI 0x05 +#define CID_MSIX 0x11 +#define CID_PMC 0x01 +#define ECID_ARICS 0x000E +#define ECID_ATS 0x000F +#define ECID_PRI 0x0013 + +/* PCI Express capability struct offsets */ +#define CIDR_OFFSET 0 +#define PCIECR_OFFSET 2 +#define DCAPR_OFFSET 4 +#define DCTLR_OFFSET 8 +#define DCAP2R_OFFSET 24 +#define DCTL2R_OFFSET 28 + +/* PCIe capabilities reg shifts and masks */ +#define PCIECR_DPT_SHIFT 4 +#define PCIECR_DPT_MASK 0xf + +/* Device Capabilities register */ +#define DCAPR_MPSS_SHIFT 0 +#define DCAPR_FLRC_SHIFT 28 + +/* Device Capabilities reg mask */ +#define DCAPR_MPSS_MASK 0x07 +#define DCAPR_FLRC_MASK 0x1 + +/* Device Control reg shifts */ +#define DCTLR_SHIFT 0 +#define DCTLR_CERE_SHIFT 0 +#define DCTLR_NFERE_SHIFT 1 +#define DCTLR_FERE_SHIFT 2 +#define DCTLR_URRE_SHIFT 3 +#define DCTLR_PFE_SHIFT 9 +#define DCTLR_APE_SHIFT 10 +#define DCTLR_ENS_SHIFT 11 +#define DCTLR_IFLR_SHIFT 15 +#define DCTLR_DSR_SHIFT 16 + +/* Device Control reg masks */ +#define DCTLR_MASK 0xffff +#define DCTLR_CERE_MASK 0x1 +#define DCTLR_NFERE_MASK 0x1 +#define DCTLR_FERE_MASK 0x1 +#define DCTLR_URRE_MASK 0x1 +#define DCTLR_PFE_MASK 0x1 +#define DCTLR_APE_MASK 0x1 +#define DCTLR_ENS_MASK 0x1 +#define DCTLR_IFLR_MASK 0x1 +#define DCTLR_DSR_MASK 0xffff +#define DCTLR_FLR_SET 0x8000 + +/* Device Status reg shifts */ +#define DSR_CED_SHIFT 0 +#define DSR_NFED_SHIFT 1 +#define DSR_FED_SHIFT 2 +#define DSR_URD_SHIFT 3 +#define DSR_TP_SHIFT 5 + +/* Device Status reg masks */ +#define DSR_CED_MASK 0x1 +#define DSR_NFED_MASK 0x1 +#define DSR_FED_MASK 0x1 +#define DSR_URD_MASK 0x1 +#define DSR_TP_MASK 0x1 + +/* Device Capabilities 2 reg shift */ +#define DCAP2R_AFS_SHIFT 5 +#define DCAP2R_OBFF_SHIFT 18 +#define DCAP2R_CTRS_SHIFT 0 +#define DCAP2R_CTDS_SHIFT 4 +#define DCAP2R_A32C_SHIFT 7 +#define DCAP2R_A64C_SHIFT 8 +#define DCAP2R_A128C_SHIFT 9 +#define DCAP2R_ARS_SHIFT 6 + +/* Device Capabilities 2 reg mask */ +#define DCAP2R_AFS_MASK 0x1 +#define DCAP2R_OBFF_MASK 0x3 +#define DCAP2R_CTRS_MASK 0xf +#define DCAP2R_CTDS_MASK 0x1 +#define DCAP2R_A32C_MASK 0x1 +#define DCAP2R_A64C_MASK 0x1 +#define DCAP2R_A128C_MASK 0x1 +#define DCAP2R_ARS_MASK 0x01 + +/* Device Control 2 reg shift */ +#define DCTL2R_AFE_SHIFT 5 + +/* Device Control 2 reg mask */ +#define DCTL2R_AFE_MASK 0x1 + +/* Device bitmask definitions */ +#define RCiEP (1 << 0b1001) +#define RCEC (1 << 0b1010) +#define EP (1 << 0b0000) +#define RP (1 << 0b0100) +#define UP (1 << 0b0101) +#define DP (1 << 0b0110) +#define iEP_EP (1 << 0b1100) +#define iEP_RP (1 << 0b1011) +#define PCIe_ALL (iEP_RP | iEP_EP | RP | EP | RCEC | RCiEP) + +#endif diff --git a/val/include/val_interface.h b/val/include/val_interface.h index 78ebf118..29462585 100644 --- a/val/include/val_interface.h +++ b/val/include/val_interface.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,12 +29,12 @@ #define AVS_PRINT_INFO 1 /* Print all statements. Do not use unless really needed */ -#define AVS_STATUS_FAIL 0x90000000 -#define AVS_STATUS_ERR 0xEDCB1234 //some impropable value? -#define AVS_STATUS_SKIP 0x10000000 -#define AVS_STATUS_PASS 0x0 - -#define AVS_INVALID_INDEX 0xFFFFFFFF +#define AVS_STATUS_FAIL 0x90000000 +#define AVS_STATUS_ERR 0xEDCB1234 //some impropable value? +#define AVS_STATUS_SKIP 0x10000000 +#define AVS_STATUS_PASS 0x0 +#define AVS_STATUS_NIST_PASS 0x1 +#define AVS_INVALID_INDEX 0xFFFFFFFF #define VAL_EXTRACT_BITS(data, start, end) ((data >> start) & ((1ul << (end-start+1))-1)) @@ -45,8 +45,10 @@ void val_print(uint32_t level, char8_t *string, uint64_t data); void val_print_raw(uint32_t level, char8_t *string, uint64_t data); void val_set_test_data(uint32_t index, uint64_t addr, uint64_t test_data); void val_get_test_data(uint32_t index, uint64_t *data0, uint64_t *data1); +uint32_t val_strncmp(char8_t *str1, char8_t *str2, uint32_t len); +void *val_memcpy(void *dest_buffer, void *src_buffer, uint32_t len); - +uint64_t val_time_delay_ms(uint64_t time_ms); /* VAL PE APIs */ uint32_t val_pe_execute_tests(uint32_t level, uint32_t num_pe); @@ -88,6 +90,8 @@ void val_gic_cpuif_init(void); uint32_t val_gic_request_irq(uint32_t irq_num, uint32_t mapped_irq_num, void *isr); void val_gic_free_irq(uint32_t irq_num, uint32_t mapped_irq_num); void val_gic_set_intr_trigger(uint32_t int_id, INTR_TRIGGER_INFO_TYPE_e trigger_type); +uint32_t val_gic_request_msi(uint32_t bdf, uint32_t IntID, uint32_t msi_index); +void val_gic_free_msi(uint32_t bdf, uint32_t IntID, uint32_t msi_index); /*TIMER VAL APIs */ typedef enum { @@ -143,14 +147,35 @@ void val_wd_set_ws0(uint32_t index, uint32_t timeout); /* PCIE VAL APIs */ void val_pcie_create_info_table(uint64_t *pcie_info_table); +uint32_t val_pcie_create_device_bdf_table(void); +addr_t val_pcie_get_ecam_base(uint32_t rp_bdf); +void *val_pcie_bdf_table_ptr(void); void val_pcie_free_info_table(void); -uint32_t val_pcie_execute_tests(uint32_t level, uint32_t num_pe); +uint32_t val_pcie_execute_tests(uint32_t enable_pcie, uint32_t level, uint32_t num_pe); uint32_t val_pcie_is_devicedma_64bit(uint32_t bdf); uint32_t val_pcie_scan_bridge_devices_and_check_memtype(uint32_t bdf); void val_pcie_read_ext_cap_word(uint32_t bdf, uint32_t ext_cap_id, uint8_t offset, uint16_t *val); uint32_t val_pcie_get_pcie_type(uint32_t bdf); uint32_t val_pcie_p2p_support(uint32_t bdf); uint32_t val_pcie_multifunction_support(uint32_t bdf); +uint32_t val_pcie_is_onchip_peripheral(uint32_t bdf); +uint32_t val_pcie_device_port_type(uint32_t bdf); +uint32_t val_pcie_find_capability(uint32_t bdf, uint32_t cid_type, + uint32_t cid, uint32_t *cid_offset); +void val_pcie_disable_bme(uint32_t bdf); +void val_pcie_enable_bme(uint32_t bdf); +void val_pcie_disable_msa(uint32_t bdf); +void val_pcie_enable_msa(uint32_t bdf); +void val_pcie_clear_urd(uint32_t bdf); +uint32_t val_pcie_is_urd(uint32_t bdf); +void val_pcie_disable_eru(uint32_t bdf); +uint32_t val_pcie_bitfield_check(uint32_t bdf, uint64_t *bf_entry); +uint32_t val_pcie_register_bitfields_check(uint64_t *bf_info_table, uint32_t table_size); +uint32_t val_pcie_function_header_type(uint32_t bdf); +void val_pcie_get_mmio_bar(uint32_t bdf, void *base); +uint32_t val_pcie_get_downstream_function(uint32_t bdf, uint32_t *dsf_bdf); +uint32_t val_pcie_get_rootport(uint32_t bdf, uint32_t *rp_bdf); +uint8_t val_pcie_parent_is_rootport(uint32_t dsf_bdf, uint32_t *rp_bdf); /* IO-VIRT APIs */ typedef enum { @@ -297,4 +322,7 @@ uint32_t val_secure_trusted_firmware_init(void); /* PCIe Exerciser tests */ uint32_t val_exerciser_execute_tests(uint32_t level); +/* NIST Statistical tests */ +uint32_t val_nist_execute_tests(uint32_t level, uint32_t num_pe); +uint32_t val_nist_generate_rng(uint32_t *rng_buffer); #endif diff --git a/val/src/avs_exerciser.c b/val/src/avs_exerciser.c index ebad2ba3..b0669502 100644 --- a/val/src/avs_exerciser.c +++ b/val/src/avs_exerciser.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -17,18 +17,56 @@ #include "include/sbsa_avs_val.h" #include "include/sbsa_avs_exerciser.h" +#include "include/sbsa_avs_pcie.h" +EXERCISER_INFO_TABLE g_exercier_info_table; /** @brief This API popultaes information from all the PCIe stimulus generation IP available in the system into exerciser_info_table structure @param exerciser_info_table - Table pointer to be filled by this API @return exerciser_info_table - Contains info to communicate with stimulus generation hardware **/ -void val_exerciser_create_info_table(EXERCISER_INFO_TABLE *exerciser_info_table) +void val_exerciser_create_info_table(void) { - pal_exerciser_create_info_table(exerciser_info_table); + uint32_t Bdf; + uint32_t reg_value; + uint32_t num_bdf; + pcie_device_bdf_table *bdf_table; + + bdf_table = val_pcie_bdf_table_ptr(); + /* if no bdf table ptr return error */ + if (bdf_table->num_entries == 0) + { + val_print(AVS_PRINT_ERR, "\n No BDFs discovered ", 0); + return; + } + + num_bdf = bdf_table->num_entries; + while (num_bdf-- != 0) + { + + Bdf = bdf_table->device[num_bdf].bdf; + /* Probe pcie device Function with this bdf */ + if (val_pcie_read_cfg(Bdf, TYPE01_VIDR, ®_value) == PCIE_NO_MAPPING) + { + /* Return if there is a bdf mapping issue */ + val_print(AVS_PRINT_ERR, "\n BDF 0x%x mapping issue", Bdf); + return; + } + + /* Store the Function's BDF if there was a valid response */ + if (reg_value == EXERCISER_ID) + { + g_exercier_info_table.e_info[g_exercier_info_table.num_exerciser].bdf = Bdf; + g_exercier_info_table.e_info[g_exercier_info_table.num_exerciser++].initialized = 0; + val_print(AVS_PRINT_DEBUG, " exerciser Bdf %x\n", Bdf); + } + } + val_print(AVS_PRINT_DEBUG, " exerciser cards in the system %x \n", + g_exercier_info_table.num_exerciser); } + /** @brief This API returns the requested information about the PCIe stimulus hardware @param type - Information type required from the stimulus hadrware @@ -37,7 +75,12 @@ void val_exerciser_create_info_table(EXERCISER_INFO_TABLE *exerciser_info_table) **/ uint32_t val_exerciser_get_info(EXERCISER_INFO_TYPE type, uint32_t instance) { - return pal_exerciser_get_info(type, instance); + switch (type) { + case EXERCISER_NUM_CARDS: + return g_exercier_info_table.num_exerciser; + default: + return 0; + } } /** @@ -48,11 +91,17 @@ uint32_t val_exerciser_get_info(EXERCISER_INFO_TYPE type, uint32_t instance) @param instance - Stimulus hardware instance number @return status - SUCCESS if the input paramter type is successfully written **/ -uint32_t val_exerciser_set_param(EXERCISER_PARAM_TYPE type, uint64_t value1, uint64_t value2, uint32_t instance) +uint32_t val_exerciser_set_param(EXERCISER_PARAM_TYPE type, uint64_t value1, uint64_t value2, + uint32_t instance) { - return pal_exerciser_set_param(type, value1, value2, instance); + return pal_exerciser_set_param(type, value1, value2, + g_exercier_info_table.e_info[instance].bdf); } +uint32_t val_exerciser_get_bdf(uint32_t instance) +{ + return g_exercier_info_table.e_info[instance].bdf; +} /** @brief This API reads the configuration parameters of the PCIe stimulus generation hardware @param type - Parameter type that needs to be read from the stimulus hadrware @@ -61,9 +110,12 @@ uint32_t val_exerciser_set_param(EXERCISER_PARAM_TYPE type, uint64_t value1, uin @param instance - Stimulus hardware instance number @return status - SUCCESS if the requested paramter type is successfully read **/ -uint32_t val_exerciser_get_param(EXERCISER_PARAM_TYPE type, uint64_t *value1, uint64_t *value2, uint32_t instance) +uint32_t val_exerciser_get_param(EXERCISER_PARAM_TYPE type, uint64_t *value1, uint64_t *value2, + uint32_t instance) { - return pal_exerciser_get_param(type, value1, value2, instance); + return pal_exerciser_get_param(type, value1, value2, + g_exercier_info_table.e_info[instance].bdf); + } /** @@ -75,21 +127,57 @@ uint32_t val_exerciser_get_param(EXERCISER_PARAM_TYPE type, uint64_t *value1, ui **/ uint32_t val_exerciser_set_state(EXERCISER_STATE state, uint64_t *value, uint32_t instance) { - return pal_exerciser_set_state(state, value, instance); + return pal_exerciser_set_state(state, value, g_exercier_info_table.e_info[instance].bdf); } /** @brief This API obtains the state of the PCIe stimulus generation hardware @param state - State that is read from the stimulus hadrware - @param value - Additional information associated with the state @param instance - Stimulus hardware instance number @return status - SUCCESS if the state is successfully read from hardware **/ -uint32_t val_exerciser_get_state(EXERCISER_STATE state, uint64_t *value, uint32_t instance) +uint32_t val_exerciser_get_state(EXERCISER_STATE *state, uint32_t instance) { - return pal_exerciser_get_state(state, value, instance); + return pal_exerciser_get_state(state, g_exercier_info_table.e_info[instance].bdf); } +/** + @brief This API obtains initializes + @param instance - Stimulus hardware instance number + @return status - SUCCESS if the state is successfully read from hardware +**/ +uint32_t val_exerciser_init(uint32_t instance) +{ + uint32_t Bdf; + uint32_t Ecam; + uint64_t cfg_addr; + EXERCISER_STATE state; + + if (!g_exercier_info_table.e_info[instance].initialized) + { + Bdf = g_exercier_info_table.e_info[instance].bdf; + if (pal_exerciser_get_state(&state, Bdf) || (state != EXERCISER_ON)) { + val_print(AVS_PRINT_ERR, "\n Exerciser Bdf %lx not ready", Bdf); + return 1; + } + + // setting command register for Memory Space Enable and Bus Master Enable + Ecam = val_pcie_get_ecam_base(Bdf); + + /* There are 8 functions / device, 32 devices / Bus and each has a 4KB config space */ + cfg_addr = (PCIE_EXTRACT_BDF_BUS(Bdf) * PCIE_MAX_DEV * PCIE_MAX_FUNC * 4096) + \ + (PCIE_EXTRACT_BDF_DEV(Bdf) * PCIE_MAX_FUNC * 4096) + \ + (PCIE_EXTRACT_BDF_FUNC(Bdf) * 4096); + + pal_mmio_write((Ecam + cfg_addr + COMMAND_REG_OFFSET), + (pal_mmio_read((Ecam + cfg_addr) + COMMAND_REG_OFFSET) | BUS_MEM_EN_MASK)); + + g_exercier_info_table.e_info[instance].initialized = 1; + } + else + val_print(AVS_PRINT_DEBUG, "\n Already initialized %d", instance); + return 0; +} /** @brief This API performs the input operation using the PCIe stimulus generation hardware @param ops - Operation thta needs to be performed with the stimulus hadrware @@ -99,7 +187,8 @@ uint32_t val_exerciser_get_state(EXERCISER_STATE state, uint64_t *value, uint32_ **/ uint32_t val_exerciser_ops(EXERCISER_OPS ops, uint64_t param, uint32_t instance) { - return pal_exerciser_ops(ops, param, instance); + return pal_exerciser_ops(ops, param, g_exercier_info_table.e_info[instance].bdf); + } /** @@ -109,9 +198,12 @@ uint32_t val_exerciser_ops(EXERCISER_OPS ops, uint64_t param, uint32_t instance) @param instance - Stimulus hardware instance number @return status - SUCCESS if the requested data is successfully filled **/ -uint32_t val_exerciser_get_data(EXERCISER_DATA_TYPE type, exerciser_data_t *data, uint32_t instance) +uint32_t val_exerciser_get_data(EXERCISER_DATA_TYPE type, exerciser_data_t *data, + uint32_t instance) { - return pal_exerciser_get_data(type, data, instance); + uint32_t bdf = g_exercier_info_table.e_info[instance].bdf; + uint64_t ecam = val_pcie_get_ecam_base(bdf); + return pal_exerciser_get_data(type, data, bdf, ecam); } /** @@ -138,19 +230,28 @@ val_exerciser_execute_tests(uint32_t level) } } + /* Create the list of valid Pcie Device Functions */ + if (val_pcie_create_device_bdf_table()) + return AVS_STATUS_SKIP; + + val_exerciser_create_info_table(); num_instances = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + if (num_instances == 0) { val_print(AVS_PRINT_INFO, " No exerciser cards in the system %x", 0); return AVS_STATUS_SKIP; } - status = e001_entry(); - status |= e002_entry(); - status |= e003_entry(); - status |= e004_entry(); - status |= e005_entry(); - status |= e006_entry(); - status |= e007_entry(); + status = e001_entry(); + status |= e002_entry(); + status |= e003_entry(); + status |= e004_entry(); + status |= e005_entry(); + status |= e006_entry(); + status |= e007_entry(); + status |= e008_entry(); + status |= e009_entry(); + status |= e010_entry(); if (status != AVS_STATUS_PASS) { val_print(AVS_PRINT_ERR, "\n One or more Exerciser tests have failed.... \n", status); diff --git a/val/src/avs_gic.c b/val/src/avs_gic.c index 99163e83..3d04415c 100644 --- a/val/src/avs_gic.c +++ b/val/src/avs_gic.c @@ -190,21 +190,6 @@ val_get_max_intid(void) return 32 * ((val_mmio_read(val_get_gicd_base() + 0x004) & 0x1F) + 1); } -/** - @brief This function writes to end of interrupt register for relevant - interrupt group. - 1. Caller - Test Suite - 2. Prerequisite - val_gic_create_info_table - @param int_id Interrupt ID for which to disable the interrupt - @return status -**/ -uint32_t val_gic_end_of_interrupt(uint32_t int_id) -{ - pal_gic_end_of_interrupt(int_id); - - return 0; -} - /** @brief This function routes interrupt to specific PE. 1. Caller - Test Suite diff --git a/val/src/avs_gic_support.c b/val/src/avs_gic_support.c index 8ead7299..4fd1b30d 100644 --- a/val/src/avs_gic_support.c +++ b/val/src/avs_gic_support.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -136,3 +136,46 @@ void val_gic_free_irq(uint32_t irq_num, uint32_t mapped_irq_num) { pal_gic_free_irq(irq_num, mapped_irq_num); } + +/** + @brief This function writes to end of interrupt register for relevant + interrupt group. + 1. Caller - Test Suite + 2. Prerequisite - val_gic_create_info_table + @param int_id Interrupt ID for which to disable the interrupt + @return status +**/ +uint32_t val_gic_end_of_interrupt(uint32_t int_id) +{ + pal_gic_end_of_interrupt(int_id); + + return 0; +} + +/** + @brief This function clear the MSI related mappings. + + @param bdf B:D:F for the device + @param IntID Interrupt ID + @param msi_index msi index in the table + + @return status +**/ +void val_gic_free_msi(uint32_t bdf, uint32_t IntID, uint32_t msi_index) +{ + pal_gic_free_msi(bdf, IntID, msi_index); +} + +/** + @brief This function creates the MSI mappings, and programs the MSI Table. + + @param bdf B:D:F for the device + @param IntID Interrupt ID + @param msi_index msi index in the table + + @return status +**/ +uint32_t val_gic_request_msi(uint32_t bdf, uint32_t IntID, uint32_t msi_index) +{ + return pal_gic_request_msi(bdf, IntID, msi_index); +} diff --git a/val/src/avs_iovirt.c b/val/src/avs_iovirt.c index d097a4c1..57b7a236 100644 --- a/val/src/avs_iovirt.c +++ b/val/src/avs_iovirt.c @@ -281,6 +281,6 @@ val_iovirt_get_rc_smmu_index(uint32_t rc_seg_num) } } - val_print(AVS_PRINT_ERR, "RC with segment number %d is not behind any SMMU", rc_seg_num); + val_print(AVS_PRINT_INFO, "RC with segment number %d is not behind any SMMU", rc_seg_num); return AVS_INVALID_INDEX; } diff --git a/val/src/avs_nist.c b/val/src/avs_nist.c new file mode 100644 index 00000000..f762a08f --- /dev/null +++ b/val/src/avs_nist.c @@ -0,0 +1,101 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "include/sbsa_avs_val.h" +#include "include/sbsa_avs_nist.h" +#include "include/sbsa_avs_common.h" +#include + +/** + @brief This API executes all the PCIe tests sequentially + @param level - level of compliance being tested for. + @param num_pe - the number of PE to run these tests on. + + @return Consolidated status of all the tests run. +**/ +uint32_t +val_nist_execute_tests(uint32_t level, uint32_t num_pe) +{ + uint32_t status, i; + + for (i = 0 ; i < MAX_TEST_SKIP_NUM ; i++) { + if (g_skip_test_num[i] == AVS_GIC_TEST_NUM_BASE) { + val_print(AVS_PRINT_TEST, " USER Override - Skipping all NIST tests \n", 0); + return AVS_STATUS_SKIP; + } + } + + status = n001_entry(num_pe); + if (status != AVS_STATUS_PASS) + val_print(AVS_PRINT_ERR, "\n NIST tests failed. Check Log \n", 0); + else + val_print(AVS_PRINT_TEST, "\n All NIST tests Passed!! \n", 0); + + return status; +} + +/** + @brief This API generates a 32 bit random number. + @param rng_buffer - Pointer to store the random data. + + @return success/failure. +**/ +uint32_t +val_nist_generate_rng(uint32_t *rng_buffer) +{ + uint32_t status; + + status = pal_nist_generate_rng(rng_buffer); + return status; +} + +double +erf(double x) +{ + // constants + double t, y; + double a1 = 0.254829592; + double a2 = -0.284496736; + double a3 = 1.421413741; + double a4 = -1.453152027; + double a5 = 1.061405429; + double p = 0.3275911; + // Save the sign of x + int sign = 1; + if (x < 0) + sign = -1; + x = fabs(x); + // A&S formula 7.1.26 + + t = 1.0/(1.0 + p*x); + y = 1.0 - (((((a5*t + a4)*t) + a3)*t + a2)*t + a1)*t*exp(-x*x); + return sign*y; +} + +double +erfc(double x) +{ + double t, z, ans; + z = fabs(x); + t = 1.0 / (1.0 + 0.5 * z); + + ans = t*exp(-z*z-1.26551223+t*(1.00002368+t*(0.37409196+t*(0.09678418+ + t*(-0.18628806+t*(0.27886807+t*(-1.13520398+t*(1.48851587+ + t*(-0.82215223+t*0.17087277))))))))); + + return x >= 0.0 ? ans : 2.0-ans; +} diff --git a/val/src/avs_pcie.c b/val/src/avs_pcie.c index 1323f401..e5c5242f 100644 --- a/val/src/avs_pcie.c +++ b/val/src/avs_pcie.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -20,7 +20,9 @@ #include "include/sbsa_avs_pcie.h" +#define WARN_STR_LEN 7 PCIE_INFO_TABLE *g_pcie_info_table; +pcie_device_bdf_table *g_pcie_bdf_table; uint64_t pal_get_mcfg_ptr(void); @@ -50,12 +52,12 @@ val_pcie_read_cfg(uint32_t bdf, uint32_t offset, uint32_t *data) if ((bus >= PCIE_MAX_BUS) || (dev >= PCIE_MAX_DEV) || (func >= PCIE_MAX_FUNC)) { val_print(AVS_PRINT_ERR, "Invalid Bus/Dev/Func %x \n", bdf); - return PCIE_READ_ERR; + return PCIE_NO_MAPPING; } if (g_pcie_info_table == NULL) { val_print(AVS_PRINT_ERR, "\n Read_PCIe_CFG: PCIE info table is not created", 0); - return PCIE_READ_ERR; + return PCIE_NO_MAPPING; } while (i < val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0)) @@ -72,7 +74,7 @@ val_pcie_read_cfg(uint32_t bdf, uint32_t offset, uint32_t *data) if (ecam_base == 0) { val_print(AVS_PRINT_ERR, "\n Read PCIe_CFG: ECAM Base is zero ", 0); - return PCIE_READ_ERR; + return PCIE_NO_MAPPING; } /* There are 8 functions / device, 32 devices / Bus and each has a 4KB config space */ @@ -160,17 +162,74 @@ val_pcie_write_cfg(uint32_t bdf, uint32_t offset, uint32_t data) pal_mmio_write(ecam_base + cfg_addr + offset, data); } +/** + @brief This API returns function config space addr. + 1. Caller - Test Suite + 2. Prerequisite - val_pcie_create_info_table + @param bdf - concatenated Bus(8-bits), device(8-bits) & function(8-bits) + + @return function config space address +**/ +uint32_t val_pcie_get_bdf_config_addr(uint32_t bdf) +{ + uint32_t bus = PCIE_EXTRACT_BDF_BUS(bdf); + uint32_t dev = PCIE_EXTRACT_BDF_DEV(bdf); + uint32_t func = PCIE_EXTRACT_BDF_FUNC(bdf); + uint32_t segment = PCIE_EXTRACT_BDF_SEG(bdf); + uint32_t cfg_addr; + uint32_t num_ecam; + addr_t ecam_base = 0; + uint32_t i = 0; + + + if ((bus >= PCIE_MAX_BUS) || (dev >= PCIE_MAX_DEV) || (func >= PCIE_MAX_FUNC)) { + val_print(AVS_PRINT_ERR, "Invalid Bus/Dev/Func %x \n", bdf); + return 0; + } + + if (g_pcie_info_table == NULL) { + val_print(AVS_PRINT_ERR, "\n Write PCIe_CFG: PCIE info table is not created", 0); + return 0; + } + + num_ecam = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); + while (i < num_ecam) + { + + if ((bus >= val_pcie_get_info(PCIE_INFO_START_BUS, i)) && + (bus <= val_pcie_get_info(PCIE_INFO_END_BUS, i)) && + (segment == val_pcie_get_info(PCIE_INFO_SEGMENT, i))) { + ecam_base = val_pcie_get_info(PCIE_INFO_ECAM, i); + break; + } + i++; + } + + if (ecam_base == 0) { + val_print(AVS_PRINT_ERR, "\n Read PCIe_CFG: ECAM Base is zero ", 0); + return 0; + } + + /* There are 8 functions / device, 32 devices / Bus and each has a 4KB config space */ + cfg_addr = (bus * PCIE_MAX_DEV * PCIE_MAX_FUNC * 4096) + \ + (dev * PCIE_MAX_FUNC * 4096) + (func * 4096); + + return ecam_base + cfg_addr; + +} + /** @brief This API executes all the PCIe tests sequentially 1. Caller - Application layer. 2. Prerequisite - val_pcie_create_info_table() - @param level - level of compliance being tested for. - @param num_pe - the number of PE to run these tests on. + @param enable_pcie - Flag to enable PCIe SBSA 6.0 (RCiEP) compliance Test + @param level - level of compliance being tested for. + @param num_pe - the number of PE to run these tests on. @return Consolidated status of all the tests run. **/ uint32_t -val_pcie_execute_tests(uint32_t level, uint32_t num_pe) +val_pcie_execute_tests(uint32_t enable_pcie, uint32_t level, uint32_t num_pe) { uint32_t status, i; @@ -186,7 +245,6 @@ val_pcie_execute_tests(uint32_t level, uint32_t num_pe) } } - status = p001_entry(num_pe); if (status != AVS_STATUS_PASS) { @@ -195,34 +253,67 @@ val_pcie_execute_tests(uint32_t level, uint32_t num_pe) } status |= p002_entry(num_pe); - status |= p003_entry(num_pe); - #ifdef TARGET_LINUX status |= p004_entry(num_pe); status |= p005_entry(num_pe); status |= p006_entry(num_pe); status |= p007_entry(num_pe); status |= p008_entry(num_pe); - status |= p011_entry(num_pe); - status |= p012_entry(num_pe); - status |= p015_entry(num_pe); if (level > 1) { status |= p009_entry(num_pe); } + status |= p011_entry(num_pe); + status |= p012_entry(num_pe); + if (level > 2) { status |= p010_entry(num_pe); status |= p013_entry(num_pe); status |= p014_entry(num_pe); } + status |= p015_entry(num_pe); + if (level > 3) { status |= p016_entry(num_pe); status |= p017_entry(num_pe); status |= p018_entry(num_pe); status |= p019_entry(num_pe); } +#else + /* Create the list of valid Pcie Device Functions */ + if (val_pcie_create_device_bdf_table()) + return AVS_STATUS_SKIP; + + if (enable_pcie) { + status |= p020_entry(num_pe); + status |= p021_entry(num_pe); + status |= p022_entry(num_pe); + status |= p023_entry(num_pe); + status |= p024_entry(num_pe); + status |= p025_entry(num_pe); + status |= p026_entry(num_pe); + status |= p027_entry(num_pe); + status |= p028_entry(num_pe); + status |= p029_entry(num_pe); + status |= p030_entry(num_pe); + status |= p031_entry(num_pe); + status |= p032_entry(num_pe); + status |= p033_entry(num_pe); + status |= p034_entry(num_pe); + status |= p035_entry(num_pe); + status |= p036_entry(num_pe); + status |= p037_entry(num_pe); + status |= p038_entry(num_pe); + status |= p039_entry(num_pe); + status |= p040_entry(num_pe); + status |= p041_entry(num_pe); + status |= p042_entry(num_pe); + status |= p043_entry(num_pe); + status |= p044_entry(num_pe); + status |= p045_entry(num_pe); + } #endif if (status != AVS_STATUS_PASS) { @@ -258,6 +349,159 @@ val_pcie_create_info_table(uint64_t *pcie_info_table) val_print(AVS_PRINT_TEST, " PCIE_INFO: Number of ECAM regions : %lx \n", val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0)); } +/** + @brief Sanity checks that all Endpoints must have a Rootport + + @param None + @return 0 if sanity check passes, 1 if sanity check fails +**/ +static uint32_t val_pcie_populate_device_rootport(void) +{ + uint32_t bdf; + uint32_t rp_bdf; + uint32_t tbl_index; + pcie_device_bdf_table *bdf_tbl_ptr; + + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + tbl_index = 0; + + for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++) + { + bdf = bdf_tbl_ptr->device[tbl_index].bdf; + val_print(AVS_PRINT_DEBUG, "\n device bdf 0x%x", bdf); + + /* Fn returns 1 if RP not foud */ + val_pcie_get_rootport(bdf, &rp_bdf); + bdf_tbl_ptr->device[tbl_index].rp_bdf = rp_bdf; + val_print(AVS_PRINT_DEBUG, " RP bdf 0x%x", rp_bdf); + } + return 0; +} + +uint32_t +val_pcie_create_device_bdf_table() +{ + + uint32_t num_ecam; + uint32_t seg_num; + uint32_t start_bus; + uint32_t end_bus; + uint32_t bus_index; + uint32_t dev_index; + uint32_t func_index; + uint32_t ecam_index; + uint32_t bdf; + uint32_t reg_value; + + /* if table is already present, return success */ + if (g_pcie_bdf_table) + return PCIE_SUCCESS; + + /* Allocate memory to store BDFs for the valid pcie device functions */ + g_pcie_bdf_table = (pcie_device_bdf_table *) pal_mem_alloc(PCIE_DEVICE_BDF_TABLE_SZ); + if (!g_pcie_bdf_table) + { + val_print(AVS_PRINT_ERR, "\n PCIe BDF table memory allocation failed ", 0); + return 1; + } + + num_ecam = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); + if (num_ecam == 0) + { + val_print(AVS_PRINT_ERR, "\n No ECAMs discovered ", 0); + return 1; + } + + g_pcie_bdf_table->num_entries = 0; + + for (ecam_index = 0; ecam_index < num_ecam; ecam_index++) + { + /* Derive ecam specific information */ + seg_num = val_pcie_get_info(PCIE_INFO_SEGMENT, ecam_index); + start_bus = val_pcie_get_info(PCIE_INFO_START_BUS, ecam_index); + end_bus = val_pcie_get_info(PCIE_INFO_END_BUS, ecam_index); + + /* Iterate over all buses, devices and functions in this ecam */ + for (bus_index = start_bus; bus_index <= end_bus; bus_index++) + { + for (dev_index = 0; dev_index < PCIE_MAX_DEV; dev_index++) + { + for (func_index = 0; func_index < PCIE_MAX_FUNC; func_index++) + { + /* Form bdf using seg, bus, device, function numbers */ + bdf = PCIE_CREATE_BDF(seg_num, bus_index, dev_index, func_index); + + /* Probe pcie device Function with this bdf */ + if (val_pcie_read_cfg(bdf, TYPE01_VIDR, ®_value) == PCIE_NO_MAPPING) + { + /* Return if there is a bdf mapping issue */ + val_print(AVS_PRINT_ERR, "\n BDF 0x%x mapping issue", bdf); + return 1; + } + + /* Store the Function's BDF if there was a valid response */ + if (reg_value != PCIE_UNKNOWN_RESPONSE) + g_pcie_bdf_table->device[g_pcie_bdf_table->num_entries++].bdf = bdf; + else + /* None of the other Function's exist if zeroth Function doesn't exist */ + if (func_index == 0) + break; + } + } + } + } + + val_print(AVS_PRINT_INFO, "\n Number of valid BDFs is %x\n", g_pcie_bdf_table->num_entries); + /* Sanity Check : Confirm all EP (normal, integrated) have a rootport */ + return val_pcie_populate_device_rootport(); + +} + +/** + @brief Returns the ECAM address of the input PCIe bridge function + + @param bdf - Segment/Bus/Dev/Func in PCIE_CREATE_BDF format + @return ECAM address if success, else NULL address +**/ +addr_t val_pcie_get_ecam_base(uint32_t bdf) +{ + + uint8_t ecam_index; + uint8_t sec_bus; + uint8_t sub_bus; + uint16_t seg_num; + uint32_t reg_value; + addr_t ecam_base; + + ecam_index = 0; + ecam_base = 0; + + val_pcie_read_cfg(bdf, TYPE1_PBN, ®_value); + sec_bus = ((reg_value >> SECBN_SHIFT) & SECBN_MASK); + sub_bus = ((reg_value >> SUBBN_SHIFT) & SUBBN_MASK); + seg_num = PCIE_EXTRACT_BDF_SEG(bdf); + + while (ecam_index < val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0)) + { + if ((sec_bus >= val_pcie_get_info(PCIE_INFO_START_BUS, ecam_index)) && + (sub_bus <= val_pcie_get_info(PCIE_INFO_END_BUS, ecam_index)) && + (seg_num == val_pcie_get_info(PCIE_INFO_SEGMENT, ecam_index))) + { + ecam_base = val_pcie_get_info(PCIE_INFO_ECAM, ecam_index); + break; + } + ecam_index++; + } + + return ecam_base; +} + +void * +val_pcie_bdf_table_ptr() +{ + return g_pcie_bdf_table; +} + /** @brief Free the memory allocated for the pcie_info_table **/ @@ -647,3 +891,763 @@ val_pcie_read_ext_cap_word(uint32_t bdf, uint32_t ext_cap_id, uint8_t offset, ui PCIE_EXTRACT_BDF_FUNC(bdf), ext_cap_id, offset, val); } + +/** + @brief Returns whether a PCIe Function is an on-chip peripheral or not + + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @return Returns TRUE if the Function is on-chip peripheral, FALSE if it is + not an on-chip peripheral +**/ +uint32_t +val_pcie_is_onchip_peripheral(uint32_t bdf) +{ + /* TO DO */ + //return pal_pcie_is_onchip_peripheral(bdf); + return 0; +} + +/** + @brief Returns whether a PCIe Function is atomicop requester capable + + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @return Returns 0 (if Function doesn't supports atomicop requester capable + else non-zero value) +**/ +uint32_t +val_pcie_get_atomicop_requester_capable(uint32_t bdf) +{ + /* TO DO */ + //return pal_pcie_get_atomicop_requester_capable(bdf); + return 0; +} + +/** + @brief Returns the type of pcie device or port for the given bdf + + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @return Returns (1 << 0b1001) for RCiEP, (1 << 0b1010) for RCEC, + (1 << 0b0000) for EP, (1 << 0b0100) for RP, + (1 << 0b1100) for iEP_EP, (1 << 0b1011) for iEP_RP, + (1 << PCIECR[7:4]) for any other device type. +**/ +uint32_t +val_pcie_device_port_type(uint32_t bdf) +{ + + uint32_t pciecs_base; + uint32_t reg_value; + uint32_t dp_type; + + /* Get the PCI Express Capability structure offset and + * use that offset to read pci express capabilities register + */ + val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &pciecs_base); + val_pcie_read_cfg(bdf, pciecs_base + CIDR_OFFSET, ®_value); + + /* Read Device/Port bits [7:4] in Function's PCIe Capabilities register */ + dp_type = (reg_value >> ((PCIECR_OFFSET - CIDR_OFFSET)*8 + + PCIECR_DPT_SHIFT)) & PCIECR_DPT_MASK; + dp_type = (1 << dp_type); + + /* Check if the device/port is an on-chip peripheral */ + if (val_pcie_is_onchip_peripheral(bdf)) + { + if (dp_type == EP) + dp_type = iEP_EP; + else if (dp_type == RP) + dp_type = iEP_RP; + } + + /* Return device/port type */ + return dp_type; +} + +/** + @brief Find a Function's config capability offset matching it's input parameter + cid. cid_offset set to the matching cpability offset w.r.t. zero. + + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @param cid - Capability ID + @param cid_offset - On return, points to cid offset in Function config space + @return PCIE_CAP_NOT_FOUND, if there was a failure in finding required capability. + PCIE_SUCCESS, if the search was successful. +**/ +uint32_t +val_pcie_find_capability(uint32_t bdf, uint32_t cid_type, uint32_t cid, uint32_t *cid_offset) +{ + + uint32_t reg_value; + uint32_t next_cap_offset; + + if (cid_type == PCIE_CAP) { + + /* Serach in PCIe configuration space */ + val_pcie_read_cfg(bdf, TYPE01_CPR, ®_value); + next_cap_offset = (reg_value & TYPE01_CPR_MASK); + while (next_cap_offset) + { + val_pcie_read_cfg(bdf, next_cap_offset, ®_value); + if ((reg_value & PCIE_CIDR_MASK) == cid) + { + *cid_offset = next_cap_offset; + return PCIE_SUCCESS; + } + next_cap_offset = ((reg_value >> PCIE_NCPR_SHIFT) & PCIE_NCPR_MASK); + } + } else if (cid_type == PCIE_ECAP) + { + + /* Serach in PCIe extended configuration space */ + next_cap_offset = PCIE_ECAP_START; + while (next_cap_offset) + { + val_pcie_read_cfg(bdf, next_cap_offset, ®_value); + if ((reg_value & PCIE_ECAP_CIDR_MASK) == cid) + { + *cid_offset = next_cap_offset; + return PCIE_SUCCESS; + } + next_cap_offset = ((reg_value >> PCIE_ECAP_NCPR_SHIFT) & PCIE_ECAP_NCPR_MASK); + } + } + + /* The capability was not found */ + return PCIE_CAP_NOT_FOUND; +} + +/** + @brief Disables bus master by clearing Bus Master Enable bit in the command register. + When BME bit is clear, it disables the ability of a Function to issue Memory + Read/Write Requests, and the ability of a Port to forward Memory Read/Write + Requests in the Upstream direction. + + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @return None +**/ +void +val_pcie_disable_bme(uint32_t bdf) +{ + + uint32_t reg_value; + uint32_t dis_mask; + + /* Clear BME bit in Command Register to disable ability to issue Memory Requests */ + val_pcie_read_cfg(bdf, TYPE01_CR, ®_value); + dis_mask = ~(1 << CR_BME_SHIFT); + val_pcie_write_cfg(bdf, TYPE01_CR, reg_value & dis_mask); + +} + +/** + @brief Gets RP support of transaction forwarding. + + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @return 0 if rp not involved in transaction forwarding +**/ +uint32_t +val_pcie_get_rp_transaction_frwd_support(uint32_t bdf) +{ + /* TO DO */ + //return pal_get_rp_transaction_frwd_support(bdf); + return 0; +} + +/** + @brief Enables ability of a function to issue Memory Requests by setting Bus + Master Enable bit in the command register. + + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @return None +**/ +void +val_pcie_enable_bme(uint32_t bdf) +{ + + uint32_t reg_value; + + /* Set BME bit in Command Register to enable ability to issue Memory Requests */ + val_pcie_read_cfg(bdf, TYPE01_CR, ®_value); + val_pcie_write_cfg(bdf, TYPE01_CR, reg_value | (1 << CR_BME_SHIFT)); + +} + +/** + @brief Disables BAR memory space access by clearring memory space enable bit + in the command register. When MSE bit is clear, all received memory + space accesses are caused to be handled as Unsupported Requests. + + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @return None +**/ +void +val_pcie_disable_msa(uint32_t bdf) +{ + + uint32_t reg_value; + uint32_t dis_mask; + + /* Clear MSE bit in Command Register to disable BAR memory space accesses */ + val_pcie_read_cfg(bdf, TYPE01_CR, ®_value); + dis_mask = ~(1 << CR_MSE_SHIFT); + val_pcie_write_cfg(bdf, TYPE01_CR, reg_value & dis_mask); + +} + +/** + @brief Enables BAR memory space access by setting memory space enable bit + in the command register. When MSE bit is Set, the Function is enabled + to decode the address and further process Memory Space accesses. + + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @return None +**/ +void +val_pcie_enable_msa(uint32_t bdf) +{ + + uint32_t reg_value; + + /* Enable MSE bit in Command Register to enable BAR memory space accesses */ + val_pcie_read_cfg(bdf, TYPE01_CR, ®_value); + val_pcie_write_cfg(bdf, TYPE01_CR, reg_value | (1 << CR_MSE_SHIFT)); + +} + +/** + @brief Clears unsupported request detected bit in Device Status Register + + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @return None +**/ +void +val_pcie_clear_urd(uint32_t bdf) +{ + + uint32_t pciecs_base; + uint32_t reg_value; + + /* + * Get the PCI Express Capability structure offset and use that + * offset to write 1b to clear URD bit in Device Status register + */ + reg_value = (1 << (DCTLR_DSR_SHIFT + DSR_URD_SHIFT)); + val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &pciecs_base); + val_pcie_write_cfg(bdf, pciecs_base + DCTLR_OFFSET, reg_value); + +} + +/** + @brief Returns whether a PCIe Function has detected an Unsupported Request + + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @return Returns TRUE if the Function has received an Unsupported Request or + FALSE if it does not receive Unsupported Request +**/ +uint32_t +val_pcie_is_urd(uint32_t bdf) +{ + + uint32_t pciecs_base; + uint32_t reg_value; + + /* Get the PCI Express Capability structure offset and + * use that offset to read the Device Status register + */ + val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &pciecs_base); + val_pcie_read_cfg(bdf, pciecs_base + DCTLR_OFFSET, ®_value); + + /* Check if URD bit is set in Function's Device Control register */ + reg_value = (reg_value >> DCTLR_DSR_SHIFT) & DCTLR_DSR_MASK; + if ((reg_value >> DSR_URD_SHIFT) & DSR_URD_MASK) + return 1; + + /* Hasn't received UR */ + return 0; +} + +/** + @brief Disable error reporting of the PCIe Function to the upstream + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @return None +**/ +void +val_pcie_disable_eru(uint32_t bdf) +{ + + uint32_t reg_value; + uint32_t dis_mask; + uint32_t pciecs_base; + + /* Clear SERR# Enable bit in the Command Register to disable reporting + * upstream of Non-fatal and Fatal errors detected by the Function. + */ + val_pcie_read_cfg(bdf, TYPE01_CR, ®_value); + dis_mask = ~(1 << CR_SERRE_SHIFT); + val_pcie_write_cfg(bdf, TYPE01_CR, reg_value & dis_mask); + + /* Get the PCI Express Capability structure offset and + * use that offset to read the Device Control register + */ + val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &pciecs_base); + val_pcie_read_cfg(bdf, pciecs_base + DCTLR_OFFSET, ®_value); + + /* Clear Correctable, Non-fatal, Fatal, UR Reporting Enable bits in the + * Device Control Register to disable reporting upstream of these errors + * detected by the Function. + */ + dis_mask = ~(1 << DCTLR_CERE_SHIFT | + 1 << DCTLR_NFERE_SHIFT | + 1 << DCTLR_FERE_SHIFT | + 1 << DCTLR_URRE_SHIFT); + val_pcie_write_cfg(bdf, pciecs_base + DCTLR_OFFSET, reg_value & dis_mask); +} + +/** + @brief Returns whether a device's bit-field passed the compliance check or not. + The device under test is indicated by input bdf. + + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @param bitfield_entry- Expected bit-field entry configuration for the comparison + @return Return 0 for success, else 1 for failure. +**/ +uint32_t val_pcie_bitfield_check(uint32_t bdf, uint64_t *bitfield_entry) +{ + + uint32_t bf_value; + uint32_t cap_base; + uint32_t reg_value; + uint32_t reg_offset; + uint32_t temp_reg_value; + uint32_t reg_overwrite_value; + uint32_t alignment_byte_cnt; + pcie_cfgreg_bitfield_entry *bf_entry; + + bf_entry = (pcie_cfgreg_bitfield_entry *)bitfield_entry; + + /* + * Calculate word alignment byte count and adjust + * reg_offset to read word-aligned offsets always. + */ + reg_offset = bf_entry->reg_offset; + alignment_byte_cnt = (reg_offset & WORD_ALIGN_MASK); + reg_offset = reg_offset - alignment_byte_cnt; + + switch (bf_entry->reg_type) + { + case HEADER: + cap_base = 0; + break; + case PCIE_CAP: + val_pcie_find_capability(bdf, PCIE_CAP, bf_entry->cap_id, &cap_base); + break; + case PCIE_ECAP: + val_pcie_find_capability(bdf, PCIE_ECAP, bf_entry->ecap_id, &cap_base); + break; + default: + val_print(AVS_PRINT_ERR, "\n Invalid reg_type : 0x%x ", bf_entry->reg_type); + return 1; + } + + + /* Derive bit-field of interest from the register value */ + val_pcie_read_cfg(bdf, cap_base + reg_offset, ®_value); + bf_value = (reg_value >> REG_SHIFT(alignment_byte_cnt, bf_entry->start)) & + REG_MASK(bf_entry->end, bf_entry->start); + + /* Check if bit-field value is proper */ + if (bf_value != bf_entry->cfg_value) + { + val_print(AVS_PRINT_ERR, "\n BDF 0x%x : ", bdf); + val_print(AVS_PRINT_ERR, bf_entry->err_str1, 0); + if (!val_strncmp(bf_entry->err_str1, "WARNING", WARN_STR_LEN)) + return 0; + return 1; + } + + /* Check if bit-field attribute is proper */ + switch (bf_entry->attr) + { + case HW_INIT: + case READ_ONLY: + case STICKY_RO: + /* Software must not alter these bits */ + reg_overwrite_value = reg_value ^ (REG_MASK(bf_entry->end, bf_entry->start) << + REG_SHIFT(alignment_byte_cnt, bf_entry->start)); + val_pcie_write_cfg(bdf, cap_base + reg_offset, reg_overwrite_value); + val_pcie_read_cfg(bdf, cap_base + reg_offset, ®_overwrite_value); + break; + case RSVDP_RO: + /* Software must preserve the value read to write to these bits */ + reg_overwrite_value = reg_value; + val_pcie_write_cfg(bdf, cap_base + reg_offset, reg_overwrite_value); + val_pcie_read_cfg(bdf, cap_base + reg_offset, ®_overwrite_value); + /* Software must return 0 when read */ + reg_value = 0; + break; + case RSVDZ_RO: + /* Software must use 0b to write to these bits */ + reg_overwrite_value = reg_value & (~(REG_MASK(bf_entry->end, bf_entry->start) << + REG_SHIFT(alignment_byte_cnt, bf_entry->start))); + val_pcie_write_cfg(bdf, cap_base + reg_offset, reg_overwrite_value); + val_pcie_read_cfg(bdf, cap_base + reg_offset, ®_overwrite_value); + break; + case READ_WRITE: + case STICKY_RW: + /* Software can alter these bits, toggle the required bits and write to register */ + temp_reg_value = reg_value; + reg_overwrite_value = reg_value ^ (REG_MASK(bf_entry->end, bf_entry->start) << + REG_SHIFT(alignment_byte_cnt, bf_entry->start)); + val_pcie_write_cfg(bdf, cap_base + reg_offset, reg_overwrite_value); + val_pcie_read_cfg(bdf, cap_base + reg_offset, ®_value); + /* Restore the original register value */ + val_pcie_write_cfg(bdf, cap_base + reg_offset, temp_reg_value); + break; + default: + val_print(AVS_PRINT_ERR, "\n Invalid Attribute : 0x%x ", bf_entry->attr); + return 1; + } + + if (reg_overwrite_value != reg_value) + { + val_print(AVS_PRINT_ERR, "\n BDF 0x%x : ", bdf); + val_print(AVS_PRINT_ERR, bf_entry->err_str2, 0); + if (!val_strncmp(bf_entry->err_str2, "WARNING", WARN_STR_LEN)) + return 0; + return 1; + } + + /* Return pass status */ + val_print(AVS_PRINT_INFO, "\n BDF 0x%x : PASS", bdf); + return 0; +} + +/** + @brief Returns if a PCIe config register bitfields are as per sbsa specification. + + @param bf_info_table - table of registers and their bit-fields for checking + @return Return 0 for success + AVS_STATUS_SKIP if no checks are executed + number of failures. +**/ +uint32_t +val_pcie_register_bitfields_check(uint64_t *bf_info_table, uint32_t num_bitfield_entries) +{ + + uint32_t bdf; + uint16_t dp_type; + uint32_t tbl_index; + uint32_t num_fails; + uint32_t num_pass; + uint32_t index; + pcie_cfgreg_bitfield_entry *bf_entry; + + num_fails = num_pass = tbl_index = 0; + + val_print(AVS_PRINT_INFO, "\n Number of bit-field entries to check %d", + num_bitfield_entries); + + while (tbl_index < g_pcie_bdf_table->num_entries) + { + bdf = g_pcie_bdf_table->device[tbl_index++].bdf; + + /* Disable error reporting of this Function to the Upstream */ + val_pcie_disable_eru(bdf); + + /* Get the Function's device/port type from bdf */ + dp_type = val_pcie_device_port_type(bdf); + + /* Set variables to iterate over all bit-field entries */ + bf_entry = (pcie_cfgreg_bitfield_entry *)&(bf_info_table[0]); + + for (index = 0; index < num_bitfield_entries; index++) + { + /* + * Skip this entry checking, if the Function + * is not part of it's device/port bit mask. + */ + if (!(dp_type & bf_entry->dev_port_bitmask)) + { + bf_entry++; + continue; + } + + /* Check for the compliance */ + if (val_pcie_bitfield_check(bdf, (void *)bf_entry)) + num_fails++; + else + num_pass++; + + /* Adjust the pointer to next bf */ + bf_entry++; + } + } + + /* Return register check status */ + if (num_pass > 0 || num_fails > 0) + return num_fails; + else + return AVS_STATUS_SKIP; +} + +/** + @brief Returns the header type of the input pcie device function + + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @return TYPE0_HEADER for functions with Type 0 config space header, + TYPE1_HEADER for functions with Type 1 config space header, +*/ +uint32_t +val_pcie_function_header_type(uint32_t bdf) +{ + + uint32_t reg_value; + + /* Read four bytes of config space starting from cache line size register */ + val_pcie_read_cfg(bdf, TYPE01_CLSR, ®_value); + + /* Extract header type register value */ + reg_value = ((reg_value >> TYPE01_HTR_SHIFT) & TYPE01_HTR_MASK); + + /* Header layout bits within header type register indicate the header type */ + return ((reg_value >> HTR_HL_SHIFT) & HTR_HL_MASK); +} + +/** + @brief Returns physical address of the first MMIO Base Address Register + + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @param base - Base Address Register address in 64-bit format + @return BAR address in 64-bit format, if found. Else NULL pointer. +**/ +void +val_pcie_get_mmio_bar(uint32_t bdf, void *base) +{ + + uint32_t index; + uint32_t *base_ptr; + uint32_t bar_low32bits; + uint32_t bar_high32bits; + + index = 0; + base_ptr = (uint32_t *) base; + while (index < TYPE0_MAX_BARS) + { + /* Read the base address register at loop index */ + val_pcie_read_cfg(bdf, TYPE01_BAR + index, &bar_low32bits); + + /* Check if the BAR is Memory Mapped IO type */ + if (((bar_low32bits >> BAR_MIT_SHIFT) & BAR_MIT_MASK) == MMIO) + { + /* Check if the BAR is 64-bit decodable */ + if (((bar_low32bits >> BAR_MDT_SHIFT) & BAR_MDT_MASK) == BITS_64) + { + /* Read the second sequential BAR at next index */ + val_pcie_read_cfg(bdf, TYPE01_BAR + index + 1, &bar_high32bits); + + /* Fill upper 32-bits of 64-bit address with second sequential BAR */ + base_ptr[1] = bar_high32bits; + + /* Adjust the index to skip next sequential BAR */ + index++; + + } else if (((bar_low32bits >> BAR_MDT_SHIFT) & BAR_MDT_MASK) == BITS_32) + { + /* Fill upper 32-bits of 64-bit address with zeros */ + base_ptr[1] = 0; + } + + /* Fill lower 32-bits of 64-bit address with first sequential BAR */ + base_ptr[0] = ((bar_low32bits >> (BAR_BASE_SHIFT) & BAR_BASE_MASK)) << BAR_BASE_SHIFT; + + return; + } + + /* Adjust index to point to next BAR */ + index++; + + /* + * Functions that implement Type 1 configuration header are limited by two BARs. + * Terminate the search after index reaches max Type 1 BARs. The header layout bits + * in header type register provide the type of the configuration header. + */ + if ((val_pcie_function_header_type(bdf) == TYPE1_HEADER) && (index == TYPE1_MAX_BARS)) + break; + + } + + /* Return NULL pointer to indicate unavailablity of mmio BAR */ + base_ptr[0] = 0; + base_ptr[1] = 0; + +} + +/** + @brief Returns BDF of first found downstream Function of a pcie bridge device. + The search is in the order of type 0 followed by type 1 functions. + + @param bdf - Bridge's Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @param dsf_bdf - Bridge's downstream function bdf in PCIE_CREATE_BDF format + @return 0 for success, 1 for failure. +**/ +uint32_t +val_pcie_get_downstream_function(uint32_t bdf, uint32_t *dsf_bdf) +{ + + uint32_t index; + uint32_t sec_bus; + uint32_t sub_bus; + uint32_t reg_value; + uint32_t type1_bdf; + uint32_t type1_flag; + + type1_bdf = 0; + *dsf_bdf = 0; + type1_flag = 0; + + /* + * Read four bytes of config space starting from Primary Bus num + * register and extract the Secondary and Subordinate Bus numbers. + */ + val_pcie_read_cfg(bdf, TYPE1_PBN, ®_value); + sec_bus = ((reg_value >> SECBN_SHIFT) & SECBN_MASK); + sub_bus = ((reg_value >> SUBBN_SHIFT) & SUBBN_MASK); + + /* + * Search for a pcie Function whose bus number is within the range of + * target bridge's bus numbers downstream, from the value of Secondary + * Bus number to the Subordinate Bus number, inclusive. + * + */ + index = 0; + while (index < g_pcie_bdf_table->num_entries) + { + if (((PCIE_EXTRACT_BDF_BUS(g_pcie_bdf_table->device[index].bdf)) >= sec_bus) && + ((PCIE_EXTRACT_BDF_BUS(g_pcie_bdf_table->device[index].bdf)) <= sub_bus)) + { + *dsf_bdf = g_pcie_bdf_table->device[index].bdf; + + /* Return the bdf of first found type 0 function */ + if (val_pcie_function_header_type(*dsf_bdf) == TYPE0_HEADER) + return 0; + else if (!type1_flag) + { + type1_flag++; + type1_bdf = *dsf_bdf; + } + } + + index++; + } + + /* Return the bdf of first found type 1 function */ + if (type1_flag) + { + *dsf_bdf = type1_bdf; + return 0; + } + + /* Return failure */ + return 1; + +} + +/** + @brief Returns BDF of the upstream Root Port of a pcie device function. + + @param bdf - Function's Segment/Bus/Dev/Func in PCIE_CREATE_BDF format + @param usrp_bdf - Upstream Rootport bdf in PCIE_CREATE_BDF format + @return 0 for success, 1 for failure. +**/ +uint32_t +val_pcie_get_rootport(uint32_t bdf, uint32_t *rp_bdf) +{ + + uint32_t index; + uint32_t sec_bus; + uint32_t sub_bus; + uint32_t reg_value; + uint32_t dp_type; + + index = 0; + + dp_type = val_pcie_device_port_type(bdf); + + val_print(AVS_PRINT_DEBUG, " DP type 0x%x ", dp_type); + + /* If the device is RP, set its rootport value to same */ + if (dp_type == RP) + { + *rp_bdf = bdf; + return 0; + } + + /* If the device is RCiEP and RCEC, set RP as 0xff */ + if ((dp_type == RCiEP) || (dp_type == RCEC)) + { + *rp_bdf = 0xffffffff; + return 1; + } + + while (index < g_pcie_bdf_table->num_entries) + { + *rp_bdf = g_pcie_bdf_table->device[index++].bdf; + + /* + * Extract Secondary and Subordinate Bus numbers of the + * upstream Root port and check if the input function's + * bus number falls within that range. + */ + val_pcie_read_cfg(*rp_bdf, TYPE1_PBN, ®_value); + sec_bus = ((reg_value >> SECBN_SHIFT) & SECBN_MASK); + sub_bus = ((reg_value >> SUBBN_SHIFT) & SUBBN_MASK); + + if ((val_pcie_device_port_type(*rp_bdf) == RP) && + (sec_bus <= PCIE_EXTRACT_BDF_BUS(bdf)) && + (sub_bus >= PCIE_EXTRACT_BDF_BUS(bdf))) + return 0; + } + + /* Return failure */ + val_print(AVS_PRINT_DEBUG, "\n Root port of Function (bdf: 0x%x) Not found ", bdf); + *rp_bdf = 0; + return 1; + +} + +uint8_t +val_pcie_parent_is_rootport(uint32_t dsf_bdf, uint32_t *rp_bdf) +{ + + uint8_t dsf_bus; + uint32_t bdf; + uint32_t dp_type; + uint32_t tbl_index; + uint32_t reg_value; + pcie_device_bdf_table *bdf_tbl_ptr; + + tbl_index = 0; + dsf_bus = PCIE_EXTRACT_BDF_BUS(dsf_bdf); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + while (tbl_index < bdf_tbl_ptr->num_entries) + { + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + dp_type = val_pcie_device_port_type(bdf); + + /* Check if this table entry is a Root Port */ + if (dp_type == RP) + { + /* Check if exerciser is a direct child of this root port */ + val_pcie_read_cfg(bdf, TYPE1_PBN, ®_value); + if ((dsf_bus == ((reg_value >> SECBN_SHIFT) & SECBN_MASK)) && + (dsf_bus <= ((reg_value >> SUBBN_SHIFT) & SUBBN_MASK))) + { + *rp_bdf = bdf; + return 0; + } + } + } + + return 1; +} diff --git a/val/src/avs_status.c b/val/src/avs_status.c index 6d23b177..3cf64df1 100644 --- a/val/src/avs_status.c +++ b/val/src/avs_status.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -41,10 +41,10 @@ val_report_status(uint32_t index, uint32_t status) val_print(AVS_PRINT_TEST, ": Result: PASS \n", status); else if (IS_TEST_FAIL(status)) - val_print(AVS_PRINT_ERR, ": Result: --FAIL-- %x \n", status & 0xFFFF); + val_print(AVS_PRINT_ERR, ": Result: --FAIL-- %x \n", status & STATUS_MASK); else if (IS_TEST_SKIP(status)) - val_print(AVS_PRINT_WARN, ": Result: -SKIPPED- %x \n", status & 0xFFFF); + val_print(AVS_PRINT_WARN, ": Result: -SKIPPED- %x \n", status & STATUS_MASK); else if (IS_TEST_START(status)) val_print(AVS_PRINT_INFO, " START ", status); diff --git a/val/src/avs_test_infra.c b/val/src/avs_test_infra.c index acefcf4b..37c908ee 100644 --- a/val/src/avs_test_infra.c +++ b/val/src/avs_test_infra.c @@ -414,3 +414,48 @@ val_debug_brk(uint32_t data) addr_t address = 0x9000F000; // address = pal_get_debug_address(); *(addr_t *)address = data; } + +/** + @brief Compares two strings + + @param str1 The pointer to a Null-terminated ASCII string. + @param str2 The pointer to a Null-terminated ASCII string. + @param len The maximum number of ASCII characters for compare. + + @return Zero if strings are identical, else non-zero value +**/ +uint32_t +val_strncmp(char8_t *str1, char8_t *str2, uint32_t len) +{ + return pal_strncmp(str1, str2, len); +} + +/** + Copies a source buffer to a destination buffer, and returns the destination buffer. + + @param DestinationBuffer The pointer to the destination buffer of the memory copy. + @param SourceBuffer The pointer to the source buffer of the memory copy. + @param Length The number of bytes to copy from SourceBuffer to DestinationBuffer. + + @return DestinationBuffer. + +**/ +void* +val_memcpy(void *dst_buffer, void *src_buffer, uint32_t len) +{ + return pal_memcpy(dst_buffer, src_buffer, len); +} + +/** + Stalls the CPU for the number of microseconds specified by MicroSeconds. + + @param MicroSeconds The minimum number of microseconds to delay. + + @return The value of MicroSeconds inputted. + +**/ +uint64_t +val_time_delay_ms(uint64_t timer_ms) +{ + return pal_time_delay_ms(timer_ms); +} diff --git a/val/src/avs_timer.c b/val/src/avs_timer.c index 167c6819..3bfd8e5f 100644 --- a/val/src/avs_timer.c +++ b/val/src/avs_timer.c @@ -117,7 +117,7 @@ val_timer_get_info(TIMER_INFO_e info_type, uint64_t instance) if (block_num != 0xFFFF) return g_timer_info_table->gt_info[block_num].GtCntBase[block_index]; case TIMER_INFO_FRAME_NUM: - val_platform_timer_get_entry_index (instance, &block_num, &block_index); + val_platform_timer_get_entry_index (instance, &block_num, &block_index); if (block_num != 0xFFFF) return g_timer_info_table->gt_info[block_num].frame_num[block_index]; case TIMER_INFO_SYS_INTID: @@ -361,13 +361,12 @@ val_timer_skip_if_cntbase_access_not_allowed(uint64_t index) frame_num = val_timer_get_info(TIMER_INFO_FRAME_NUM, index); if(cnt_ctl_base){ - /* should we also check if this frame is non-secure before accessing this register? */ data = val_mmio_read(cnt_ctl_base + 0x40 + frame_num * 4); if((data & 0x1) == 0x1) return 0; else{ data |= 0x1; - val_mmio_write(cnt_ctl_base + 0x40 + frame_num * 4, data); + val_mmio_write(cnt_ctl_base + 0x40 + frame_num *4, data); data = val_mmio_read(cnt_ctl_base + 0x40 + frame_num * 4); if((data & 0x1) == 1) return 0;